axi_dmac: Fix some data width mismatches

Make sure that the right hand side expression of assignments is not wider
than the target signal. This avoids warnings about implicit truncations.

None of these changes affect the behaviour, just fixes some warnings about
implicit signal truncation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/axi_dmac/address_generator.v

@@ -70,7 +70,8 @@ module dmac_address_generator #(
   output     [ 3:0]            cache
 );
 
-localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH);
+localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};
+localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}};
 
 `include "inc_id.h"
 
@@ -78,7 +79,13 @@ assign burst = 2'b01;
 assign prot = 3'b000;
 assign cache = 4'b0011;
 assign len = length;
-assign size = $clog2(DMA_DATA_WIDTH/8);
+assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 :
+              DMA_DATA_WIDTH ==  512 ? 3'b110 :
+              DMA_DATA_WIDTH ==  256 ? 3'b101 :
+              DMA_DATA_WIDTH ==  128 ? 3'b100 :
+              DMA_DATA_WIDTH ==   64 ? 3'b011 :
+              DMA_DATA_WIDTH ==   32 ? 3'b010 :
+              DMA_DATA_WIDTH ==   16 ? 3'b001 : 3'b000;
 
 reg [LENGTH_WIDTH-1:0] length = 'h0;
 reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00;
@@ -106,7 +113,7 @@ always @(posedge clk) begin
     if (eot == 1'b1)
       length <= last_burst_len;
     else
-      length <= MAX_BEATS_PER_BURST - 1;
+      length <= MAX_LENGTH;
   end
 end
 

library/axi_dmac/axi_dmac.v

@@ -272,7 +272,7 @@ reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00;
 reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
 reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
 reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
-reg up_dma_cyclic = CYCLIC;
+reg up_dma_cyclic = CYCLIC ? 1'b1 : 1'b0;
 wire up_dma_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0;
 
 // ID signals from the DMAC, just for debugging
@@ -339,7 +339,7 @@ up_axi #(
 // IRQ handling
 assign up_irq_pending = ~up_irq_mask & up_irq_source;
 assign up_irq_trigger  = {up_eot, up_sot};
-assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 9'h021) ? up_wdata[1:0] : 0;
+assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 9'h021) ? up_wdata[1:0] : 2'b00;
 
 always @(posedge s_axi_aclk)
 begin
@@ -371,7 +371,7 @@ begin
     up_dma_x_length <= 'h00;
     up_dma_dest_stride <= 'h00;
     up_dma_src_stride <= 'h00;
-    up_irq_mask <= 3'b11;
+    up_irq_mask <= 2'b11;
     up_dma_req_valid <= 1'b0;
     up_scratch <= 'h00;
     up_dma_cyclic <= 1'b0;
@@ -392,7 +392,7 @@ begin
     if (up_wreq) begin
       case (up_waddr)
       9'h002: up_scratch <= up_wdata;
-      9'h020: up_irq_mask <= up_wdata;
+      9'h020: up_irq_mask <= up_wdata[1:0];
       9'h100: {up_pause, up_enable} <= up_wdata[1:0];
                         9'h103: begin
                           if (CYCLIC) up_dma_cyclic <= up_wdata[0];

library/axi_dmac/data_mover.v

@@ -68,7 +68,7 @@ module dmac_data_mover #(
   input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
 );
 
-localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH);
+localparam BEAT_COUNTER_MAX = {BEATS_PER_BURST_WIDTH{1'b1}};
 
 `include "inc_id.h"
 
@@ -130,8 +130,8 @@ always @(posedge clk) begin
     beat_counter <= 'h1;
   end else if (s_axi_ready && s_axi_valid) begin
     last_eot <= beat_counter == last_burst_length;
-    last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1;
-    beat_counter <= beat_counter + 1;
+    last_non_eot <= beat_counter == BEAT_COUNTER_MAX;
+    beat_counter <= beat_counter + 1'b1;
   end
 end
 

library/axi_dmac/inc_id.h

@@ -59,8 +59,8 @@ function [ID_WIDTH-1:0] b2g;
 	end
 endfunction
 
-function [ID_WIDTH:0] inc_id;
-input [ID_WIDTH:0] id;
+function [ID_WIDTH-1:0] inc_id;
+input [ID_WIDTH-1:0] id;
 begin
 	inc_id = b2g(g2b(id) + 1);
 end