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library/axi_ad9361: add rst/locked to clock

main
Rejeesh Kutty 2016-05-04 13:38:53 -04:00
parent 1aac44b0d9
commit 16a13b2023
2 changed files with 26 additions and 2 deletions
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14
library/axi_ad9361/axi_ad9361_cmos_if.v
View File

@ -84,6 +84,7 @@ module axi_ad9361_cmos_if (
// delay interface // delay interface
mmcm_rst,
up_clk, up_clk,
up_enable, up_enable,
up_txnrx, up_txnrx,
@ -148,6 +149,7 @@ module axi_ad9361_cmos_if (
// delay interface // delay interface
input mmcm_rst;
input up_clk; input up_clk;
input up_enable; input up_enable;
input up_txnrx; input up_txnrx;
@ -209,6 +211,8 @@ module axi_ad9361_cmos_if (
reg txnrx_n_int = 'd0; reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0; reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0; reg txnrx_p_int = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
// internal signals // internal signals
@ -219,6 +223,7 @@ module axi_ad9361_cmos_if (
wire [11:0] rx_data_n_s; wire [11:0] rx_data_n_s;
wire rx_frame_p_s; wire rx_frame_p_s;
wire rx_frame_n_s; wire rx_frame_n_s;
wire locked_s;
genvar l_inst; genvar l_inst;
@ -293,7 +298,7 @@ module axi_ad9361_cmos_if (
if (adc_valid_int == 1'b1) begin if (adc_valid_int == 1'b1) begin
adc_data <= adc_data_int; adc_data <= adc_data_int;
end end
adc_status <= adc_status_int; adc_status <= adc_status_int & locked;
end end
// transmit data path mux (reverse of what receive does above) // transmit data path mux (reverse of what receive does above)
@ -550,9 +555,16 @@ module axi_ad9361_cmos_if (
// device clock interface (receive clock) // device clock interface (receive clock)
always @(posedge clk) begin
locked_m1 <= locked_s;
locked <= locked_m1;
end
ad_cmos_clk #( ad_cmos_clk #(
.DEVICE_TYPE (DEVICE_TYPE)) .DEVICE_TYPE (DEVICE_TYPE))
i_clk ( i_clk (
.rst (mmcm_rst),
.locked (locked_s),
.clk_in (rx_clk_in), .clk_in (rx_clk_in),
.clk (l_clk)); .clk (l_clk));

14
library/axi_ad9361/axi_ad9361_lvds_if.v
View File

@ -90,6 +90,7 @@ module axi_ad9361_lvds_if (
// delay interface // delay interface
mmcm_rst,
up_clk, up_clk,
up_enable, up_enable,
up_txnrx, up_txnrx,
@ -160,6 +161,7 @@ module axi_ad9361_lvds_if (
// delay interface // delay interface
input mmcm_rst;
input up_clk; input up_clk;
input up_enable; input up_enable;
input up_txnrx; input up_txnrx;
@ -225,6 +227,8 @@ module axi_ad9361_lvds_if (
reg txnrx_n_int = 'd0; reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0; reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0; reg txnrx_p_int = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
// internal signals // internal signals
@ -235,6 +239,7 @@ module axi_ad9361_lvds_if (
wire [ 5:0] rx_data_n_s; wire [ 5:0] rx_data_n_s;
wire rx_frame_p_s; wire rx_frame_p_s;
wire rx_frame_n_s; wire rx_frame_n_s;
wire locked_s;
genvar l_inst; genvar l_inst;
@ -326,7 +331,7 @@ module axi_ad9361_lvds_if (
if (adc_valid_int == 1'b1) begin if (adc_valid_int == 1'b1) begin
adc_data <= adc_data_int; adc_data <= adc_data_int;
end end
adc_status <= adc_status_int; adc_status <= adc_status_int & locked;
end end
// transmit data path mux (reverse of what receive does above) // transmit data path mux (reverse of what receive does above)
@ -605,9 +610,16 @@ module axi_ad9361_lvds_if (
// device clock interface (receive clock) // device clock interface (receive clock)
always @(posedge clk) begin
locked_m1 <= locked_s;
locked <= locked_m1;
end
ad_lvds_clk #( ad_lvds_clk #(
.DEVICE_TYPE (DEVICE_TYPE)) .DEVICE_TYPE (DEVICE_TYPE))
i_clk ( i_clk (
.rst (mmcm_rst),
.locked (locked_s),
.clk_in_p (rx_clk_in_p), .clk_in_p (rx_clk_in_p),
.clk_in_n (rx_clk_in_n), .clk_in_n (rx_clk_in_n),
.clk (l_clk)); .clk (l_clk));