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pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2

main
Adrian Costina 2017-01-18 12:01:24 +02:00
parent 319a883c00
commit 165ba76d9d
6 changed files with 85 additions and 20 deletions
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6
projects/pzsdr1/ccbox_lvds/Makefile
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@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac
make -C ../../../library/axi_i2s_adi
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo

6
projects/pzsdr1/ccbrk_cmos/Makefile
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@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_gpreg clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac
make -C ../../../library/axi_gpreg
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo

3
projects/pzsdr1/ccbrk_cmos/system_bd.tcl
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@ -2,5 +2,8 @@
source ../common/pzsdr1_bd.tcl
source ../common/ccbrk_bd.tcl
set_property -dict [list CONFIG.SEL_0_DIV {BYPASS}] $clkdiv
set_property -dict [list CONFIG.SEL_1_DIV {BYPASS}] $clkdiv
cfg_ad9361_interface CMOS

6
projects/pzsdr1/ccbrk_lvds/Makefile
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@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_gpreg clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac
make -C ../../../library/axi_gpreg
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo

6
projects/pzsdr1/ccusb_lvds/Makefile
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@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_usb_fx3 clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac
make -C ../../../library/axi_usb_fx3
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo

78
projects/pzsdr1/common/pzsdr1_bd.tcl
View File

@ -242,6 +242,21 @@ set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic
set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic
# connections
ad_connect sys_200m_clk axi_ad9361/delay_clk
@ -253,11 +268,14 @@ ad_connect up_enable axi_ad9361/up_enable
ad_connect up_txnrx axi_ad9361/up_txnrx
ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk
ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk
ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst
ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
ad_connect axi_ad9361_clk clkdiv/clk
ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk
ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out
ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset
ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn
ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
@ -287,23 +305,43 @@ ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk
ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect axi_ad9361/adc_r1_mode concat_logic/In0
ad_connect axi_ad9361/dac_r1_mode concat_logic/In1
ad_connect concat_logic/dout clkdiv_sel_logic/Op1
ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf
ad_connect dac_fifo/din_clk clkdiv/clk_out
ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn
ad_connect axi_ad9361_clk dac_fifo/dout_clk
ad_connect dac_fifo/dout_rst axi_ad9361/rst
ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out
ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0
ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0
ad_connect dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0
ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1
ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1
ad_connect dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1
ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2
ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2
ad_connect dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2
ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3
ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3
ad_connect dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3
ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0
ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0
ad_connect axi_ad9361/dac_data_i0 dac_fifo/dout_data_0
ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1
ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1
ad_connect axi_ad9361/dac_data_q0 dac_fifo/dout_data_1
ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2
ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2
ad_connect axi_ad9361/dac_data_i1 dac_fifo/dout_data_2
ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3
ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3
ad_connect axi_ad9361/dac_data_q1 dac_fifo/dout_data_3
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync