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fmcadc4- ad9680 version

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Rejeesh Kutty 2015-05-11 13:54:43 -04:00
parent 2cd1d8a591
commit 16541335e6
1 changed files with 6 additions and 6 deletions
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12
projects/fmcadc4/zc706/system_bd.tcl
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@ -2,7 +2,7 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
p_plddr3_fifo [current_bd_instance .] axi_ad9234_fifo 256
p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 256
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
@ -10,13 +10,13 @@ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sy
set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9234_fifo/sys_rst
ad_connect sys_clk axi_ad9234_fifo/sys_clk
ad_connect ddr3 axi_ad9234_fifo/ddr3
ad_connect sys_rst axi_ad9680_fifo/sys_rst
ad_connect sys_clk axi_ad9680_fifo/sys_clk
ad_connect ddr3 axi_ad9680_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9234_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9234_fifo/axi_ddr_cntrl/memmap/memaddr] \
[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/fmcadc4_bd.tcl