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ad_datafmt: Fix Quartus warnings 

Fix the following warnings that are generated by Quartus:
	Warning (10036): Verilog HDL or VHDL warning at ad_datafmt.v(69): object "sign_s" assigned a value but never read

Move the sign_s and signext_s signals into the generate block in which
they are used.

No functional changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-04-11 14:00:57 +02:00 committed by Lars-Peter Clausen
parent b555218152
commit 162248375c
1 changed files with 7 additions and 6 deletions
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9
library/common/ad_datafmt.v
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@ -65,8 +65,6 @@ module ad_datafmt #(
// internal signals
wire type_s;
wire signext_s;
wire sign_s;
wire [15:0] data_out_s;
// data-path disable
@ -84,11 +82,14 @@ module ad_datafmt #(
// if offset-binary convert to 2's complement first
assign type_s = dfmt_enable & dfmt_type;
assign signext_s = dfmt_enable & dfmt_se;
assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
generate
if (DATA_WIDTH < 16) begin
wire signext_s;
wire sign_s;
assign signext_s = dfmt_enable & dfmt_se;
assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
end
endgenerate