ad_datafmt: Fix Quartus warnings
Fix the following warnings that are generated by Quartus: Warning (10036): Verilog HDL or VHDL warning at ad_datafmt.v(69): object "sign_s" assigned a value but never read Move the sign_s and signext_s signals into the generate block in which they are used. No functional changes. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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b555218152
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162248375c
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@ -65,8 +65,6 @@ module ad_datafmt #(
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// internal signals
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// internal signals
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wire type_s;
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wire type_s;
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wire signext_s;
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wire sign_s;
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wire [15:0] data_out_s;
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wire [15:0] data_out_s;
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// data-path disable
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// data-path disable
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@ -84,12 +82,15 @@ module ad_datafmt #(
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// if offset-binary convert to 2's complement first
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// if offset-binary convert to 2's complement first
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assign type_s = dfmt_enable & dfmt_type;
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assign type_s = dfmt_enable & dfmt_type;
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assign signext_s = dfmt_enable & dfmt_se;
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assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
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generate
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generate
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if (DATA_WIDTH < 16) begin
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if (DATA_WIDTH < 16) begin
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assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
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wire signext_s;
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wire sign_s;
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assign signext_s = dfmt_enable & dfmt_se;
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assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
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assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
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end
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end
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endgenerate
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endgenerate
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