From 162248375c635e746931e4a5a5fcceeaface1c5f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 11 Apr 2018 14:00:57 +0200 Subject: [PATCH] ad_datafmt: Fix Quartus warnings Fix the following warnings that are generated by Quartus: Warning (10036): Verilog HDL or VHDL warning at ad_datafmt.v(69): object "sign_s" assigned a value but never read Move the sign_s and signext_s signals into the generate block in which they are used. No functional changes. Signed-off-by: Lars-Peter Clausen --- library/common/ad_datafmt.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/library/common/ad_datafmt.v b/library/common/ad_datafmt.v index 65e32e0ad..0d47f7f84 100644 --- a/library/common/ad_datafmt.v +++ b/library/common/ad_datafmt.v @@ -65,8 +65,6 @@ module ad_datafmt #( // internal signals wire type_s; - wire signext_s; - wire sign_s; wire [15:0] data_out_s; // data-path disable @@ -84,15 +82,18 @@ module ad_datafmt #( // if offset-binary convert to 2's complement first assign type_s = dfmt_enable & dfmt_type; - assign signext_s = dfmt_enable & dfmt_se; - assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]); generate if (DATA_WIDTH < 16) begin - assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}}; + wire signext_s; + wire sign_s; + + assign signext_s = dfmt_enable & dfmt_se; + assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]); + assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}}; end endgenerate - + assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)]; assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0];