fmcadc4: Update project to the new JESD interface framework
Istvan Csomortani
parent
f4b432da08
commit
1604e88242
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@ -7,23 +7,6 @@ create_bd_port -dir I rx_sysref
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create_bd_port -dir I -from 7 -to 0 rx_data_p
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create_bd_port -dir I -from 7 -to 0 rx_data_n
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_enable_0
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create_bd_port -dir O adc_valid_0
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create_bd_port -dir O -from 63 -to 0 adc_data_0
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create_bd_port -dir O adc_enable_1
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create_bd_port -dir O adc_valid_1
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create_bd_port -dir O -from 63 -to 0 adc_data_1
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create_bd_port -dir O adc_enable_2
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create_bd_port -dir O adc_valid_2
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create_bd_port -dir O -from 63 -to 0 adc_data_2
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create_bd_port -dir O adc_enable_3
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create_bd_port -dir O adc_valid_3
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create_bd_port -dir O -from 63 -to 0 adc_data_3
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create_bd_port -dir I adc_dwr
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create_bd_port -dir I adc_dsync
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create_bd_port -dir I -from 255 -to 0 adc_ddata
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# adc peripherals
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set axi_ad9680_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_0]
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@ -48,123 +31,112 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
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# dac/adc common gt
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set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9680_cpack
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# adc common gt
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set axi_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc4_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_fmcadc4_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc4_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc4_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc4_gt
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set util_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc4_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc4_gt
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# connections (gt)
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ad_connect axi_fmcadc4_gt/ref_clk_q rx_ref_clk
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ad_connect axi_fmcadc4_gt/rx_data_p rx_data_p
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ad_connect axi_fmcadc4_gt/rx_data_n rx_data_n
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ad_connect axi_fmcadc4_gt/rx_sync rx_sync
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ad_connect axi_fmcadc4_gt/rx_ext_sysref rx_sysref
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ad_connect util_fmcadc4_gt/qpll_ref_clk rx_ref_clk
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ad_connect axi_fmcadc4_gt/gt_qpll_0 util_fmcadc4_gt/gt_qpll_0
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ad_connect axi_fmcadc4_gt/gt_qpll_1 util_fmcadc4_gt/gt_qpll_1
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ad_connect axi_fmcadc4_gt/gt_pll_0 util_fmcadc4_gt/gt_pll_0
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ad_connect axi_fmcadc4_gt/gt_pll_1 util_fmcadc4_gt/gt_pll_1
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ad_connect axi_fmcadc4_gt/gt_pll_2 util_fmcadc4_gt/gt_pll_2
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ad_connect axi_fmcadc4_gt/gt_pll_3 util_fmcadc4_gt/gt_pll_3
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ad_connect axi_fmcadc4_gt/gt_pll_4 util_fmcadc4_gt/gt_pll_4
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ad_connect axi_fmcadc4_gt/gt_pll_5 util_fmcadc4_gt/gt_pll_5
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ad_connect axi_fmcadc4_gt/gt_pll_6 util_fmcadc4_gt/gt_pll_6
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ad_connect axi_fmcadc4_gt/gt_pll_7 util_fmcadc4_gt/gt_pll_7
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ad_connect axi_fmcadc4_gt/gt_rx_0 util_fmcadc4_gt/gt_rx_0
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ad_connect axi_fmcadc4_gt/gt_rx_1 util_fmcadc4_gt/gt_rx_1
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ad_connect axi_fmcadc4_gt/gt_rx_2 util_fmcadc4_gt/gt_rx_2
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ad_connect axi_fmcadc4_gt/gt_rx_3 util_fmcadc4_gt/gt_rx_3
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ad_connect axi_fmcadc4_gt/gt_rx_4 util_fmcadc4_gt/gt_rx_4
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ad_connect axi_fmcadc4_gt/gt_rx_5 util_fmcadc4_gt/gt_rx_5
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ad_connect axi_fmcadc4_gt/gt_rx_6 util_fmcadc4_gt/gt_rx_6
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ad_connect axi_fmcadc4_gt/gt_rx_7 util_fmcadc4_gt/gt_rx_7
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ad_connect axi_fmcadc4_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_4 axi_ad9680_jesd/gt4_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_5 axi_ad9680_jesd/gt5_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_6 axi_ad9680_jesd/gt6_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_7 axi_ad9680_jesd/gt7_rx
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_4 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_5 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_6 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_7 axi_ad9680_jesd/rxencommaalign_out
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# connections (adc)
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ad_connect axi_fmcadc4_gt/rx_clk_g adc_clk
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ad_connect axi_fmcadc4_gt/tx_clk_g axi_fmcadc4_gt/tx_clk
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ad_connect axi_fmcadc4_gt/rx_clk_g axi_fmcadc4_gt/rx_clk
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ad_connect axi_fmcadc4_gt/rx_clk_g axi_ad9680_core_0/rx_clk
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ad_connect axi_fmcadc4_gt/rx_clk_g axi_ad9680_core_1/rx_clk
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ad_connect axi_fmcadc4_gt/rx_clk_g axi_ad9680_jesd/rx_core_clk
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ad_connect axi_fmcadc4_gt/rx_rst axi_ad9680_jesd/rx_reset
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ad_connect axi_fmcadc4_gt/rx_sysref axi_ad9680_jesd/rx_sysref
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_charisk]
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ad_connect util_bsplit_rx_gt_charisk/data axi_fmcadc4_gt/rx_gt_charisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9680_jesd/gt0_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9680_jesd/gt1_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_ad9680_jesd/gt2_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_ad9680_jesd/gt3_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_4 axi_ad9680_jesd/gt4_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_5 axi_ad9680_jesd/gt5_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_6 axi_ad9680_jesd/gt6_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_7 axi_ad9680_jesd/gt7_rxcharisk
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_disperr]
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ad_connect util_bsplit_rx_gt_disperr/data axi_fmcadc4_gt/rx_gt_disperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9680_jesd/gt0_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad9680_jesd/gt1_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_ad9680_jesd/gt2_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_ad9680_jesd/gt3_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_4 axi_ad9680_jesd/gt4_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_5 axi_ad9680_jesd/gt5_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_6 axi_ad9680_jesd/gt6_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_7 axi_ad9680_jesd/gt7_rxdisperr
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_notintable]
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ad_connect util_bsplit_rx_gt_notintable/data axi_fmcadc4_gt/rx_gt_notintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9680_jesd/gt0_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9680_jesd/gt1_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_ad9680_jesd/gt2_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_ad9680_jesd/gt3_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_4 axi_ad9680_jesd/gt4_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_5 axi_ad9680_jesd/gt5_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_6 axi_ad9680_jesd/gt6_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_7 axi_ad9680_jesd/gt7_rxnotintable
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_data]
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ad_connect util_bsplit_rx_gt_data/data axi_fmcadc4_gt/rx_gt_data
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ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9680_jesd/gt0_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9680_jesd/gt1_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_2 axi_ad9680_jesd/gt2_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_3 axi_ad9680_jesd/gt3_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_4 axi_ad9680_jesd/gt4_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_5 axi_ad9680_jesd/gt5_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_6 axi_ad9680_jesd/gt6_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_7 axi_ad9680_jesd/gt7_rxdata
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ad_connect axi_fmcadc4_gt/rx_rst_done axi_ad9680_jesd/rx_reset_done
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ad_connect axi_fmcadc4_gt/rx_ip_comma_align axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
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ad_connect axi_fmcadc4_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
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ad_connect axi_fmcadc4_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
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ad_connect util_fmcadc4_gt/rx_sysref rx_sysref
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ad_connect util_fmcadc4_gt/rx_p rx_data_p
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ad_connect util_fmcadc4_gt/rx_n rx_data_n
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ad_connect util_fmcadc4_gt/rx_sync rx_sync
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ad_connect util_fmcadc4_gt/rx_out_clk util_fmcadc4_gt/rx_clk
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ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
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ad_connect util_fmcadc4_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
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ad_connect util_fmcadc4_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
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ad_connect util_fmcadc4_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
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ad_connect util_fmcadc4_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
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ad_connect util_fmcadc4_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
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ad_connect util_fmcadc4_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_data
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {128}] [get_bd_cells util_bsplit_rx_data]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_data]
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ad_connect util_bsplit_rx_data/data axi_fmcadc4_gt/rx_data
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ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_core_0/rx_clk
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ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_core_1/rx_clk
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ad_connect util_fmcadc4_gt/rx_data util_bsplit_rx_data/data
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ad_connect util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data
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ad_connect util_bsplit_rx_data/split_data_1 axi_ad9680_core_1/rx_data
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ad_connect axi_ad9680_core_0/adc_enable_0 adc_enable_0
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ad_connect axi_ad9680_core_0/adc_valid_0 adc_valid_0
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ad_connect axi_ad9680_core_0/adc_data_0 adc_data_0
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ad_connect axi_ad9680_core_0/adc_enable_1 adc_enable_1
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ad_connect axi_ad9680_core_0/adc_valid_1 adc_valid_1
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ad_connect axi_ad9680_core_0/adc_data_1 adc_data_1
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ad_connect axi_ad9680_core_1/adc_enable_0 adc_enable_2
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ad_connect axi_ad9680_core_1/adc_valid_0 adc_valid_2
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ad_connect axi_ad9680_core_1/adc_data_0 adc_data_2
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ad_connect axi_ad9680_core_1/adc_enable_1 adc_enable_3
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ad_connect axi_ad9680_core_1/adc_valid_1 adc_valid_3
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ad_connect axi_ad9680_core_1/adc_data_1 adc_data_3
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ad_connect axi_ad9680_fifo/adc_rst axi_fmcadc4_gt/rx_rst
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ad_connect axi_ad9680_core_0/adc_clk axi_ad9680_cpack/adc_clk
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ad_connect util_fmcadc4_gt/rx_rst axi_ad9680_cpack/adc_rst
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ad_connect axi_ad9680_core_0/adc_enable_0 axi_ad9680_cpack/adc_enable_0
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ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/adc_valid_0
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ad_connect axi_ad9680_core_0/adc_data_0 axi_ad9680_cpack/adc_data_0
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ad_connect axi_ad9680_core_0/adc_enable_1 axi_ad9680_cpack/adc_enable_1
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ad_connect axi_ad9680_core_0/adc_valid_1 axi_ad9680_cpack/adc_valid_1
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ad_connect axi_ad9680_core_0/adc_data_1 axi_ad9680_cpack/adc_data_1
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ad_connect axi_ad9680_core_1/adc_enable_0 axi_ad9680_cpack/adc_enable_2
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ad_connect axi_ad9680_core_1/adc_valid_0 axi_ad9680_cpack/adc_valid_2
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ad_connect axi_ad9680_core_1/adc_data_0 axi_ad9680_cpack/adc_data_2
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ad_connect axi_ad9680_core_1/adc_enable_1 axi_ad9680_cpack/adc_enable_3
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ad_connect axi_ad9680_core_1/adc_valid_1 axi_ad9680_cpack/adc_valid_3
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ad_connect axi_ad9680_core_1/adc_data_1 axi_ad9680_cpack/adc_data_3
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ad_connect axi_ad9680_core_0/adc_clk axi_ad9680_fifo/adc_clk
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ad_connect axi_ad9680_core_0/adc_dovf axi_ad9680_fifo/adc_wovf
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ad_connect adc_dwr axi_ad9680_fifo/adc_wr
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ad_connect adc_ddata axi_ad9680_fifo/adc_wdata
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ad_connect util_fmcadc4_gt/rx_rst axi_ad9680_fifo/adc_rst
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ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
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ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
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ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
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ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
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ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
|
||||
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
|
||||
ad_connect axi_ad9680_core_0/adc_dovf axi_ad9680_fifo/adc_wovf
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
@ -183,9 +155,8 @@ ad_mem_hp3_interconnect sys_cpu_clk axi_fmcadc4_gt/m_axi
|
|||
|
||||
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
|
||||
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-13 mb-13 axi_ad9680_dma/irq
|
||||
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
|
||||
|
||||
|
|
|
|||
|
|
@ -46,5 +46,5 @@ set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9680_2
|
|||
# clocks
|
||||
|
||||
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcadc4_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcadc4_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
|
|
@ -21,16 +21,16 @@
|
|||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -71,7 +71,7 @@ module system_top (
|
|||
hdmi_hsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
|
||||
spdif,
|
||||
|
||||
sys_rst,
|
||||
|
|
@ -107,14 +107,14 @@ module system_top (
|
|||
rx_sync_1_n,
|
||||
rx_data_p,
|
||||
rx_data_n,
|
||||
|
||||
|
||||
ad9528_rstn,
|
||||
ad9528_status,
|
||||
ad9680_1_fda,
|
||||
ad9680_1_fdb,
|
||||
ad9680_2_fda,
|
||||
ad9680_2_fdb,
|
||||
|
||||
|
||||
ad9528_csn,
|
||||
ada4961_1a_csn,
|
||||
ada4961_1b_csn,
|
||||
|
|
@ -155,7 +155,7 @@ module system_top (
|
|||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [23:0] hdmi_data;
|
||||
|
||||
|
||||
output spdif;
|
||||
|
||||
input sys_rst;
|
||||
|
|
@ -191,14 +191,14 @@ module system_top (
|
|||
output rx_sync_1_n;
|
||||
input [ 7:0] rx_data_p;
|
||||
input [ 7:0] rx_data_n;
|
||||
|
||||
|
||||
inout ad9528_rstn;
|
||||
inout ad9528_status;
|
||||
inout ad9680_1_fda;
|
||||
inout ad9680_1_fdb;
|
||||
inout ad9680_2_fda;
|
||||
inout ad9680_2_fdb;
|
||||
|
||||
|
||||
output ad9528_csn;
|
||||
output ada4961_1a_csn;
|
||||
output ada4961_1b_csn;
|
||||
|
|
@ -209,13 +209,6 @@ module system_top (
|
|||
output spi_clk;
|
||||
inout spi_sdio;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 1:0] adc_dcnt = 'd0;
|
||||
reg adc_dsync = 'd0;
|
||||
reg adc_dwr = 'd0;
|
||||
reg [255:0] adc_ddata = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
|
|
@ -232,172 +225,6 @@ module system_top (
|
|||
wire rx_ref_clk;
|
||||
wire rx_sysref;
|
||||
wire rx_sync;
|
||||
wire adc_clk;
|
||||
wire [63:0] adc_data_0;
|
||||
wire [63:0] adc_data_1;
|
||||
wire [63:0] adc_data_2;
|
||||
wire [63:0] adc_data_3;
|
||||
wire adc_enable_0;
|
||||
wire adc_enable_1;
|
||||
wire adc_enable_2;
|
||||
wire adc_enable_3;
|
||||
wire adc_valid_0;
|
||||
wire adc_valid_1;
|
||||
wire adc_valid_2;
|
||||
wire adc_valid_3;
|
||||
|
||||
// adc-pack place holder
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_dcnt <= adc_dcnt + 1'b1;
|
||||
case ({adc_enable_3, adc_enable_2, adc_enable_1, adc_enable_0})
|
||||
4'b1111: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_3 & adc_valid_2 & adc_valid_1 & adc_valid_0;
|
||||
adc_ddata[255:240] <= $signed(adc_data_3[63:52]);
|
||||
adc_ddata[239:224] <= $signed(adc_data_2[63:52]);
|
||||
adc_ddata[223:208] <= $signed(adc_data_1[63:52]);
|
||||
adc_ddata[207:192] <= $signed(adc_data_0[63:52]);
|
||||
adc_ddata[191:176] <= $signed(adc_data_3[47:36]);
|
||||
adc_ddata[175:160] <= $signed(adc_data_2[47:36]);
|
||||
adc_ddata[159:144] <= $signed(adc_data_1[47:36]);
|
||||
adc_ddata[143:128] <= $signed(adc_data_0[47:36]);
|
||||
adc_ddata[127:112] <= $signed(adc_data_3[31:20]);
|
||||
adc_ddata[111: 96] <= $signed(adc_data_2[31:20]);
|
||||
adc_ddata[ 95: 80] <= $signed(adc_data_1[31:20]);
|
||||
adc_ddata[ 79: 64] <= $signed(adc_data_0[31:20]);
|
||||
adc_ddata[ 63: 48] <= $signed(adc_data_3[15: 4]);
|
||||
adc_ddata[ 47: 32] <= $signed(adc_data_2[15: 4]);
|
||||
adc_ddata[ 31: 16] <= $signed(adc_data_1[15: 4]);
|
||||
adc_ddata[ 15: 0] <= $signed(adc_data_0[15: 4]);
|
||||
end
|
||||
4'b0001: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_0 & adc_dcnt[0] & adc_dcnt[1];
|
||||
adc_ddata[255:240] <= $signed(adc_data_0[63:52]);
|
||||
adc_ddata[239:224] <= $signed(adc_data_0[47:36]);
|
||||
adc_ddata[223:208] <= $signed(adc_data_0[31:20]);
|
||||
adc_ddata[207:192] <= $signed(adc_data_0[15: 4]);
|
||||
adc_ddata[191:176] <= adc_ddata[255:240];
|
||||
adc_ddata[175:160] <= adc_ddata[239:224];
|
||||
adc_ddata[159:144] <= adc_ddata[223:208];
|
||||
adc_ddata[143:128] <= adc_ddata[207:192];
|
||||
adc_ddata[127:112] <= adc_ddata[191:176];
|
||||
adc_ddata[111: 96] <= adc_ddata[175:160];
|
||||
adc_ddata[ 95: 80] <= adc_ddata[159:144];
|
||||
adc_ddata[ 79: 64] <= adc_ddata[143:128];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||
end
|
||||
4'b0010: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_1 & adc_dcnt[0] & adc_dcnt[1];
|
||||
adc_ddata[255:240] <= $signed(adc_data_1[63:52]);
|
||||
adc_ddata[239:224] <= $signed(adc_data_1[47:36]);
|
||||
adc_ddata[223:208] <= $signed(adc_data_1[31:20]);
|
||||
adc_ddata[207:192] <= $signed(adc_data_1[15: 4]);
|
||||
adc_ddata[191:176] <= adc_ddata[255:240];
|
||||
adc_ddata[175:160] <= adc_ddata[239:224];
|
||||
adc_ddata[159:144] <= adc_ddata[223:208];
|
||||
adc_ddata[143:128] <= adc_ddata[207:192];
|
||||
adc_ddata[127:112] <= adc_ddata[191:176];
|
||||
adc_ddata[111: 96] <= adc_ddata[175:160];
|
||||
adc_ddata[ 95: 80] <= adc_ddata[159:144];
|
||||
adc_ddata[ 79: 64] <= adc_ddata[143:128];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||
end
|
||||
4'b0011: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_1 & adc_valid_0 & adc_dcnt[0];
|
||||
adc_ddata[255:240] <= $signed(adc_data_1[63:52]);
|
||||
adc_ddata[239:224] <= $signed(adc_data_0[63:52]);
|
||||
adc_ddata[223:208] <= $signed(adc_data_1[47:36]);
|
||||
adc_ddata[207:192] <= $signed(adc_data_0[47:36]);
|
||||
adc_ddata[191:176] <= $signed(adc_data_1[31:20]);
|
||||
adc_ddata[175:160] <= $signed(adc_data_0[31:20]);
|
||||
adc_ddata[159:144] <= $signed(adc_data_1[15: 4]);
|
||||
adc_ddata[143:128] <= $signed(adc_data_0[15: 4]);
|
||||
adc_ddata[127:112] <= adc_ddata[255:240];
|
||||
adc_ddata[111: 96] <= adc_ddata[239:224];
|
||||
adc_ddata[ 95: 80] <= adc_ddata[223:208];
|
||||
adc_ddata[ 79: 64] <= adc_ddata[207:192];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[191:176];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[175:160];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[159:144];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[143:128];
|
||||
end
|
||||
4'b0100: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_2 & adc_dcnt[0] & adc_dcnt[1];
|
||||
adc_ddata[255:240] <= $signed(adc_data_2[63:52]);
|
||||
adc_ddata[239:224] <= $signed(adc_data_2[47:36]);
|
||||
adc_ddata[223:208] <= $signed(adc_data_2[31:20]);
|
||||
adc_ddata[207:192] <= $signed(adc_data_2[15: 4]);
|
||||
adc_ddata[191:176] <= adc_ddata[255:240];
|
||||
adc_ddata[175:160] <= adc_ddata[239:224];
|
||||
adc_ddata[159:144] <= adc_ddata[223:208];
|
||||
adc_ddata[143:128] <= adc_ddata[207:192];
|
||||
adc_ddata[127:112] <= adc_ddata[191:176];
|
||||
adc_ddata[111: 96] <= adc_ddata[175:160];
|
||||
adc_ddata[ 95: 80] <= adc_ddata[159:144];
|
||||
adc_ddata[ 79: 64] <= adc_ddata[143:128];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||
end
|
||||
4'b1000: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_3 & adc_dcnt[0] & adc_dcnt[1];
|
||||
adc_ddata[255:240] <= $signed(adc_data_3[63:52]);
|
||||
adc_ddata[239:224] <= $signed(adc_data_3[47:36]);
|
||||
adc_ddata[223:208] <= $signed(adc_data_3[31:20]);
|
||||
adc_ddata[207:192] <= $signed(adc_data_3[15: 4]);
|
||||
adc_ddata[191:176] <= adc_ddata[255:240];
|
||||
adc_ddata[175:160] <= adc_ddata[239:224];
|
||||
adc_ddata[159:144] <= adc_ddata[223:208];
|
||||
adc_ddata[143:128] <= adc_ddata[207:192];
|
||||
adc_ddata[127:112] <= adc_ddata[191:176];
|
||||
adc_ddata[111: 96] <= adc_ddata[175:160];
|
||||
adc_ddata[ 95: 80] <= adc_ddata[159:144];
|
||||
adc_ddata[ 79: 64] <= adc_ddata[143:128];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||
end
|
||||
4'b1100: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_3 & adc_valid_2 & adc_dcnt[0];
|
||||
adc_ddata[255:240] <= $signed(adc_data_3[63:52]);
|
||||
adc_ddata[239:224] <= $signed(adc_data_2[63:52]);
|
||||
adc_ddata[223:208] <= $signed(adc_data_3[47:36]);
|
||||
adc_ddata[207:192] <= $signed(adc_data_2[47:36]);
|
||||
adc_ddata[191:176] <= $signed(adc_data_3[31:20]);
|
||||
adc_ddata[175:160] <= $signed(adc_data_2[31:20]);
|
||||
adc_ddata[159:144] <= $signed(adc_data_3[15: 4]);
|
||||
adc_ddata[143:128] <= $signed(adc_data_2[15: 4]);
|
||||
adc_ddata[127:112] <= adc_ddata[255:240];
|
||||
adc_ddata[111: 96] <= adc_ddata[239:224];
|
||||
adc_ddata[ 95: 80] <= adc_ddata[223:208];
|
||||
adc_ddata[ 79: 64] <= adc_ddata[207:192];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[191:176];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[175:160];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[159:144];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[143:128];
|
||||
end
|
||||
default: begin
|
||||
adc_dsync <= 1'b0;
|
||||
adc_dwr <= 1'b0;
|
||||
adc_ddata <= 256'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// spi
|
||||
|
||||
|
|
@ -459,22 +286,6 @@ module system_top (
|
|||
.dio_p (gpio_bd));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_data_0 (adc_data_0),
|
||||
.adc_data_1 (adc_data_1),
|
||||
.adc_data_2 (adc_data_2),
|
||||
.adc_data_3 (adc_data_3),
|
||||
.adc_ddata (adc_ddata),
|
||||
.adc_dsync (adc_dsync),
|
||||
.adc_dwr (adc_dwr),
|
||||
.adc_enable_0 (adc_enable_0),
|
||||
.adc_enable_1 (adc_enable_1),
|
||||
.adc_enable_2 (adc_enable_2),
|
||||
.adc_enable_3 (adc_enable_3),
|
||||
.adc_valid_0 (adc_valid_0),
|
||||
.adc_valid_1 (adc_valid_1),
|
||||
.adc_valid_2 (adc_valid_2),
|
||||
.adc_valid_3 (adc_valid_3),
|
||||
.ddr3_addr (ddr3_addr),
|
||||
.ddr3_ba (ddr3_ba),
|
||||
.ddr3_cas_n (ddr3_cas_n),
|
||||
|
|
|
|||
Loading…
Reference in New Issue