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alt_serdes- updates

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Rejeesh Kutty 2016-09-14 12:05:48 -04:00
parent 4a6b554c0a
commit 16046a984c
3 changed files with 9 additions and 1 deletions
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3
library/altera/alt_serdes/alt_serdes_hw.tcl
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@ -131,10 +131,11 @@ proc p_alt_serdes {} {
set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate
set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor
set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
add_interface data_out conduit end
set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out
add_interface clk conduit end

3
library/altera/common/ad_serdes_clk.v
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@ -85,6 +85,9 @@ module ad_serdes_clk (
// defaults
assign out_clk = div_clk;
assign up_drp_rdata = up_drp_rdata_int;
assign up_drp_ready = up_drp_ready_int;
assign up_drp_locked = up_drp_locked_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin

4
library/altera/common/ad_serdes_in.v
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@ -79,6 +79,10 @@ module ad_serdes_in (
parameter DEVICE_TYPE = 0;
// assignments
assign up_drdata = 5'd0;
// instantiations
alt_serdes_in_core i_core (