ad4630_fmc: Initial commit
Istvan Csomortani
sarpadi
parent
6a526f4bb6
commit
15a6480601
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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# system level parameters
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set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
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set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE)
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set CLK_MODE $ad_project_params(CLK_MODE)
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set DDR_EN $ad_project_params(DDR_EN)
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puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ;DDR_EN: $DDR_EN"
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# block design ports and interfaces
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# specify the CNV generator's reference clock frequency in MHz
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# NOTE: this is a default value, software may or may not change this
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set cnv_ref_clk 100
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# specify ADC sampling rate in samples/seconds
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# NOTE: this is a default value, software may or may not change this
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set adc_sampling_rate 1000000
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#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad463x_spi
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create_bd_port -dir O ad463x_spi_sclk
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create_bd_port -dir O ad463x_spi_cs
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create_bd_port -dir O ad463x_spi_sdo
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create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad463x_spi_sdi
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create_bd_port -dir I ad463x_echo_sclk
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create_bd_port -dir I ad463x_busy
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create_bd_port -dir O ad463x_cnv
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create_bd_port -dir I ad463x_ext_clk
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## To support the 2MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect spi_clk spi_clkgen/clk_0
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# create a SPI Engine architecture
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###
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# name data_width async_spi_clk num_csn num_sdi sdi_delay echo_sclk
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spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDI 0 1
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ad_ip_parameter spi_ad463x/execution CONFIG.DEFAULT_SPI_CFG 1 ; # latching MISO on negative edge - hardware only
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ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI
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ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_1 $CAPTURE_ZONE
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ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_2 $CLK_MODE
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ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_3 $DDR_EN
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## to setup the sample rate of the system change the PULSE_PERIOD value of the
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## CNV generator; the actual sample rate will be PULSE_PERIOD * (1/cnv_ref_clk)
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set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))]
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ad_ip_instance axi_pwm_gen cnv_generator
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ad_ip_parameter cnv_generator CONFIG.N_PWMS 2
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ad_ip_parameter cnv_generator CONFIG.PULSE_0_PERIOD $sampling_cycle
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ad_ip_parameter cnv_generator CONFIG.PULSE_0_WIDTH 1
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ad_ip_parameter cnv_generator CONFIG.PULSE_1_PERIOD $sampling_cycle
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ad_ip_parameter cnv_generator CONFIG.PULSE_1_WIDTH 1
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ad_ip_parameter cnv_generator CONFIG.PULSE_1_OFFSET 1
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ad_ip_instance spi_axis_reorder data_reorder
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ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_ad463x_dma
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ad_ip_parameter axi_ad463x_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad463x_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad463x_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# Trigger for SPI offload
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if {$CAPTURE_ZONE == 1} {
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## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY
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# is used for SDI latching
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switch $CLK_MODE {
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0 {
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ad_connect spi_ad463x/echo_sclk ad463x_echo_sclk
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}
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1 -
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2 {
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puts "ERROR: Invalid configuration option. CAPTURE_ZONE 1 can be used only in SPI mode (CLK_MODE == 1)."
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exit 2
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}
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default {
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puts "ERROR: Invalid value for CLK_MODE. (valid values are 0 or 1 or 2)"
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exit 2
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}
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}
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# Zone 1 - trigger to BUSY's negative edge
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create_bd_cell -type module -reference sync_bits busy_sync
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create_bd_cell -type module -reference ad_edge_detect busy_capture
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set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
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ad_connect spi_clk busy_capture/clk
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ad_connect spi_clk busy_sync/out_clk
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ad_connect busy_capture/rst GND
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ad_connect spi_ad463x/axi_regmap/spi_resetn busy_sync/out_resetn
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ad_connect ad463x_busy busy_sync/in_bits
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ad_connect busy_sync/out_bits busy_capture/signal_in
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ad_connect busy_capture/signal_out spi_ad463x/trigger
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## SDI is latched by the SPIE execution module
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ad_connect spi_ad463x/m_axis_sample data_reorder/s_axis
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} elseif {$CAPTURE_ZONE == 2} {
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# Zone 2 - trigger to next consecutive CNV
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ad_ip_parameter spi_ad463x/offload CONFIG.ASYNC_TRIG 1
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ad_connect cnv_generator/pwm_0 spi_ad463x/trigger
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## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY
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# is used for SDI latching
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ad_connect spi_ad463x/echo_sclk ad463x_echo_sclk
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switch $CLK_MODE {
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0 {
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## SDI is latched by the SPIE execution module
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ad_connect spi_ad463x/m_axis_sample data_reorder/s_axis
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}
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1 -
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2 {
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## SDI is latched by the data capture
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ad_ip_instance ad463x_data_capture data_capture
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ad_ip_parameter data_capture CONFIG.DDR_EN $DDR_EN
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ad_ip_parameter data_capture CONFIG.NUM_OF_LANES $NUM_OF_SDI
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ad_connect spi_clk data_capture/clk
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ad_connect ad463x_spi_cs data_capture/csn
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ad_connect ad463x_busy data_capture/echo_sclk
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ad_connect ad463x_spi_sdi data_capture/data_in
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ad_connect data_capture/m_axis data_reorder/s_axis
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}
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default {
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puts "ERROR: Invalid value for CLK_MODE. (valid values are 0 or 1 or 2)"
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exit 2
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}
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}
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} else {
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puts "ERROR: Invalid capture zone, please choose 1 or 2."
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exit 2
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}
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ad_connect ad463x_cnv cnv_generator/pwm_1
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# clocks
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ad_connect $sys_cpu_clk spi_ad463x/clk
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ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk
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ad_connect spi_clk spi_ad463x/spi_clk
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ad_connect spi_clk data_reorder/axis_aclk
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ad_connect spi_clk axi_ad463x_dma/s_axis_aclk
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ad_connect ad463x_ext_clk cnv_generator/ext_clk
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# resets
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ad_connect $sys_cpu_resetn cnv_generator/s_axi_aresetn
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ad_connect data_reorder/axis_aresetn VCC
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ad_connect $sys_cpu_resetn spi_ad463x/resetn
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ad_connect $sys_cpu_resetn axi_ad463x_dma/m_dest_axi_aresetn
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# data path
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ad_connect spi_ad463x/execution/cs ad463x_spi_cs
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ad_connect spi_ad463x/execution/sclk ad463x_spi_sclk
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ad_connect spi_ad463x/execution/sdo ad463x_spi_sdo
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ad_connect spi_ad463x/execution/sdi ad463x_spi_sdi
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ad_connect axi_ad463x_dma/s_axis data_reorder/m_axis
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# AXI memory mapped address space
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ad_cpu_interconnect 0x44a00000 spi_ad463x/axi_regmap
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ad_cpu_interconnect 0x44b00000 cnv_generator
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ad_cpu_interconnect 0x44a30000 axi_ad463x_dma
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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# interrupts
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad463x_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /spi_ad463x/irq
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# interconnect to memory interface
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad463x_dma/m_dest_axi
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad463x_fmc_zed
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M_DEPS += system_constr_8sdi.xdc
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M_DEPS += system_constr_4sdi.xdc
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M_DEPS += system_constr_2sdi.xdc
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M_DEPS += system_constr_1sdi.xdc
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M_DEPS += ../common/ad463x_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_data_clk.v
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M_DEPS += ../../../library/util_cdc/sync_bits.v
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M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../../library/common/ad_edge_detect.v
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LIB_DEPS += ad463x_data_capture
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_pwm_gen
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += axi_sysid
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LIB_DEPS += spi_engine/axi_spi_engine
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LIB_DEPS += spi_engine/spi_axis_reorder
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LIB_DEPS += spi_engine/spi_engine_execution
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LIB_DEPS += spi_engine/spi_engine_interconnect
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LIB_DEPS += spi_engine/spi_engine_offload
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_i2c_mixer
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include ../../scripts/project-xilinx.mk
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# EVAL-AD463x_FMCZ HDL reference design
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## Building the design
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The design supports almost all the digital interface modes of AD4630-24, a new
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bit stream should be generated each time when the targeted configuration changes.
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**NOTE:** Interleaved mode (SPI hase one MISO lines) is supported only in SPI clock mode.
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Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR
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data capture and second capture zone is used to pull out data from the converter.
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### Building attributes
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| Attribute name | Valid values |
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| --------------- | ------------------------------------------------- |
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| CLK_MODE | 0 - SPI / 1 - Echo-clock or Master clock |
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| NUM_OF_SDI | 1 - Interleaved / 2 - 1LPC / 4 - 2LPC / 8 - 4LPC |
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| CAPTURE_ZONE | 1 - negedge of BUSY / 2 - next posedge of CNV |
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| DDR_EN | 0 - MISO runs on SDR / 1 - MISO runs on DDR |
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**Example:** make NUM_OF_SDI=2 CAPTURE_ZONE=2
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## Documantation
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https://wiki.analog.com/resources/eval/user-guides/ad436x/hdl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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# add RTL source that will be instantiated in system_bd directly
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adi_project_files ad463x_fmc_zed [list \
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"$ad_hdl_dir/library/common/ad_edge_detect.v" \
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"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
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]
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# block design
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source ../common/ad463x_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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# ad463x_fmc SPI interface
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo]
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk]
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs]
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set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk]
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn]
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set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy]
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv]
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk]
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# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
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create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk]
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# SCLK echod clock, tuned to 80 MHz //, phase shifted with 30% (aprox. 4ns)
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create_clock -period 12.500 -name ECHOSCLK_clk [get_ports ad463x_echo_sclk]
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# rename auto-generated clock for SPIEngine to spi_clk - 160MHz
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# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
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create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
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# create a generated clock for SCLK - fSCLK=spi_clk/2 - 80MHz
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create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports ad463x_spi_sclk]
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# output delay for MOSI line (SDI for the device)
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#
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# tHSDI and tSSDI is 1.5ns
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set_output_delay -clock [get_clocks SCLK_clk] -max 1.500 [get_ports ad463x_spi_sdo]
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set_output_delay -clock [get_clocks SCLK_clk] -min 1.500 [get_ports ad463x_spi_sdo]
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# relax the SDO path to help closing timing at high frequencies
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set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 8
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set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 7
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set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/execution/inst/left_aligned_reg*] 8
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set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/execution/inst/left_aligned_reg*] 7
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P
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# input delays for MISO lines (SDO for the device)
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# data is latched on negative edge
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set tsetup 5.6
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set thold 1.4
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi]
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P
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# input delays for MISO lines (SDO for the device)
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# data is latched on negative edge
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set tsetup 5.6
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set thold 1.4
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]]
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set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]]
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|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}]
|
||||
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}]
|
||||
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}]
|
||||
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}]
|
||||
|
||||
# input delays for MISO lines (SDO for the device)
|
||||
# data is latched on negative edge
|
||||
|
||||
set tsetup 5.6
|
||||
set thold 1.4
|
||||
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[2]}]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}]
|
||||
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[3]] ; ## G10 FMC_LPC_LA03_N
|
||||
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[4]] ; ## H10 FMC_LPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[5]] ; ## H11 FMC_LPC_LA04_N
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[6]] ; ## D11 FMC_LPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[7]] ; ## D12 FMC_LPC_LA05_N
|
||||
|
||||
set tsetup 5.6
|
||||
set thold 1.6
|
||||
|
||||
# input delays for MISO lines (SDO for the device)
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[4]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[4]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[5]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[5]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[6]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]]
|
||||
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]]
|
||||
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
# The get_env_param procedure retrieves parameter value from the environment if exists,
|
||||
# other case returns the default value specified in its second parameter field.
|
||||
#
|
||||
# How to use over-writable parameters from the environment:
|
||||
#
|
||||
# e.g.
|
||||
# make NUM_OF_SDI=4 CAPTURE_ZONE=2
|
||||
#
|
||||
#
|
||||
# Parameter description:
|
||||
#
|
||||
# CLK_MODE : Clocking mode of the device's digital interface
|
||||
#
|
||||
# 0 - SPI Mode
|
||||
# 1 - Echo-clock or Master clock mode
|
||||
#
|
||||
# NUM_OF_SDI : the number of MOSI lines of the SPI interface
|
||||
#
|
||||
# 1 - Interleaved mode
|
||||
# 2 - 1 lane per channel
|
||||
# 4 - 2 lanes per channel
|
||||
# 8 - 4 lanes per channel
|
||||
#
|
||||
# CAPTURE_ZONE : the capture zone of the next sample
|
||||
# There are two capture zones for AD4624-30:
|
||||
#
|
||||
# 1 - from negative edge of the BUSY line until the next CNV positive edge -20ns
|
||||
# 2 - from the next consecutive CNV positive edge +20ns until the second next
|
||||
# consecutive CNV positive edge -20ns
|
||||
#
|
||||
# DDR_EN : in echo and master clock mode the SDI lines can have Single or Double
|
||||
# Data Rates
|
||||
#
|
||||
# 0 - MISO runs on SDR
|
||||
# 1 - MISO runs on DDR
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# make NUM_OF_SDI=2 CAPTURE_ZONE=2
|
||||
#
|
||||
|
||||
adi_project ad463x_fmc_zed 0 [list \
|
||||
CLK_MODE [get_env_param CLK_MODE 0] \
|
||||
NUM_OF_SDI [get_env_param NUM_OF_SDI 4] \
|
||||
CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \
|
||||
DDR_EN [get_env_param DDR_EN 0] \
|
||||
]
|
||||
|
||||
adi_project_files ad463x_fmc_zed [list \
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
|
||||
"system_constr.xdc" \
|
||||
"system_top.v" \
|
||||
]
|
||||
|
||||
switch [get_env_param NUM_OF_SDI 4] {
|
||||
1 {
|
||||
adi_project_files ad463x_fmc_zed [list \
|
||||
"system_constr_1sdi.xdc"
|
||||
]
|
||||
}
|
||||
2 {
|
||||
adi_project_files ad463x_fmc_zed [list \
|
||||
"system_constr_2sdi.xdc"
|
||||
]
|
||||
}
|
||||
4 {
|
||||
adi_project_files ad463x_fmc_zed [list \
|
||||
"system_constr_4sdi.xdc"
|
||||
]
|
||||
}
|
||||
8 {
|
||||
adi_project_files ad463x_fmc_zed [list \
|
||||
"system_constr_8sdi.xdc"
|
||||
]
|
||||
}
|
||||
default {
|
||||
adi_project_files ad463x_fmc_zed [list \
|
||||
"system_constr_2sdi.xdc"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
adi_project_run ad463x_fmc_zed
|
||||
|
||||
|
|
@ -0,0 +1,248 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsabilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top #(
|
||||
parameter NUM_OF_SDI = 2
|
||||
)(
|
||||
|
||||
inout [14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [31:0] gpio_bd,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [15:0] hdmi_data,
|
||||
|
||||
output spdif,
|
||||
|
||||
output i2s_mclk,
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
output i2s_sdata_out,
|
||||
input i2s_sdata_in,
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
inout [ 1:0] iic_mux_scl,
|
||||
inout [ 1:0] iic_mux_sda,
|
||||
|
||||
input otg_vbusoc,
|
||||
|
||||
// ad463x SPI configuration interface
|
||||
|
||||
input [NUM_OF_SDI-1:0] ad463x_spi_sdi,
|
||||
output ad463x_spi_sdo,
|
||||
output ad463x_spi_sclk,
|
||||
output ad463x_spi_cs,
|
||||
|
||||
input ad463x_echo_sclk,
|
||||
input ad463x_ext_clk,
|
||||
output ad463x_cnv,
|
||||
input ad463x_busy,
|
||||
inout ad463x_resetn
|
||||
|
||||
);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire ext_clk_s;
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
wire ad463x_echo_sclk_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
assign gpio_i[63:33] = 31'b0;
|
||||
|
||||
ad_data_clk #(
|
||||
.SINGLE_ENDED (1))
|
||||
i_ext_clk (
|
||||
.rst (1'b0),
|
||||
.locked (),
|
||||
.clk_in_p (ad463x_ext_clk),
|
||||
.clk_in_n (1'b0),
|
||||
.clk (ext_clk_s)
|
||||
);
|
||||
|
||||
ad_data_clk #(
|
||||
.SINGLE_ENDED (1))
|
||||
i_echo_sclk (
|
||||
.rst (1'b0),
|
||||
.locked (),
|
||||
.clk_in_p (ad463x_echo_sclk),
|
||||
.clk_in_n (1'b0),
|
||||
.clk (ad463x_echo_sclk_s)
|
||||
);
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(1)
|
||||
) i_ad463x_gpio_iobuf (
|
||||
.dio_t(gpio_t[32]),
|
||||
.dio_i(gpio_o[32]),
|
||||
.dio_o(gpio_i[32]),
|
||||
.dio_p(ad463x_resetn));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(32)
|
||||
) i_iobuf (
|
||||
.dio_t(gpio_t[31:0]),
|
||||
.dio_i(gpio_o[31:0]),
|
||||
.dio_o(gpio_i[31:0]),
|
||||
.dio_p(gpio_bd));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_iic_mux_scl (
|
||||
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
|
||||
.dio_i(iic_mux_scl_o_s),
|
||||
.dio_o(iic_mux_scl_i_s),
|
||||
.dio_p(iic_mux_scl));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_iic_mux_sda (
|
||||
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
|
||||
.dio_i(iic_mux_sda_o_s),
|
||||
.dio_o(iic_mux_sda_i_s),
|
||||
.dio_p(iic_mux_sda));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (),
|
||||
.spi0_csn_0_o (),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (1'b0),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o (),
|
||||
.ad463x_spi_sdo (ad463x_spi_sdo),
|
||||
.ad463x_spi_sdi (ad463x_spi_sdi),
|
||||
.ad463x_spi_cs (ad463x_spi_cs),
|
||||
.ad463x_spi_sclk (ad463x_spi_sclk),
|
||||
.ad463x_echo_sclk (ad463x_echo_sclk_s),
|
||||
.ad463x_busy (ad463x_busy),
|
||||
.ad463x_cnv (ad463x_cnv),
|
||||
.ad463x_ext_clk (ext_clk_s),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue