From 15a6480601e4fd9ef5fdb951c6bb0721b4fccfe3 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 21 Jan 2021 10:05:11 +0000 Subject: [PATCH] ad4630_fmc: Initial commit --- projects/ad4630_fmc/Makefile | 7 + projects/ad4630_fmc/common/ad463x_bd.tcl | 202 ++++++++++++++ projects/ad4630_fmc/zed/Makefile | 39 +++ projects/ad4630_fmc/zed/README.md | 27 ++ projects/ad4630_fmc/zed/system_bd.tcl | 20 ++ projects/ad4630_fmc/zed/system_constr.xdc | 39 +++ .../ad4630_fmc/zed/system_constr_1sdi.xdc | 12 + .../ad4630_fmc/zed/system_constr_2sdi.xdc | 15 ++ .../ad4630_fmc/zed/system_constr_4sdi.xdc | 21 ++ .../ad4630_fmc/zed/system_constr_8sdi.xdc | 31 +++ projects/ad4630_fmc/zed/system_project.tcl | 91 +++++++ projects/ad4630_fmc/zed/system_top.v | 248 ++++++++++++++++++ 12 files changed, 752 insertions(+) create mode 100644 projects/ad4630_fmc/Makefile create mode 100644 projects/ad4630_fmc/common/ad463x_bd.tcl create mode 100644 projects/ad4630_fmc/zed/Makefile create mode 100644 projects/ad4630_fmc/zed/README.md create mode 100644 projects/ad4630_fmc/zed/system_bd.tcl create mode 100644 projects/ad4630_fmc/zed/system_constr.xdc create mode 100644 projects/ad4630_fmc/zed/system_constr_1sdi.xdc create mode 100644 projects/ad4630_fmc/zed/system_constr_2sdi.xdc create mode 100644 projects/ad4630_fmc/zed/system_constr_4sdi.xdc create mode 100644 projects/ad4630_fmc/zed/system_constr_8sdi.xdc create mode 100644 projects/ad4630_fmc/zed/system_project.tcl create mode 100644 projects/ad4630_fmc/zed/system_top.v diff --git a/projects/ad4630_fmc/Makefile b/projects/ad4630_fmc/Makefile new file mode 100644 index 000000000..2458d9876 --- /dev/null +++ b/projects/ad4630_fmc/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl new file mode 100644 index 000000000..172b9a3b8 --- /dev/null +++ b/projects/ad4630_fmc/common/ad463x_bd.tcl @@ -0,0 +1,202 @@ + +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + +# system level parameters +set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) +set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE) +set CLK_MODE $ad_project_params(CLK_MODE) +set DDR_EN $ad_project_params(DDR_EN) + +puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ;DDR_EN: $DDR_EN" + +# block design ports and interfaces +# specify the CNV generator's reference clock frequency in MHz +# NOTE: this is a default value, software may or may not change this +set cnv_ref_clk 100 + +# specify ADC sampling rate in samples/seconds +# NOTE: this is a default value, software may or may not change this +set adc_sampling_rate 1000000 + +#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad463x_spi + +create_bd_port -dir O ad463x_spi_sclk +create_bd_port -dir O ad463x_spi_cs +create_bd_port -dir O ad463x_spi_sdo +create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad463x_spi_sdi + +create_bd_port -dir I ad463x_echo_sclk + +create_bd_port -dir I ad463x_busy +create_bd_port -dir O ad463x_cnv +create_bd_port -dir I ad463x_ext_clk + +## To support the 2MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz + +ad_ip_instance axi_clkgen spi_clkgen +ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5 +ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8 +ad_connect $sys_cpu_clk spi_clkgen/clk +ad_connect spi_clk spi_clkgen/clk_0 + +# create a SPI Engine architecture +### +# name data_width async_spi_clk num_csn num_sdi sdi_delay echo_sclk +spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDI 0 1 +ad_ip_parameter spi_ad463x/execution CONFIG.DEFAULT_SPI_CFG 1 ; # latching MISO on negative edge - hardware only + +ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI +ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_1 $CAPTURE_ZONE +ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_2 $CLK_MODE +ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_3 $DDR_EN + +## to setup the sample rate of the system change the PULSE_PERIOD value of the +## CNV generator; the actual sample rate will be PULSE_PERIOD * (1/cnv_ref_clk) +set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))] + +ad_ip_instance axi_pwm_gen cnv_generator +ad_ip_parameter cnv_generator CONFIG.N_PWMS 2 +ad_ip_parameter cnv_generator CONFIG.PULSE_0_PERIOD $sampling_cycle +ad_ip_parameter cnv_generator CONFIG.PULSE_0_WIDTH 1 +ad_ip_parameter cnv_generator CONFIG.PULSE_1_PERIOD $sampling_cycle +ad_ip_parameter cnv_generator CONFIG.PULSE_1_WIDTH 1 +ad_ip_parameter cnv_generator CONFIG.PULSE_1_OFFSET 1 + +ad_ip_instance spi_axis_reorder data_reorder +ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI + +# dma to receive data stream + +ad_ip_instance axi_dmac axi_ad463x_dma +ad_ip_parameter axi_ad463x_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_ad463x_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad463x_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_SRC 1 +ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +# Trigger for SPI offload +if {$CAPTURE_ZONE == 1} { + + ## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY + # is used for SDI latching + switch $CLK_MODE { + 0 { + ad_connect spi_ad463x/echo_sclk ad463x_echo_sclk + } + 1 - + 2 { + puts "ERROR: Invalid configuration option. CAPTURE_ZONE 1 can be used only in SPI mode (CLK_MODE == 1)." + exit 2 + } + default { + puts "ERROR: Invalid value for CLK_MODE. (valid values are 0 or 1 or 2)" + exit 2 + } + } + + # Zone 1 - trigger to BUSY's negative edge + create_bd_cell -type module -reference sync_bits busy_sync + create_bd_cell -type module -reference ad_edge_detect busy_capture + set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture] + + ad_connect spi_clk busy_capture/clk + ad_connect spi_clk busy_sync/out_clk + ad_connect busy_capture/rst GND + ad_connect spi_ad463x/axi_regmap/spi_resetn busy_sync/out_resetn + + ad_connect ad463x_busy busy_sync/in_bits + ad_connect busy_sync/out_bits busy_capture/signal_in + ad_connect busy_capture/signal_out spi_ad463x/trigger + + ## SDI is latched by the SPIE execution module + ad_connect spi_ad463x/m_axis_sample data_reorder/s_axis + +} elseif {$CAPTURE_ZONE == 2} { + + # Zone 2 - trigger to next consecutive CNV + ad_ip_parameter spi_ad463x/offload CONFIG.ASYNC_TRIG 1 + ad_connect cnv_generator/pwm_0 spi_ad463x/trigger + + ## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY + # is used for SDI latching + + ad_connect spi_ad463x/echo_sclk ad463x_echo_sclk + switch $CLK_MODE { + 0 { + ## SDI is latched by the SPIE execution module + ad_connect spi_ad463x/m_axis_sample data_reorder/s_axis + } + 1 - + 2 { + ## SDI is latched by the data capture + ad_ip_instance ad463x_data_capture data_capture + ad_ip_parameter data_capture CONFIG.DDR_EN $DDR_EN + ad_ip_parameter data_capture CONFIG.NUM_OF_LANES $NUM_OF_SDI + + ad_connect spi_clk data_capture/clk + ad_connect ad463x_spi_cs data_capture/csn + ad_connect ad463x_busy data_capture/echo_sclk + ad_connect ad463x_spi_sdi data_capture/data_in + + ad_connect data_capture/m_axis data_reorder/s_axis + + } + default { + puts "ERROR: Invalid value for CLK_MODE. (valid values are 0 or 1 or 2)" + exit 2 + } + } + +} else { + + puts "ERROR: Invalid capture zone, please choose 1 or 2." + exit 2 + +} +ad_connect ad463x_cnv cnv_generator/pwm_1 + +# clocks + +ad_connect $sys_cpu_clk spi_ad463x/clk +ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk +ad_connect spi_clk spi_ad463x/spi_clk +ad_connect spi_clk data_reorder/axis_aclk +ad_connect spi_clk axi_ad463x_dma/s_axis_aclk +ad_connect ad463x_ext_clk cnv_generator/ext_clk + +# resets + +ad_connect $sys_cpu_resetn cnv_generator/s_axi_aresetn +ad_connect data_reorder/axis_aresetn VCC +ad_connect $sys_cpu_resetn spi_ad463x/resetn +ad_connect $sys_cpu_resetn axi_ad463x_dma/m_dest_axi_aresetn + +# data path + +ad_connect spi_ad463x/execution/cs ad463x_spi_cs +ad_connect spi_ad463x/execution/sclk ad463x_spi_sclk +ad_connect spi_ad463x/execution/sdo ad463x_spi_sdo +ad_connect spi_ad463x/execution/sdi ad463x_spi_sdi + +ad_connect axi_ad463x_dma/s_axis data_reorder/m_axis + +# AXI memory mapped address space + +ad_cpu_interconnect 0x44a00000 spi_ad463x/axi_regmap +ad_cpu_interconnect 0x44b00000 cnv_generator +ad_cpu_interconnect 0x44a30000 axi_ad463x_dma +ad_cpu_interconnect 0x44a70000 spi_clkgen + +# interrupts + +ad_cpu_interrupt "ps-13" "mb-13" axi_ad463x_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" /spi_ad463x/irq + +# interconnect to memory interface + +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad463x_dma/m_dest_axi + diff --git a/projects/ad4630_fmc/zed/Makefile b/projects/ad4630_fmc/zed/Makefile new file mode 100644 index 000000000..7d841fcd8 --- /dev/null +++ b/projects/ad4630_fmc/zed/Makefile @@ -0,0 +1,39 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad463x_fmc_zed + +M_DEPS += system_constr_8sdi.xdc +M_DEPS += system_constr_4sdi.xdc +M_DEPS += system_constr_2sdi.xdc +M_DEPS += system_constr_1sdi.xdc +M_DEPS += ../common/ad463x_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_data_clk.v +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_edge_detect.v + +LIB_DEPS += ad463x_data_capture +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_axis_reorder +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad4630_fmc/zed/README.md b/projects/ad4630_fmc/zed/README.md new file mode 100644 index 000000000..417c1f213 --- /dev/null +++ b/projects/ad4630_fmc/zed/README.md @@ -0,0 +1,27 @@ + +# EVAL-AD463x_FMCZ HDL reference design + +## Building the design + +The design supports almost all the digital interface modes of AD4630-24, a new +bit stream should be generated each time when the targeted configuration changes. +**NOTE:** Interleaved mode (SPI hase one MISO lines) is supported only in SPI clock mode. + +Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR +data capture and second capture zone is used to pull out data from the converter. + +### Building attributes + +| Attribute name | Valid values | +| --------------- | ------------------------------------------------- | +| CLK_MODE | 0 - SPI / 1 - Echo-clock or Master clock | +| NUM_OF_SDI | 1 - Interleaved / 2 - 1LPC / 4 - 2LPC / 8 - 4LPC | +| CAPTURE_ZONE | 1 - negedge of BUSY / 2 - next posedge of CNV | +| DDR_EN | 0 - MISO runs on SDR / 1 - MISO runs on DDR | + +**Example:** make NUM_OF_SDI=2 CAPTURE_ZONE=2 + +## Documantation + +https://wiki.analog.com/resources/eval/user-guides/ad436x/hdl + diff --git a/projects/ad4630_fmc/zed/system_bd.tcl b/projects/ad4630_fmc/zed/system_bd.tcl new file mode 100644 index 000000000..6a11c550b --- /dev/null +++ b/projects/ad4630_fmc/zed/system_bd.tcl @@ -0,0 +1,20 @@ + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + +# add RTL source that will be instantiated in system_bd directly +adi_project_files ad463x_fmc_zed [list \ + "$ad_hdl_dir/library/common/ad_edge_detect.v" \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ +] + +# block design +source ../common/ad463x_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "sys rom custom string placeholder" +sysid_gen_sys_init_file $sys_cstring + diff --git a/projects/ad4630_fmc/zed/system_constr.xdc b/projects/ad4630_fmc/zed/system_constr.xdc new file mode 100644 index 000000000..e943b7ea9 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr.xdc @@ -0,0 +1,39 @@ + +# ad463x_fmc SPI interface + +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] + +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk] +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn] +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy] +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] + +# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency +create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk] + +# SCLK echod clock, tuned to 80 MHz //, phase shifted with 30% (aprox. 4ns) +create_clock -period 12.500 -name ECHOSCLK_clk [get_ports ad463x_echo_sclk] + +# rename auto-generated clock for SPIEngine to spi_clk - 160MHz +# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk +create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] + +# create a generated clock for SCLK - fSCLK=spi_clk/2 - 80MHz +create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports ad463x_spi_sclk] + +# output delay for MOSI line (SDI for the device) +# +# tHSDI and tSSDI is 1.5ns +set_output_delay -clock [get_clocks SCLK_clk] -max 1.500 [get_ports ad463x_spi_sdo] +set_output_delay -clock [get_clocks SCLK_clk] -min 1.500 [get_ports ad463x_spi_sdo] + +# relax the SDO path to help closing timing at high frequencies +set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 8 +set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 7 + +set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/execution/inst/left_aligned_reg*] 8 +set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/execution/inst/left_aligned_reg*] 7 + diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi.xdc new file mode 100644 index 000000000..39b64b583 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr_1sdi.xdc @@ -0,0 +1,12 @@ + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P + +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.4 + +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi] + diff --git a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi.xdc new file mode 100644 index 000000000..364667fc5 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr_2sdi.xdc @@ -0,0 +1,15 @@ + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P + +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.4 + +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] + diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi.xdc new file mode 100644 index 000000000..cac5c7c14 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr_4sdi.xdc @@ -0,0 +1,21 @@ + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] + +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.4 + +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[2]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}] + diff --git a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc b/projects/ad4630_fmc/zed/system_constr_8sdi.xdc new file mode 100644 index 000000000..a07383a71 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr_8sdi.xdc @@ -0,0 +1,31 @@ + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[3]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[4]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[5]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[6]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[7]] ; ## D12 FMC_LPC_LA05_N + +set tsetup 5.6 +set thold 1.6 + +# input delays for MISO lines (SDO for the device) +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[4]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[4]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[5]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[5]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[6]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]] + diff --git a/projects/ad4630_fmc/zed/system_project.tcl b/projects/ad4630_fmc/zed/system_project.tcl new file mode 100644 index 000000000..8ecc99a4e --- /dev/null +++ b/projects/ad4630_fmc/zed/system_project.tcl @@ -0,0 +1,91 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# The get_env_param procedure retrieves parameter value from the environment if exists, +# other case returns the default value specified in its second parameter field. +# +# How to use over-writable parameters from the environment: +# +# e.g. +# make NUM_OF_SDI=4 CAPTURE_ZONE=2 +# +# +# Parameter description: +# +# CLK_MODE : Clocking mode of the device's digital interface +# +# 0 - SPI Mode +# 1 - Echo-clock or Master clock mode +# +# NUM_OF_SDI : the number of MOSI lines of the SPI interface +# +# 1 - Interleaved mode +# 2 - 1 lane per channel +# 4 - 2 lanes per channel +# 8 - 4 lanes per channel +# +# CAPTURE_ZONE : the capture zone of the next sample +# There are two capture zones for AD4624-30: +# +# 1 - from negative edge of the BUSY line until the next CNV positive edge -20ns +# 2 - from the next consecutive CNV positive edge +20ns until the second next +# consecutive CNV positive edge -20ns +# +# DDR_EN : in echo and master clock mode the SDI lines can have Single or Double +# Data Rates +# +# 0 - MISO runs on SDR +# 1 - MISO runs on DDR +# +# Example: +# +# make NUM_OF_SDI=2 CAPTURE_ZONE=2 +# + +adi_project ad463x_fmc_zed 0 [list \ + CLK_MODE [get_env_param CLK_MODE 0] \ + NUM_OF_SDI [get_env_param NUM_OF_SDI 4] \ + CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \ + DDR_EN [get_env_param DDR_EN 0] \ +] + +adi_project_files ad463x_fmc_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "system_constr.xdc" \ + "system_top.v" \ +] + +switch [get_env_param NUM_OF_SDI 4] { + 1 { + adi_project_files ad463x_fmc_zed [list \ + "system_constr_1sdi.xdc" + ] + } + 2 { + adi_project_files ad463x_fmc_zed [list \ + "system_constr_2sdi.xdc" + ] + } + 4 { + adi_project_files ad463x_fmc_zed [list \ + "system_constr_4sdi.xdc" + ] + } + 8 { + adi_project_files ad463x_fmc_zed [list \ + "system_constr_8sdi.xdc" + ] + } + default { + adi_project_files ad463x_fmc_zed [list \ + "system_constr_2sdi.xdc" + ] + } +} + +adi_project_run ad463x_fmc_zed + diff --git a/projects/ad4630_fmc/zed/system_top.v b/projects/ad4630_fmc/zed/system_top.v new file mode 100644 index 000000000..aa8b2526e --- /dev/null +++ b/projects/ad4630_fmc/zed/system_top.v @@ -0,0 +1,248 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter NUM_OF_SDI = 2 +)( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // ad463x SPI configuration interface + + input [NUM_OF_SDI-1:0] ad463x_spi_sdi, + output ad463x_spi_sdo, + output ad463x_spi_sclk, + output ad463x_spi_cs, + + input ad463x_echo_sclk, + input ad463x_ext_clk, + output ad463x_cnv, + input ad463x_busy, + inout ad463x_resetn + +); + + // internal signals + + wire ext_clk_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire ad463x_echo_sclk_s; + + // instantiations + + assign gpio_i[63:33] = 31'b0; + + ad_data_clk #( + .SINGLE_ENDED (1)) + i_ext_clk ( + .rst (1'b0), + .locked (), + .clk_in_p (ad463x_ext_clk), + .clk_in_n (1'b0), + .clk (ext_clk_s) + ); + + ad_data_clk #( + .SINGLE_ENDED (1)) + i_echo_sclk ( + .rst (1'b0), + .locked (), + .clk_in_p (ad463x_echo_sclk), + .clk_in_n (1'b0), + .clk (ad463x_echo_sclk_s) + ); + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_ad463x_gpio_iobuf ( + .dio_t(gpio_t[32]), + .dio_i(gpio_o[32]), + .dio_o(gpio_i[32]), + .dio_p(ad463x_resetn)); + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .ad463x_spi_sdo (ad463x_spi_sdo), + .ad463x_spi_sdi (ad463x_spi_sdi), + .ad463x_spi_cs (ad463x_spi_cs), + .ad463x_spi_sclk (ad463x_spi_sclk), + .ad463x_echo_sclk (ad463x_echo_sclk_s), + .ad463x_busy (ad463x_busy), + .ad463x_cnv (ad463x_cnv), + .ad463x_ext_clk (ext_clk_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// ***************************************************************************