From 157afcbc33795f240bdafe385715d4f9dbde7a98 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 16 May 2019 15:05:11 +0100 Subject: [PATCH] tb_base: Fix various test benches The tb_base.v verilog files does not contain a full module definition, just some plain test code. In general the files is sourced inside the test bench main module. As is, defining a timescale in these files will generate an error, because timescale directive can not be inside a module. Delete all the timescale directive from these files. --- library/axi_dmac/tb/tb_base.v | 2 -- library/jesd204/tb/tb_base.v | 2 -- library/util_pack/tb/tb_base.v | 2 -- 3 files changed, 6 deletions(-) diff --git a/library/axi_dmac/tb/tb_base.v b/library/axi_dmac/tb/tb_base.v index ea6b51acd..e6dd7ad93 100644 --- a/library/axi_dmac/tb/tb_base.v +++ b/library/axi_dmac/tb/tb_base.v @@ -33,8 +33,6 @@ // *************************************************************************** // *************************************************************************** -`timescale 1ns/100ps - reg clk = 1'b0; reg [3:0] reset_shift = 4'b1111; reg trigger_reset = 1'b0; diff --git a/library/jesd204/tb/tb_base.v b/library/jesd204/tb/tb_base.v index d1225babe..459ae7573 100644 --- a/library/jesd204/tb/tb_base.v +++ b/library/jesd204/tb/tb_base.v @@ -42,8 +42,6 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // -`timescale 1ns/100ps - reg clk = 1'b0; reg [3:0] reset_shift = 4'b1111; reg trigger_reset = 1'b0; diff --git a/library/util_pack/tb/tb_base.v b/library/util_pack/tb/tb_base.v index 93b2a8e82..f721d873d 100644 --- a/library/util_pack/tb/tb_base.v +++ b/library/util_pack/tb/tb_base.v @@ -33,8 +33,6 @@ // *************************************************************************** // *************************************************************************** -`timescale 1ns/100ps - reg clk = 1'b1; reg [3:0] reset_shift = 4'b1111; reg trigger_reset = 1'b0;