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fmcjesdadc1- 15.0 updates

main
Rejeesh Kutty 2015-06-24 05:30:03 -04:00
parent 281a47c117
commit 15740a7d34
5 changed files with 1549 additions and 1122 deletions
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108
projects/common/a5gt/a5gt_system_assign.tcl
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@ -764,61 +764,61 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_rx_clk
# leds
set_location_assignment PIN_M19 -to led_grn[0]
set_location_assignment PIN_L19 -to led_grn[1]
set_location_assignment PIN_K19 -to led_grn[2]
set_location_assignment PIN_J19 -to led_grn[3]
set_location_assignment PIN_K20 -to led_grn[4]
set_location_assignment PIN_J20 -to led_grn[5]
set_location_assignment PIN_T20 -to led_grn[6]
set_location_assignment PIN_R20 -to led_grn[7]
set_location_assignment PIN_N20 -to led_red[0]
set_location_assignment PIN_C15 -to led_red[1]
set_location_assignment PIN_AL28 -to led_red[2]
set_location_assignment PIN_F11 -to led_red[3]
set_location_assignment PIN_AJ31 -to led_red[4]
set_location_assignment PIN_AN34 -to led_red[5]
set_location_assignment PIN_AJ34 -to led_red[6]
set_location_assignment PIN_AK33 -to led_red[7]
set_location_assignment PIN_D6 -to push_buttons[0]
set_location_assignment PIN_C6 -to push_buttons[1]
set_location_assignment PIN_K7 -to push_buttons[2]
set_location_assignment PIN_C8 -to dip_switches[0]
set_location_assignment PIN_D8 -to dip_switches[1]
set_location_assignment PIN_E7 -to dip_switches[2]
set_location_assignment PIN_E6 -to dip_switches[3]
set_location_assignment PIN_G8 -to dip_switches[4]
set_location_assignment PIN_F8 -to dip_switches[5]
set_location_assignment PIN_D15 -to dip_switches[6]
set_location_assignment PIN_G11 -to dip_switches[7]
set_location_assignment PIN_M19 -to gpio_bd[0] ; ## led_grn[0]
set_location_assignment PIN_L19 -to gpio_bd[1] ; ## led_grn[1]
set_location_assignment PIN_K19 -to gpio_bd[2] ; ## led_grn[2]
set_location_assignment PIN_J19 -to gpio_bd[3] ; ## led_grn[3]
set_location_assignment PIN_K20 -to gpio_bd[4] ; ## led_grn[4]
set_location_assignment PIN_J20 -to gpio_bd[5] ; ## led_grn[5]
set_location_assignment PIN_T20 -to gpio_bd[6] ; ## led_grn[6]
set_location_assignment PIN_R20 -to gpio_bd[7] ; ## led_grn[7]
set_location_assignment PIN_N20 -to gpio_bd[8] ; ## led_red[0]
set_location_assignment PIN_C15 -to gpio_bd[9] ; ## led_red[1]
set_location_assignment PIN_AL28 -to gpio_bd[10] ; ## led_red[2]
set_location_assignment PIN_F11 -to gpio_bd[11] ; ## led_red[3]
set_location_assignment PIN_AJ31 -to gpio_bd[12] ; ## led_red[4]
set_location_assignment PIN_AN34 -to gpio_bd[13] ; ## led_red[5]
set_location_assignment PIN_AJ34 -to gpio_bd[14] ; ## led_red[6]
set_location_assignment PIN_AK33 -to gpio_bd[15] ; ## led_red[7]
set_location_assignment PIN_C8 -to gpio_bd[16] ; ## dip_switches[0]
set_location_assignment PIN_D8 -to gpio_bd[17] ; ## dip_switches[1]
set_location_assignment PIN_E7 -to gpio_bd[18] ; ## dip_switches[2]
set_location_assignment PIN_E6 -to gpio_bd[19] ; ## dip_switches[3]
set_location_assignment PIN_G8 -to gpio_bd[20] ; ## dip_switches[4]
set_location_assignment PIN_F8 -to gpio_bd[21] ; ## dip_switches[5]
set_location_assignment PIN_D15 -to gpio_bd[22] ; ## dip_switches[6]
set_location_assignment PIN_G11 -to gpio_bd[23] ; ## dip_switches[7]
set_location_assignment PIN_D6 -to gpio_bd[24] ; ## push_buttons[0]
set_location_assignment PIN_C6 -to gpio_bd[25] ; ## push_buttons[1]
set_location_assignment PIN_K7 -to gpio_bd[26] ; ## push_buttons[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[16]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[17]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[18]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[19]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[20]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[21]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[22]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[23]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[24]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[25]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[26]
# globals

2216
projects/fmcjesdadc1/a5gt/system_bd.qsys
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28
projects/fmcjesdadc1/a5gt/system_constr.sdc
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@ -1,32 +1,10 @@
create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name n_clk_250m [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name ref_clk_250mhz [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name eth_rx_clk_125mhz [get_ports {eth_rx_clk}]
derive_pll_clocks
derive_clock_uncertainty
set clk_100m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_166m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_125m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_25m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_2m5 [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -from {sys_resetn} -to *
set_false_path -from $clk_100m -to $clk_166m
set_false_path -from $clk_100m -to $clk_rxlink
set_false_path -from $clk_166m -to $clk_100m
set_false_path -from $clk_166m -to $clk_rxlink
set_false_path -from $clk_rxlink -to $clk_100m
set_false_path -from $clk_rxlink -to $clk_166m
set_false_path -from $clk_125m -to $clk_25m
set_false_path -from $clk_125m -to $clk_2m5
set_false_path -from $clk_25m -to $clk_125m
set_false_path -from $clk_25m -to $clk_2m5
set_false_path -from $clk_2m5 -to $clk_125m
set_false_path -from $clk_2m5 -to $clk_25m

8
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -6,8 +6,7 @@ project_new fmcjesdadc1_a5gt -overwrite
source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
# reference clock
@ -55,5 +54,10 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
# disable auto-pack
set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
execute_flow -compile

311
projects/fmcjesdadc1/a5gt/system_top.v
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@ -46,21 +46,21 @@ module system_top (
// ddr3
ddr3_a,
ddr3_ba,
ddr3_clk_p,
ddr3_clk_n,
ddr3_a,
ddr3_ba,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_odt,
ddr3_reset_n,
ddr3_we_n,
ddr3_ras_n,
ddr3_cas_n,
ddr3_we_n,
ddr3_reset_n,
ddr3_dq,
ddr3_dqs_p,
ddr3_dqs_n,
ddr3_odt,
ddr3_dq,
ddr3_dm,
ddr3_rzq,
// ethernet
@ -79,10 +79,7 @@ module system_top (
// board gpio
led_grn,
led_red,
push_buttons,
dip_switches,
gpio_bd,
// lane interface
@ -104,21 +101,21 @@ module system_top (
// ddr3
output [ 13:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_clk_p;
output ddr3_clk_n;
output [ 13:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_cke;
output ddr3_cs_n;
output [ 7:0] ddr3_dm;
output ddr3_odt;
output ddr3_reset_n;
output ddr3_we_n;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
inout [ 63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_p;
inout [ 7:0] ddr3_dqs_n;
output ddr3_odt;
inout [ 63:0] ddr3_dq;
output [ 7:0] ddr3_dm;
input ddr3_rzq;
// ethernet
@ -137,10 +134,7 @@ module system_top (
// board gpio
output [ 7:0] led_grn;
output [ 7:0] led_red;
input [ 2:0] push_buttons;
input [ 7:0] dip_switches;
output [ 26:0] gpio_bd;
// lane interface
@ -157,76 +151,85 @@ module system_top (
// internal registers
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref_d1 = 'd0;
reg rx_sysref_d2 = 'd0;
reg rx_sysref = 'd0;
reg dma0_wr = 'd0;
reg [ 63:0] dma0_wdata = 'd0;
reg dma1_wr = 'd0;
reg [ 63:0] dma1_wdata = 'd0;
reg rx_sync_m1 = 'd0;
reg rx_sync_m2 = 'd0;
reg rx_sync_up = 'd0;
reg [ 3:0] phy_rst_cnt = 0;
reg phy_rst_reg = 0;
// internal clocks and resets
wire sys_pll_clk;
wire sys_125m_clk;
wire sys_25m_clk;
wire sys_2m5_clk;
wire eth_tx_clk;
wire rx_clk;
wire adc0_clk;
wire adc1_clk;
// internal signals
wire sys_pll_locked_s;
wire eth_tx_reset_s;
wire eth_tx_mode_1g_s;
wire eth_tx_mode_10m_100m_n_s;
wire sys_pll_locked;
wire eth_tx_mode_1g;
wire eth_tx_mode_10m_100m_n;
wire spi_mosi;
wire spi_miso;
wire adc0_enable_a_s;
wire [ 31:0] adc0_data_a_s;
wire adc0_enable_b_s;
wire [ 31:0] adc0_data_b_s;
wire adc0_dovf_s;
wire adc1_enable_a_s;
wire [ 31:0] adc1_data_a_s;
wire adc1_enable_b_s;
wire [ 31:0] adc1_data_b_s;
wire adc1_dovf_s;
wire [ 3:0] rx_ip_sof_s;
wire [127:0] rx_ip_data_s;
wire [127:0] rx_data_s;
wire rx_sw_rstn_s;
wire rx_sysref_s;
wire rx_err_s;
wire rx_ready_s;
wire [ 3:0] rx_rst_state_s;
wire rx_lane_aligned_s;
wire [ 3:0] rx_analog_reset_s;
wire [ 3:0] rx_digital_reset_s;
wire [ 3:0] rx_cdr_locked_s;
wire [ 3:0] rx_cal_busy_s;
wire rx_pll_locked_s;
wire [ 15:0] rx_xcvr_status_s;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 31:0] gpio_jesd_i;
wire [ 31:0] gpio_jesd_o;
wire [ 3:0] rx_ready;
// jesd sysref
always @(posedge sys_pll_clk or negedge sys_resetn) begin
rx_sysref_d1 <= gpio_jesd_i[13];
rx_sysref_d2 <= rx_sysref_d1;
rx_sysref <= rx_sysref_d1 & ~rx_sysref_d2;
rx_sync_m1 = rx_sync;
rx_sync_m2 = rx_sync_m1;
rx_sync_up = rx_sync_m2;
end
assign gpio_jesd_i[31:24] = gpio_jesd_o[31:24];
assign gpio_jesd_i[23:16] = 8'd0;
assign gpio_jesd_i[15:15] = gpio_jesd_o[15];
assign gpio_jesd_i[14:14] = rx_sync_up;
assign gpio_jesd_i[13:13] = gpio_jesd_o[13];
assign gpio_jesd_i[12: 8] = 5'd0;
assign gpio_jesd_i[ 7: 4] = 4'hf;
assign gpio_jesd_i[ 3: 0] = rx_ready;
// ethernet transmit clock
assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
(eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
assign eth_tx_clk = (eth_tx_mode_1g == 1'b1) ? sys_125m_clk :
(eth_tx_mode_10m_100m_n == 1'b0) ? sys_25m_clk : sys_2m5_clk;
assign eth_phy_resetn = phy_rst_reg;
always@ (posedge eth_mdc) begin
phy_rst_cnt <= phy_rst_cnt + 4'd1;
if (phy_rst_cnt == 4'h0) begin
phy_rst_reg <= sys_pll_locked_s;
phy_rst_reg <= sys_pll_locked;
end
end
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
.dio_t ({11'h7ff, 16'h0}),
.dio_i (gpio_o[26:0]),
.dio_o (gpio_i[26:0]),
.dio_p (gpio_bd));
altddio_out #(.width(1)) i_eth_tx_clk_out (
.aset (1'b0),
.sset (1'b0),
@ -236,104 +239,17 @@ module system_top (
.datain_h (1'b1),
.datain_l (1'b0),
.outclocken (1'b1),
.aclr (eth_tx_reset_s),
.aclr (~sys_pll_locked),
.outclock (eth_tx_clk),
.dataout (eth_tx_clk_out));
assign eth_tx_reset_s = ~sys_pll_locked_s;
always @(posedge rx_clk) begin
rx_sysref_m1 <= rx_sysref_s;
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_m3 <= rx_sysref_m2;
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
end
always @(posedge rx_clk) begin
dma0_wr <= adc0_enable_a_s & adc0_enable_b_s;
dma0_wdata <= { adc0_data_b_s[31:16],
adc0_data_a_s[31:16],
adc0_data_b_s[15: 0],
adc0_data_a_s[15: 0]};
dma1_wr <= adc1_enable_a_s & adc1_enable_b_s;
dma1_wdata <= { adc1_data_b_s[31:16],
adc1_data_a_s[31:16],
adc1_data_b_s[15: 0],
adc1_data_a_s[15: 0]};
end
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (130),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
.sld_node_crc_bits (32),
.sld_node_crc_hiword (10311),
.sld_node_crc_loword (14297),
.sld_node_info (1076736),
.sld_ram_block_type ("AUTO"),
.sld_sample_depth (1024),
.sld_storage_qualifier_gap_record (0),
.sld_storage_qualifier_mode ("OFF"),
.sld_trigger_bits (2),
.sld_trigger_in_enabled (0),
.sld_trigger_level (1),
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (rx_clk),
.acq_data_in ({ rx_sysref,
rx_sync,
adc1_data_b_s,
adc1_data_a_s,
adc0_data_b_s,
adc0_data_a_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_align_1
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_data (rx_data_s[n*32+31:n*32]));
end
endgenerate
assign rx_xcvr_status_s[15:15] = 1'd0;
assign rx_xcvr_status_s[14:14] = rx_sync;
assign rx_xcvr_status_s[13:13] = rx_ready_s;
assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
.rx_clk (rx_clk),
.rx_rstn (sys_resetn),
.rx_sw_rstn (rx_sw_rstn_s),
.rx_pll_locked (rx_pll_locked_s),
.rx_cal_busy (rx_cal_busy_s),
.rx_cdr_locked (rx_cdr_locked_s),
.rx_analog_reset (rx_analog_reset_s),
.rx_digital_reset (rx_digital_reset_s),
.rx_ready (rx_ready_s),
.rx_rst_state (rx_rst_state_s));
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn),
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),
.sys_clk_clk (sys_clk),
.sys_clk_out_clk (sys_pll_clk),
.sys_ddr3_oct_rzqin (ddr3_rzq),
.sys_ddr3_phy_mem_a (ddr3_a),
.sys_ddr3_phy_mem_ba (ddr3_ba),
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
@ -349,77 +265,38 @@ module system_top (
.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
.sys_ddr3_phy_mem_odt (ddr3_odt),
.sys_ddr3_oct_rzqin (ddr3_rzq),
.sys_ethernet_tx_clk_clk (eth_tx_clk),
.sys_ethernet_rx_clk_clk (eth_rx_clk),
.sys_ethernet_status_set_10 (),
.sys_ethernet_status_set_1000 (),
.sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_gpio_in_port ({rx_xcvr_status_s, 5'd0, push_buttons, dip_switches}),
.sys_gpio_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}),
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.sys_ethernet_rx_clk_clk (eth_rx_clk),
.sys_ethernet_status_set_10 (),
.sys_ethernet_status_set_1000 (),
.sys_ethernet_status_eth_mode (eth_tx_mode_1g),
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
.sys_ethernet_tx_clk_clk (eth_tx_clk),
.sys_gpio_in_port (gpio_i[63:32]),
.sys_gpio_out_port (gpio_o[63:32]),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_gpio_jesd_in_port (gpio_jesd_i[31:0]),
.sys_gpio_jesd_out_port (gpio_jesd_o[31:0]),
.sys_pll_locked_export (sys_pll_locked),
.sys_reset_reset_n (sys_resetn),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.axi_ad9250_0_xcvr_clk_clk (rx_clk),
.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
.axi_ad9250_0_adc_clock_clk (adc0_clk),
.axi_ad9250_0_adc_dma_if_adc_valid_a (),
.axi_ad9250_0_adc_dma_if_adc_enable_a (adc0_enable_a_s),
.axi_ad9250_0_adc_dma_if_adc_data_a (adc0_data_a_s),
.axi_ad9250_0_adc_dma_if_adc_valid_b (),
.axi_ad9250_0_adc_dma_if_adc_enable_b (adc0_enable_b_s),
.axi_ad9250_0_adc_dma_if_adc_data_b (adc0_data_b_s),
.axi_ad9250_0_adc_dma_if_adc_dovf (adc0_dovf_s),
.axi_ad9250_0_adc_dma_if_adc_dunf (1'b0),
.axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
.axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
.axi_dmac_0_fifo_wr_if_wren (dma0_wr),
.axi_dmac_0_fifo_wr_if_data (dma0_wdata),
.axi_dmac_0_fifo_wr_if_sync (1'b1),
.axi_ad9250_1_xcvr_clk_clk (rx_clk),
.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
.axi_ad9250_1_adc_clock_clk (adc1_clk),
.axi_ad9250_1_adc_dma_if_adc_valid_a (),
.axi_ad9250_1_adc_dma_if_adc_enable_a (adc1_enable_a_s),
.axi_ad9250_1_adc_dma_if_adc_data_a (adc1_data_a_s),
.axi_ad9250_1_adc_dma_if_adc_valid_b (),
.axi_ad9250_1_adc_dma_if_adc_enable_b (adc1_enable_b_s),
.axi_ad9250_1_adc_dma_if_adc_data_b (adc1_data_b_s),
.axi_ad9250_1_adc_dma_if_adc_dovf (adc1_dovf_s),
.axi_ad9250_1_adc_dma_if_adc_dunf (1'b0),
.axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
.axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
.axi_dmac_1_fifo_wr_if_wren (dma1_wr),
.axi_dmac_1_fifo_wr_if_data (dma1_wdata),
.axi_dmac_1_fifo_wr_if_sync (1'b1),
.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
.sys_jesd204b_s1_rx_link_valid (),
.sys_jesd204b_s1_rx_link_ready (1'b1),
.sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sysref_export (rx_sysref),
.sys_jesd204b_s1_rx_ferr_export (rx_err_s),
.sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sync_n_export (rx_sync),
.sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
.sys_jesd204b_s1_locked_rx_is_lockedtodata (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_rx_cal_busy (rx_cal_busy_s),
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
.sys_pll_locked_export (sys_pll_locked_s));
.sys_xcvr_reset_reset (gpio_jesd_o[15]),
.sys_xcvr_rstcntrl_rx_ready_rx_ready (rx_ready),
.sys_xcvr_rx_ref_clk_clk (ref_clk),
.sys_xcvr_rx_sync_n_export (rx_sync),
.sys_xcvr_rx_sysref_export (rx_sysref),
.sys_xcvr_rxd_rx_serial_data (rx_data));
endmodule