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daq2 : Integrate the DACFIFO into the supported projects. 

+ All pack/unpack logic is made by the cpack and upack modules.
+ The DAC FIFO is integrated between the TX DMA and cpack.
+ All the top files are updated, all the projects compiled successfully.
main
Istvan Csomortani 2015-05-11 12:17:59 +03:00
parent bad821ba1c
commit 15618c9edf
13 changed files with 120 additions and 740 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

144
projects/daq2/common/daq2_bd.tcl
View File

@ -13,33 +13,6 @@ create_bd_port -dir I tx_sysref
create_bd_port -dir O -from 3 -to 0 tx_data_p
create_bd_port -dir O -from 3 -to 0 tx_data_n
create_bd_port -dir O dac_clk
create_bd_port -dir O dac_valid_0
create_bd_port -dir O dac_enable_0
create_bd_port -dir I -from 63 -to 0 dac_ddata_0
create_bd_port -dir O dac_valid_1
create_bd_port -dir O dac_enable_1
create_bd_port -dir I -from 63 -to 0 dac_ddata_1
create_bd_port -dir O dac_valid_2
create_bd_port -dir O dac_enable_2
create_bd_port -dir I -from 63 -to 0 dac_ddata_2
create_bd_port -dir O dac_valid_3
create_bd_port -dir O dac_enable_3
create_bd_port -dir I -from 63 -to 0 dac_ddata_3
create_bd_port -dir I dac_drd
create_bd_port -dir O -from 127 -to 0 dac_ddata
create_bd_port -dir O adc_clk
create_bd_port -dir O adc_enable_0
create_bd_port -dir O adc_valid_0
create_bd_port -dir O -from 63 -to 0 adc_data_0
create_bd_port -dir O adc_enable_1
create_bd_port -dir O adc_valid_1
create_bd_port -dir O -from 63 -to 0 adc_data_1
create_bd_port -dir I adc_dwr
create_bd_port -dir I adc_dsync
create_bd_port -dir I -from 127 -to 0 adc_ddata
# dac peripherals
set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
@ -51,17 +24,21 @@ set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack]
set_property -dict [list CONFIG.CH_DW {64}] $axi_ad9144_upack
set_property -dict [list CONFIG.CH_CNT {2}] $axi_ad9144_upack
# adc peripherals
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
@ -84,6 +61,10 @@ set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
set_property -dict [list CONFIG.CH_DW {64}] $axi_ad9680_cpack
set_property -dict [list CONFIG.CH_CNT {2}] $axi_ad9680_cpack
# dac/adc common gt
set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt]
@ -96,23 +77,23 @@ set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {2}] $axi_daq2_gt
# connections (gt)
ad_connect axi_daq2_gt/ref_clk_q rx_ref_clk
ad_connect axi_daq2_gt/ref_clk_c tx_ref_clk
ad_connect axi_daq2_gt/rx_data_p rx_data_p
ad_connect axi_daq2_gt/rx_data_n rx_data_n
ad_connect axi_daq2_gt/rx_sync rx_sync
ad_connect axi_daq2_gt/rx_ext_sysref rx_sysref
ad_connect axi_daq2_gt/tx_data_p tx_data_p
ad_connect axi_daq2_gt/tx_data_n tx_data_n
ad_connect axi_daq2_gt/tx_sync tx_sync
ad_connect axi_daq2_gt/tx_ext_sysref tx_sysref
ad_connect axi_daq2_gt/ref_clk_q rx_ref_clk
ad_connect axi_daq2_gt/ref_clk_c tx_ref_clk
ad_connect axi_daq2_gt/rx_data_p rx_data_p
ad_connect axi_daq2_gt/rx_data_n rx_data_n
ad_connect axi_daq2_gt/rx_sync rx_sync
ad_connect axi_daq2_gt/rx_ext_sysref rx_sysref
ad_connect axi_daq2_gt/tx_data_p tx_data_p
ad_connect axi_daq2_gt/tx_data_n tx_data_n
ad_connect axi_daq2_gt/tx_sync tx_sync
ad_connect axi_daq2_gt/tx_ext_sysref tx_sysref
# connections (dac)
ad_connect axi_daq2_gt/tx_clk_g dac_clk
ad_connect axi_daq2_gt/tx_clk_g axi_daq2_gt/tx_clk
ad_connect axi_daq2_gt/tx_clk_g axi_ad9144_core/tx_clk
ad_connect axi_daq2_gt/tx_clk_g axi_ad9144_jesd/tx_core_clk
ad_connect axi_daq2_gt/tx_clk_g axi_ad9144_upack/dac_clk
ad_connect axi_daq2_gt/tx_rst axi_ad9144_jesd/tx_reset
ad_connect axi_daq2_gt/tx_sysref axi_ad9144_jesd/tx_sysref
@ -120,52 +101,54 @@ create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_char
set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_ccat_tx_gt_charisk]
set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_ccat_tx_gt_charisk]
ad_connect util_ccat_tx_gt_charisk/ccat_data axi_daq2_gt/tx_gt_charisk
ad_connect util_ccat_tx_gt_charisk/data_0 axi_ad9144_jesd/gt0_txcharisk
ad_connect util_ccat_tx_gt_charisk/data_1 axi_ad9144_jesd/gt1_txcharisk
ad_connect util_ccat_tx_gt_charisk/data_2 axi_ad9144_jesd/gt2_txcharisk
ad_connect util_ccat_tx_gt_charisk/data_3 axi_ad9144_jesd/gt3_txcharisk
ad_connect util_ccat_tx_gt_charisk/ccat_data axi_daq2_gt/tx_gt_charisk
ad_connect util_ccat_tx_gt_charisk/data_0 axi_ad9144_jesd/gt0_txcharisk
ad_connect util_ccat_tx_gt_charisk/data_1 axi_ad9144_jesd/gt1_txcharisk
ad_connect util_ccat_tx_gt_charisk/data_2 axi_ad9144_jesd/gt2_txcharisk
ad_connect util_ccat_tx_gt_charisk/data_3 axi_ad9144_jesd/gt3_txcharisk
create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_data
set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_ccat_tx_gt_data]
set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_ccat_tx_gt_data]
ad_connect util_ccat_tx_gt_data/ccat_data axi_daq2_gt/tx_gt_data
ad_connect util_ccat_tx_gt_data/data_0 axi_ad9144_jesd/gt0_txdata
ad_connect util_ccat_tx_gt_data/data_1 axi_ad9144_jesd/gt1_txdata
ad_connect util_ccat_tx_gt_data/data_2 axi_ad9144_jesd/gt2_txdata
ad_connect util_ccat_tx_gt_data/data_3 axi_ad9144_jesd/gt3_txdata
ad_connect util_ccat_tx_gt_data/ccat_data axi_daq2_gt/tx_gt_data
ad_connect util_ccat_tx_gt_data/data_0 axi_ad9144_jesd/gt0_txdata
ad_connect util_ccat_tx_gt_data/data_1 axi_ad9144_jesd/gt1_txdata
ad_connect util_ccat_tx_gt_data/data_2 axi_ad9144_jesd/gt2_txdata
ad_connect util_ccat_tx_gt_data/data_3 axi_ad9144_jesd/gt3_txdata
ad_connect axi_daq2_gt/tx_rst_done axi_ad9144_jesd/tx_reset_done
ad_connect axi_daq2_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
ad_connect axi_daq2_gt/tx_ip_sof axi_ad9144_jesd/tx_start_of_frame
ad_connect axi_daq2_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
ad_connect axi_daq2_gt/tx_data axi_ad9144_core/tx_data
ad_connect axi_ad9144_core/dac_clk axi_ad9144_dma/fifo_rd_clk
ad_connect axi_ad9144_core/dac_valid_0 dac_valid_0
ad_connect axi_ad9144_core/dac_enable_0 dac_enable_0
ad_connect axi_ad9144_core/dac_ddata_0 dac_ddata_0
ad_connect axi_ad9144_core/dac_valid_1 dac_valid_1
ad_connect axi_ad9144_core/dac_enable_1 dac_enable_1
ad_connect axi_ad9144_core/dac_ddata_1 dac_ddata_1
ad_connect axi_ad9144_core/dac_valid_2 dac_valid_2
ad_connect axi_ad9144_core/dac_enable_2 dac_enable_2
ad_connect axi_ad9144_core/dac_ddata_2 dac_ddata_2
ad_connect axi_ad9144_core/dac_valid_3 dac_valid_3
ad_connect axi_ad9144_core/dac_enable_3 dac_enable_3
ad_connect axi_ad9144_core/dac_ddata_3 dac_ddata_3
ad_connect dac_drd axi_ad9144_dma/fifo_rd_en
ad_connect dac_ddata axi_ad9144_dma/fifo_rd_dout
ad_connect axi_ad9144_core/dac_dunf axi_ad9144_dma/fifo_rd_underflow
ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1
ad_connect axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1
ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1
ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk
ad_connect axi_ad9144_dma/m_axis_xfer_req axi_ad9144_fifo/dma_xfer_req
ad_connect axi_ad9144_dma/m_axis_aclk axi_ad9144_fifo/dma_clk
ad_connect axi_ad9144_dma/m_axis_ready axi_ad9144_fifo/dma_ready
ad_connect axi_ad9144_dma/m_axis_data axi_ad9144_fifo/dma_data
ad_connect axi_ad9144_dma/m_axis_valid axi_ad9144_fifo/dma_valid
ad_connect axi_ad9144_dma/m_axis_last axi_ad9144_fifo/dma_xfer_last
ad_connect axi_ad9144_fifo/dac_clk axi_daq2_gt/tx_clk
ad_connect axi_ad9144_fifo/dac_valid axi_ad9144_upack/dac_valid
ad_connect axi_ad9144_fifo/dac_data axi_ad9144_upack/dac_data
# connections (adc)
ad_connect axi_daq2_gt/rx_clk_g adc_clk
ad_connect axi_daq2_gt/rx_clk_g axi_daq2_gt/rx_clk
ad_connect axi_daq2_gt/rx_clk_g axi_ad9680_core/rx_clk
ad_connect axi_daq2_gt/rx_clk_g axi_ad9680_jesd/rx_core_clk
ad_connect axi_daq2_gt/rx_jesd_rst axi_ad9680_jesd/rx_reset
ad_connect axi_daq2_gt/rx_clk_g axi_ad9680_cpack/adc_clk
ad_connect axi_daq2_gt/rx_sysref axi_ad9680_jesd/rx_sysref
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
@ -214,18 +197,19 @@ ad_connect axi_daq2_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
ad_connect axi_daq2_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
ad_connect axi_daq2_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
ad_connect axi_daq2_gt/rx_data axi_ad9680_core/rx_data
ad_connect axi_ad9680_core/adc_enable_0 adc_enable_0
ad_connect axi_ad9680_core/adc_valid_0 adc_valid_0
ad_connect axi_ad9680_core/adc_data_0 adc_data_0
ad_connect axi_ad9680_core/adc_enable_1 adc_enable_1
ad_connect axi_ad9680_core/adc_valid_1 adc_valid_1
ad_connect axi_ad9680_core/adc_data_1 adc_data_1
ad_connect axi_daq2_gt/rx_rst axi_ad9680_fifo/adc_rst
ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
ad_connect axi_daq2_gt/rx_rst axi_ad9680_fifo/adc_rst
ad_connect axi_daq2_gt/rx_rst axi_ad9680_cpack/adc_rst
ad_connect axi_ad9680_core/adc_clk axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
ad_connect adc_dwr axi_ad9680_fifo/adc_wr
ad_connect adc_ddata axi_ad9680_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
@ -247,7 +231,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_daq2_gt/m_axi
ad_connect sys_cpu_resetn axi_daq2_gt/m_axi_aresetn
ad_connect sys_cpu_resetn axi_daq2_gt/m_axi_aresetn
ad_connect sys_cpu_clk axi_daq2_gt/drp_clk
# interconnect (mem/dac)
@ -259,6 +243,6 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
# interrupts
ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq

6
projects/daq2/kc705/Makefile
View File

@ -15,8 +15,10 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
M_DEPS += ../common/daq2_bd.tcl
M_DEPS += ../../common/kc705/kc705_system_mig.prj
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
@ -48,8 +50,10 @@ clean:
clean-all:clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/axi_ad9680 clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_adcfifo clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/util_dacfifo clean
@ -64,8 +68,10 @@ daq2_kc705.xpr: $(M_DEPS)
lib:
make -C ../../../library/axi_jesd_gt
make -C ../../../library/util_cpack
make -C ../../../library/util_bsplit
make -C ../../../library/axi_ad9680
make -C ../../../library/util_upack
make -C ../../../library/util_adcfifo
make -C ../../../library/axi_dmac
make -C ../../../library/util_dacfifo

1
projects/daq2/kc705/system_bd.tcl
View File

@ -3,6 +3,7 @@ source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl

170
projects/daq2/kc705/system_top.v
View File

@ -148,15 +148,15 @@ module system_top (
output ddr3_cas_n;
output ddr3_ras_n;
output ddr3_we_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output ddr3_ck_n;
output ddr3_ck_p;
output ddr3_cke;
output ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_odt;
output mdio_mdc;
inout mdio_mdio;
@ -225,17 +225,6 @@ module system_top (
inout spi_sdio;
output spi_dir;
// internal registers
reg dac_drd = 'd0;
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg [63:0] dac_ddata_2 = 'd0;
reg [63:0] dac_ddata_3 = 'd0;
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [127:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -251,130 +240,6 @@ module system_top (
wire tx_ref_clk;
wire tx_sysref;
wire tx_sync;
wire dac_clk;
wire [127:0] dac_ddata;
wire dac_enable_0;
wire dac_enable_1;
wire dac_enable_2;
wire dac_enable_3;
wire dac_valid_0;
wire dac_valid_1;
wire dac_valid_2;
wire dac_valid_3;
wire adc_clk;
wire [63:0] adc_data_0;
wire [63:0] adc_data_1;
wire adc_enable_0;
wire adc_enable_1;
wire adc_valid_0;
wire adc_valid_1;
// adc-dac data
always @(posedge dac_clk) begin
case ({dac_enable_1, dac_enable_0})
2'b11: begin
dac_drd <= dac_valid_0 & dac_valid_1;
dac_ddata_0[63:48] <= dac_ddata[111: 96];
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b10: begin
dac_drd <= dac_valid_1 & ~dac_drd;
dac_ddata_0 <= 64'd0;
if (dac_drd == 1'b1) begin
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[111: 96];
dac_ddata_1[31:16] <= dac_ddata[ 95: 80];
dac_ddata_1[15: 0] <= dac_ddata[ 79: 64];
end else begin
dac_ddata_1[63:48] <= dac_ddata[ 63: 48];
dac_ddata_1[47:32] <= dac_ddata[ 47: 32];
dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b01: begin
dac_drd <= dac_valid_0 & ~dac_drd;
if (dac_drd == 1'b1) begin
dac_ddata_0[63:48] <= dac_ddata[127:112];
dac_ddata_0[47:32] <= dac_ddata[111: 96];
dac_ddata_0[31:16] <= dac_ddata[ 95: 80];
dac_ddata_0[15: 0] <= dac_ddata[ 79: 64];
end else begin
dac_ddata_0[63:48] <= dac_ddata[ 63: 48];
dac_ddata_0[47:32] <= dac_ddata[ 47: 32];
dac_ddata_0[31:16] <= dac_ddata[ 31: 16];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
default: begin
dac_drd <= 1'b0;
dac_ddata_0 <= 64'd0;
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
endcase
end
always @(posedge adc_clk) begin
case ({adc_enable_1, adc_enable_0})
2'b11: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & adc_valid_0;
adc_ddata[127:112] <= adc_data_1[63:48];
adc_ddata[111: 96] <= adc_data_0[63:48];
adc_ddata[ 95: 80] <= adc_data_1[47:32];
adc_ddata[ 79: 64] <= adc_data_0[47:32];
adc_ddata[ 63: 48] <= adc_data_1[31:16];
adc_ddata[ 47: 32] <= adc_data_0[31:16];
adc_ddata[ 31: 16] <= adc_data_1[15: 0];
adc_ddata[ 15: 0] <= adc_data_0[15: 0];
end
2'b10: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & ~adc_dwr;
adc_ddata[127:112] <= adc_data_1[63:48];
adc_ddata[111: 96] <= adc_data_1[47:32];
adc_ddata[ 95: 80] <= adc_data_1[31:16];
adc_ddata[ 79: 64] <= adc_data_1[15: 0];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
2'b01: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_0 & ~adc_dwr;
adc_ddata[127:112] <= adc_data_0[63:48];
adc_ddata[111: 96] <= adc_data_0[47:32];
adc_ddata[ 95: 80] <= adc_data_0[31:16];
adc_ddata[ 79: 64] <= adc_data_0[15: 0];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
default: begin
adc_dsync <= 1'b0;
adc_dwr <= 1'b0;
adc_ddata <= 128'd0;
end
endcase
end
// spi
@ -460,31 +325,6 @@ module system_top (
.dio (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_ddata (adc_ddata),
.adc_dsync (adc_dsync),
.adc_dwr (adc_dwr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_ddata (dac_ddata),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_ddata_2 (dac_ddata_2),
.dac_ddata_3 (dac_ddata_3),
.dac_drd (dac_drd),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_enable_2 (dac_enable_2),
.dac_enable_3 (dac_enable_3),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.dac_valid_2 (dac_valid_2),
.dac_valid_3 (dac_valid_3),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),

6
projects/daq2/kcu105/Makefile
View File

@ -15,8 +15,10 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
M_DEPS += ../common/daq2_bd.tcl
M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
@ -48,8 +50,10 @@ clean:
clean-all:clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/axi_ad9680 clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_adcfifo clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/util_dacfifo clean
@ -64,8 +68,10 @@ daq2_kcu105.xpr: $(M_DEPS)
lib:
make -C ../../../library/axi_jesd_gt
make -C ../../../library/util_cpack
make -C ../../../library/util_bsplit
make -C ../../../library/axi_ad9680
make -C ../../../library/util_upack
make -C ../../../library/util_adcfifo
make -C ../../../library/axi_dmac
make -C ../../../library/util_dacfifo

1
projects/daq2/kcu105/system_bd.tcl
View File

@ -3,6 +3,7 @@ source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl

188
projects/daq2/kcu105/system_top.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -88,7 +88,7 @@ module system_top (
rx_sync_n,
rx_data_p,
rx_data_n,
tx_ref_clk_p,
tx_ref_clk_n,
tx_sysref_p,
@ -97,7 +97,7 @@ module system_top (
tx_sync_n,
tx_data_p,
tx_data_n,
trig_p,
trig_n,
@ -105,12 +105,12 @@ module system_top (
adc_fda,
dac_irq,
clkd_status,
adc_pd,
dac_txen,
dac_reset,
clkd_sync,
spi_csn_clk,
spi_csn_dac,
spi_csn_adc,
@ -165,7 +165,7 @@ module system_top (
output rx_sync_n;
input [ 3:0] rx_data_p;
input [ 3:0] rx_data_n;
input tx_ref_clk_p;
input tx_ref_clk_n;
input tx_sysref_p;
@ -174,37 +174,26 @@ module system_top (
input tx_sync_n;
output [ 3:0] tx_data_p;
output [ 3:0] tx_data_n;
input trig_p;
input trig_n;
inout adc_fdb;
inout adc_fda;
inout dac_irq;
inout [ 1:0] clkd_status;
inout adc_pd;
inout dac_txen;
inout dac_reset;
inout clkd_sync;
output spi_csn_clk;
output spi_csn_dac;
output spi_csn_adc;
output spi_clk;
inout spi_sdio;
output spi_dir;
// internal registers
reg dac_drd = 'd0;
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg [63:0] dac_ddata_2 = 'd0;
reg [63:0] dac_ddata_3 = 'd0;
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [127:0] adc_ddata = 'd0;
// internal signals
@ -221,130 +210,6 @@ module system_top (
wire tx_ref_clk;
wire tx_sysref;
wire tx_sync;
wire dac_clk;
wire [127:0] dac_ddata;
wire dac_enable_0;
wire dac_enable_1;
wire dac_enable_2;
wire dac_enable_3;
wire dac_valid_0;
wire dac_valid_1;
wire dac_valid_2;
wire dac_valid_3;
wire adc_clk;
wire [63:0] adc_data_0;
wire [63:0] adc_data_1;
wire adc_enable_0;
wire adc_enable_1;
wire adc_valid_0;
wire adc_valid_1;
// adc-dac data
always @(posedge dac_clk) begin
case ({dac_enable_1, dac_enable_0})
2'b11: begin
dac_drd <= dac_valid_0 & dac_valid_1;
dac_ddata_0[63:48] <= dac_ddata[111: 96];
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b10: begin
dac_drd <= dac_valid_1 & ~dac_drd;
dac_ddata_0 <= 64'd0;
if (dac_drd == 1'b1) begin
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[111: 96];
dac_ddata_1[31:16] <= dac_ddata[ 95: 80];
dac_ddata_1[15: 0] <= dac_ddata[ 79: 64];
end else begin
dac_ddata_1[63:48] <= dac_ddata[ 63: 48];
dac_ddata_1[47:32] <= dac_ddata[ 47: 32];
dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b01: begin
dac_drd <= dac_valid_0 & ~dac_drd;
if (dac_drd == 1'b1) begin
dac_ddata_0[63:48] <= dac_ddata[127:112];
dac_ddata_0[47:32] <= dac_ddata[111: 96];
dac_ddata_0[31:16] <= dac_ddata[ 95: 80];
dac_ddata_0[15: 0] <= dac_ddata[ 79: 64];
end else begin
dac_ddata_0[63:48] <= dac_ddata[ 63: 48];
dac_ddata_0[47:32] <= dac_ddata[ 47: 32];
dac_ddata_0[31:16] <= dac_ddata[ 31: 16];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
default: begin
dac_drd <= 1'b0;
dac_ddata_0 <= 64'd0;
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
endcase
end
always @(posedge adc_clk) begin
case ({adc_enable_1, adc_enable_0})
2'b11: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & adc_valid_0;
adc_ddata[127:112] <= adc_data_1[63:48];
adc_ddata[111: 96] <= adc_data_0[63:48];
adc_ddata[ 95: 80] <= adc_data_1[47:32];
adc_ddata[ 79: 64] <= adc_data_0[47:32];
adc_ddata[ 63: 48] <= adc_data_1[31:16];
adc_ddata[ 47: 32] <= adc_data_0[31:16];
adc_ddata[ 31: 16] <= adc_data_1[15: 0];
adc_ddata[ 15: 0] <= adc_data_0[15: 0];
end
2'b10: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & ~adc_dwr;
adc_ddata[127:112] <= adc_data_1[63:48];
adc_ddata[111: 96] <= adc_data_1[47:32];
adc_ddata[ 95: 80] <= adc_data_1[31:16];
adc_ddata[ 79: 64] <= adc_data_1[15: 0];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
2'b01: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_0 & ~adc_dwr;
adc_ddata[127:112] <= adc_data_0[63:48];
adc_ddata[111: 96] <= adc_data_0[47:32];
adc_ddata[ 95: 80] <= adc_data_0[31:16];
adc_ddata[ 79: 64] <= adc_data_0[15: 0];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
default: begin
adc_dsync <= 1'b0;
adc_dwr <= 1'b0;
adc_ddata <= 128'd0;
end
endcase
end
// spi
@ -427,16 +292,6 @@ module system_top (
.dio (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_ddata (adc_ddata),
.adc_dsync (adc_dsync),
.adc_dwr (adc_dwr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.c0_ddr4_act_n (ddr4_act_n),
.c0_ddr4_adr (ddr4_addr),
.c0_ddr4_ba (ddr4_ba),
@ -451,21 +306,6 @@ module system_top (
.c0_ddr4_dqs_t (ddr4_dqs_p),
.c0_ddr4_odt (ddr4_odt),
.c0_ddr4_reset_n (ddr4_reset_n),
.dac_clk (dac_clk),
.dac_ddata (dac_ddata),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_ddata_2 (dac_ddata_2),
.dac_ddata_3 (dac_ddata_3),
.dac_drd (dac_drd),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_enable_2 (dac_enable_2),
.dac_enable_3 (dac_enable_3),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.dac_valid_2 (dac_valid_2),
.dac_valid_3 (dac_valid_3),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),

6
projects/daq2/vc707/Makefile
View File

@ -15,8 +15,10 @@ M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
M_DEPS += ../common/daq2_bd.tcl
M_DEPS += ../../common/vc707/vc707_system_mig.prj
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
@ -48,8 +50,10 @@ clean:
clean-all:clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/axi_ad9680 clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_adcfifo clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/util_dacfifo clean
@ -64,8 +68,10 @@ daq2_vc707.xpr: $(M_DEPS)
lib:
make -C ../../../library/axi_jesd_gt
make -C ../../../library/util_cpack
make -C ../../../library/util_bsplit
make -C ../../../library/axi_ad9680
make -C ../../../library/util_upack
make -C ../../../library/util_adcfifo
make -C ../../../library/axi_dmac
make -C ../../../library/util_dacfifo

1
projects/daq2/vc707/system_bd.tcl
View File

@ -3,6 +3,7 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl

160
projects/daq2/vc707/system_top.v
View File

@ -215,17 +215,6 @@ module system_top (
inout spi_sdio;
output spi_dir;
// internal registers
reg dac_drd = 'd0;
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg [63:0] dac_ddata_2 = 'd0;
reg [63:0] dac_ddata_3 = 'd0;
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [127:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -241,130 +230,6 @@ module system_top (
wire tx_ref_clk;
wire tx_sysref;
wire tx_sync;
wire dac_clk;
wire [127:0] dac_ddata;
wire dac_enable_0;
wire dac_enable_1;
wire dac_enable_2;
wire dac_enable_3;
wire dac_valid_0;
wire dac_valid_1;
wire dac_valid_2;
wire dac_valid_3;
wire adc_clk;
wire [63:0] adc_data_0;
wire [63:0] adc_data_1;
wire adc_enable_0;
wire adc_enable_1;
wire adc_valid_0;
wire adc_valid_1;
// adc-dac data
always @(posedge dac_clk) begin
case ({dac_enable_1, dac_enable_0})
2'b11: begin
dac_drd <= dac_valid_0 & dac_valid_1;
dac_ddata_0[63:48] <= dac_ddata[111: 96];
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b10: begin
dac_drd <= dac_valid_1 & ~dac_drd;
dac_ddata_0 <= 64'd0;
if (dac_drd == 1'b1) begin
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[111: 96];
dac_ddata_1[31:16] <= dac_ddata[ 95: 80];
dac_ddata_1[15: 0] <= dac_ddata[ 79: 64];
end else begin
dac_ddata_1[63:48] <= dac_ddata[ 63: 48];
dac_ddata_1[47:32] <= dac_ddata[ 47: 32];
dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b01: begin
dac_drd <= dac_valid_0 & ~dac_drd;
if (dac_drd == 1'b1) begin
dac_ddata_0[63:48] <= dac_ddata[127:112];
dac_ddata_0[47:32] <= dac_ddata[111: 96];
dac_ddata_0[31:16] <= dac_ddata[ 95: 80];
dac_ddata_0[15: 0] <= dac_ddata[ 79: 64];
end else begin
dac_ddata_0[63:48] <= dac_ddata[ 63: 48];
dac_ddata_0[47:32] <= dac_ddata[ 47: 32];
dac_ddata_0[31:16] <= dac_ddata[ 31: 16];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
default: begin
dac_drd <= 1'b0;
dac_ddata_0 <= 64'd0;
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
endcase
end
always @(posedge adc_clk) begin
case ({adc_enable_1, adc_enable_0})
2'b11: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & adc_valid_0;
adc_ddata[127:112] <= adc_data_1[63:48];
adc_ddata[111: 96] <= adc_data_0[63:48];
adc_ddata[ 95: 80] <= adc_data_1[47:32];
adc_ddata[ 79: 64] <= adc_data_0[47:32];
adc_ddata[ 63: 48] <= adc_data_1[31:16];
adc_ddata[ 47: 32] <= adc_data_0[31:16];
adc_ddata[ 31: 16] <= adc_data_1[15: 0];
adc_ddata[ 15: 0] <= adc_data_0[15: 0];
end
2'b10: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & ~adc_dwr;
adc_ddata[127:112] <= adc_data_1[63:48];
adc_ddata[111: 96] <= adc_data_1[47:32];
adc_ddata[ 95: 80] <= adc_data_1[31:16];
adc_ddata[ 79: 64] <= adc_data_1[15: 0];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
2'b01: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_0 & ~adc_dwr;
adc_ddata[127:112] <= adc_data_0[63:48];
adc_ddata[111: 96] <= adc_data_0[47:32];
adc_ddata[ 95: 80] <= adc_data_0[31:16];
adc_ddata[ 79: 64] <= adc_data_0[15: 0];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
default: begin
adc_dsync <= 1'b0;
adc_dwr <= 1'b0;
adc_ddata <= 128'd0;
end
endcase
end
// spi
@ -448,31 +313,6 @@ module system_top (
.dio (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_ddata (adc_ddata),
.adc_dsync (adc_dsync),
.adc_dwr (adc_dwr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_ddata (dac_ddata),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_ddata_2 (dac_ddata_2),
.dac_ddata_3 (dac_ddata_3),
.dac_drd (dac_drd),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_enable_2 (dac_enable_2),
.dac_enable_3 (dac_enable_3),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.dac_valid_2 (dac_valid_2),
.dac_valid_3 (dac_valid_3),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),

13
projects/daq2/zc706/Makefile
View File

@ -12,13 +12,18 @@ M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += system_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl
M_DEPS += ../../common/xilinx/sys_dmafifo.tcl
M_DEPS += ../common/daq2_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_mig.prj
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_ccat/util_ccat.xpr
M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
@ -50,10 +55,14 @@ clean:
clean-all:clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/axi_ad9680 clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_adcfifo clean
make -C ../../../library/axi_adcfifo clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/util_dacfifo clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_ccat clean
make -C ../../../library/axi_ad9144 clean
@ -68,10 +77,14 @@ daq2_zc706.xpr: $(M_DEPS)
lib:
make -C ../../../library/axi_jesd_gt
make -C ../../../library/util_cpack
make -C ../../../library/util_bsplit
make -C ../../../library/axi_ad9680
make -C ../../../library/util_upack
make -C ../../../library/util_adcfifo
make -C ../../../library/axi_adcfifo
make -C ../../../library/axi_dmac
make -C ../../../library/util_dacfifo
make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_ccat
make -C ../../../library/axi_ad9144

4
projects/daq2/zc706/system_bd.tcl
View File

@ -1,14 +1,16 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9680_fifo/sys_rst
ad_connect sys_clk axi_ad9680_fifo/sys_clk

160
projects/daq2/zc706/system_top.v
View File

@ -229,17 +229,6 @@ module system_top (
inout spi_sdio;
output spi_dir;
// internal registers
reg dac_drd = 'd0;
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg [63:0] dac_ddata_2 = 'd0;
reg [63:0] dac_ddata_3 = 'd0;
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [127:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -260,130 +249,6 @@ module system_top (
wire tx_ref_clk;
wire tx_sysref;
wire tx_sync;
wire dac_clk;
wire [127:0] dac_ddata;
wire dac_enable_0;
wire dac_enable_1;
wire dac_enable_2;
wire dac_enable_3;
wire dac_valid_0;
wire dac_valid_1;
wire dac_valid_2;
wire dac_valid_3;
wire adc_clk;
wire [63:0] adc_data_0;
wire [63:0] adc_data_1;
wire adc_enable_0;
wire adc_enable_1;
wire adc_valid_0;
wire adc_valid_1;
// adc-dac data
always @(posedge dac_clk) begin
case ({dac_enable_1, dac_enable_0})
2'b11: begin
dac_drd <= dac_valid_0 & dac_valid_1;
dac_ddata_0[63:48] <= dac_ddata[111: 96];
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b10: begin
dac_drd <= dac_valid_1 & ~dac_drd;
dac_ddata_0 <= 64'd0;
if (dac_drd == 1'b1) begin
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[111: 96];
dac_ddata_1[31:16] <= dac_ddata[ 95: 80];
dac_ddata_1[15: 0] <= dac_ddata[ 79: 64];
end else begin
dac_ddata_1[63:48] <= dac_ddata[ 63: 48];
dac_ddata_1[47:32] <= dac_ddata[ 47: 32];
dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
2'b01: begin
dac_drd <= dac_valid_0 & ~dac_drd;
if (dac_drd == 1'b1) begin
dac_ddata_0[63:48] <= dac_ddata[127:112];
dac_ddata_0[47:32] <= dac_ddata[111: 96];
dac_ddata_0[31:16] <= dac_ddata[ 95: 80];
dac_ddata_0[15: 0] <= dac_ddata[ 79: 64];
end else begin
dac_ddata_0[63:48] <= dac_ddata[ 63: 48];
dac_ddata_0[47:32] <= dac_ddata[ 47: 32];
dac_ddata_0[31:16] <= dac_ddata[ 31: 16];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
end
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
default: begin
dac_drd <= 1'b0;
dac_ddata_0 <= 64'd0;
dac_ddata_1 <= 64'd0;
dac_ddata_2 <= 64'd0;
dac_ddata_3 <= 64'd0;
end
endcase
end
always @(posedge adc_clk) begin
case ({adc_enable_1, adc_enable_0})
2'b11: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & adc_valid_0;
adc_ddata[127:112] <= adc_data_1[63:48];
adc_ddata[111: 96] <= adc_data_0[63:48];
adc_ddata[ 95: 80] <= adc_data_1[47:32];
adc_ddata[ 79: 64] <= adc_data_0[47:32];
adc_ddata[ 63: 48] <= adc_data_1[31:16];
adc_ddata[ 47: 32] <= adc_data_0[31:16];
adc_ddata[ 31: 16] <= adc_data_1[15: 0];
adc_ddata[ 15: 0] <= adc_data_0[15: 0];
end
2'b10: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & ~adc_dwr;
adc_ddata[127:112] <= adc_data_1[63:48];
adc_ddata[111: 96] <= adc_data_1[47:32];
adc_ddata[ 95: 80] <= adc_data_1[31:16];
adc_ddata[ 79: 64] <= adc_data_1[15: 0];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
2'b01: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_0 & ~adc_dwr;
adc_ddata[127:112] <= adc_data_0[63:48];
adc_ddata[111: 96] <= adc_data_0[47:32];
adc_ddata[ 95: 80] <= adc_data_0[31:16];
adc_ddata[ 79: 64] <= adc_data_0[15: 0];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
default: begin
adc_dsync <= 1'b0;
adc_dwr <= 1'b0;
adc_ddata <= 128'd0;
end
endcase
end
// spi
@ -463,31 +328,6 @@ module system_top (
.dio (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_ddata (adc_ddata),
.adc_dsync (adc_dsync),
.adc_dwr (adc_dwr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_ddata (dac_ddata),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_ddata_2 (dac_ddata_2),
.dac_ddata_3 (dac_ddata_3),
.dac_drd (dac_drd),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_enable_2 (dac_enable_2),
.dac_enable_3 (dac_enable_3),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.dac_valid_2 (dac_valid_2),
.dac_valid_3 (dac_valid_3),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),