axi_ad9467: Fix PN sequence checker
Make sure that the reference PN sequence is only incremented every two clock cycles to make sure that it matches the rate of the ADC PN sequence. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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59640f181b
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151781a2af
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@ -165,10 +165,12 @@ module axi_ad9467_pnmon (
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always @(posedge adc_clk) begin
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adc_valid_in <= ~adc_valid_in;
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adc_pn_data_in <= {adc_pn_data_in[15:0], ~adc_data[15], adc_data[14:0]};
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if (adc_pnseq_sel == 4'd0) begin
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adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
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end else begin
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adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
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if (adc_valid_in == 1'b1) begin
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if (adc_pnseq_sel == 4'd0) begin
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adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
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end else begin
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adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
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end
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end
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end
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