avl_dacfifo: Add avl_dacfifo_byteenable_coder
Define and integrate avl_dacfifo_byteenabke_coder module, which generates the byteenable signal for the avalon interface.main
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2016(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module avl_dacfifo_byteenable_coder #(
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parameter MEM_RATIO = 8,
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parameter LAST_BEATS_WIDTH = 3) (
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input avl_clk,
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input [LAST_BEATS_WIDTH-1:0] avl_last_beats,
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input avl_enable,
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output reg [ 63:0] avl_byteenable
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);
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always @(posedge avl_clk) begin
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if (avl_enable == 1'b1) begin
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case (avl_last_beats)
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0 : begin
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case (MEM_RATIO)
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2 : avl_byteenable <= {32'b0, {32{1'b1}}};
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4 : avl_byteenable <= {48'b0, {16{1'b1}}};
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8 : avl_byteenable <= {56'b0, {8{1'b1}}};
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16 : avl_byteenable <= {60'b0, {4{1'b1}}};
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32 : avl_byteenable <= {62'b0, {2{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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1 : begin
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case (MEM_RATIO)
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4 : avl_byteenable <= {32'b0, {32{1'b1}}};
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8 : avl_byteenable <= {48'b0, {16{1'b1}}};
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16 : avl_byteenable <= {56'b0, {8{1'b1}}};
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32 : avl_byteenable <= {60'b0, {4{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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2 : begin
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case (MEM_RATIO)
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4 : avl_byteenable <= {16'b0, {48{1'b1}}};
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8 : avl_byteenable <= {40'b0, {24{1'b1}}};
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16 : avl_byteenable <= {52'b0, {12{1'b1}}};
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32 : avl_byteenable <= {58'b0, {6{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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3 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {32'b0, {32{1'b1}}};
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16 : avl_byteenable <= {48'b0, {16{1'b1}}};
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32 : avl_byteenable <= {56'b0, {8{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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4 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {24'b0, {40{1'b1}}};
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16 : avl_byteenable <= {44'b0, {20{1'b1}}};
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32 : avl_byteenable <= {54'b0, {10{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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5 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {16'b0, {48{1'b1}}};
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16 : avl_byteenable <= {40'b0, {24{1'b1}}};
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32 : avl_byteenable <= {52'b0, {12{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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6 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {8'b0, {56{1'b1}}};
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16 : avl_byteenable <= {36'b0, {28{1'b1}}};
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32 : avl_byteenable <= {50'b0, {14{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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7 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {32'b0, {32{1'b1}}};
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32 : avl_byteenable <= {48'b0, {16{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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8 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {28'b0, {36{1'b1}}};
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32 : avl_byteenable <= {46'b0, {18{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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9 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {24'b0, {40{1'b1}}};
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32 : avl_byteenable <= {44'b0, {20{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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10 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {20'b0, {44{1'b1}}};
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32 : avl_byteenable <= {42'b0, {22{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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11 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {16'b0, {48{1'b1}}};
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32 : avl_byteenable <= {40'b0, {24{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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12 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {12'b0, {52{1'b1}}};
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32 : avl_byteenable <= {38'b0, {26{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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13 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {8'b0, {56{1'b1}}};
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32 : avl_byteenable <= {36'b0, {28{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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14 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {4'b0, {60{1'b1}}};
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32 : avl_byteenable <= {34'b0, {30{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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15 : begin
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case (MEM_RATIO)
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32 : avl_byteenable <= {32'b0, {32{1'b1}}};
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default: avl_byteenable <= {64{1'b1}};
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endcase
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end
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16 : begin
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avl_byteenable <= {30'b0, {34{1'b1}}};
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end
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17 : begin
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avl_byteenable <= {28'b0, {36{1'b1}}};
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end
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18 : begin
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avl_byteenable <= {26'b0, {38{1'b1}}};
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end
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19 : begin
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avl_byteenable <= {24'b0, {40{1'b1}}};
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end
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20 : begin
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avl_byteenable <= {22'b0, {42{1'b1}}};
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end
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21 : begin
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avl_byteenable <= {20'b0, {44{1'b1}}};
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end
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22 : begin
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avl_byteenable <= {18'b0, {46{1'b1}}};
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end
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23 : begin
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avl_byteenable <= {16'b0, {48{1'b1}}};
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end
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24 : begin
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avl_byteenable <= {14'b0, {50{1'b1}}};
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end
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25 : begin
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avl_byteenable <= {12'b0, {52{1'b1}}};
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end
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26 : begin
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avl_byteenable <= {10'b0, {54{1'b1}}};
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end
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27 : begin
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avl_byteenable <= {8'b0, {56{1'b1}}};
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end
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28 : begin
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avl_byteenable <= {6'b0, {58{1'b1}}};
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end
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29 : begin
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avl_byteenable <= {4'b0, {60{1'b1}}};
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end
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30 : begin
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avl_byteenable <= {2'b0, {62{1'b1}}};
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end
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end else begin
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avl_byteenable <= {64{1'b1}};
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end
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end
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endmodule
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@ -8,6 +8,7 @@ ad_ip_files avl_dacfifo [list\
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$ad_hdl_dir/library/altera/common/ad_mem_asym.v \
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$ad_hdl_dir/library/common/util_dacfifo_bypass.v \
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$ad_hdl_dir/library/common/util_delay.v \
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avl_dacfifo_byteenable_coder.v \
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avl_dacfifo_wr.v \
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avl_dacfifo_rd.v \
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avl_dacfifo.v \
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@ -44,7 +44,7 @@ module avl_dacfifo_wr #(
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input avl_reset,
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output reg [24:0] avl_address,
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output [ 5:0] avl_burstcount,
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output reg [63:0] avl_byteenable,
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output [63:0] avl_byteenable,
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input avl_ready,
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output reg avl_write,
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output reg [AVL_DATA_WIDTH-1:0] avl_data,
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@ -354,186 +354,18 @@ module avl_dacfifo_wr #(
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end else begin
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avl_last_beats_m1 <= dma_mem_last_beats;
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avl_last_beats_m2 <= avl_last_beats_m1;
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avl_last_beats <= (avl_last_beat_req == 1'b1) ? avl_last_beats_m2 : avl_last_beats;
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avl_last_beats <= (avl_last_beat_req_s == 1'b1) ? avl_last_beats_m2 : avl_last_beats;
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end
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end
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always @(posedge avl_clk) begin
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if (avl_last_transfer_req_s == 1'b1) begin
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case (avl_last_beats)
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0 : begin
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case (MEM_RATIO)
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2 : avl_byteenable <= {32'b0, {32{1'b1}}};
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4 : avl_byteenable <= {48'b0, {16{1'b1}}};
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8 : avl_byteenable <= {56'b0, {8{1'b1}}};
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16 : avl_byteenable <= {60'b0, {4{1'b1}}};
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32 : avl_byteenable <= {62'b0, {2{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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1 : begin
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case (MEM_RATIO)
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4 : avl_byteenable <= {32'b0, {32{1'b1}}};
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8 : avl_byteenable <= {48'b0, {16{1'b1}}};
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16 : avl_byteenable <= {56'b0, {8{1'b1}}};
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32 : avl_byteenable <= {60'b0, {4{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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2 : begin
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case (MEM_RATIO)
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4 : avl_byteenable <= {16'b0, {48{1'b1}}};
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8 : avl_byteenable <= {40'b0, {24{1'b1}}};
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16 : avl_byteenable <= {52'b0, {12{1'b1}}};
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32 : avl_byteenable <= {58'b0, {6{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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3 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {32'b0, {32{1'b1}}};
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16 : avl_byteenable <= {48'b0, {16{1'b1}}};
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32 : avl_byteenable <= {56'b0, {8{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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4 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {24'b0, {40{1'b1}}};
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16 : avl_byteenable <= {44'b0, {20{1'b1}}};
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32 : avl_byteenable <= {54'b0, {10{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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5 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {16'b0, {48{1'b1}}};
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16 : avl_byteenable <= {40'b0, {24{1'b1}}};
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32 : avl_byteenable <= {52'b0, {12{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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6 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {8'b0, {56{1'b1}}};
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16 : avl_byteenable <= {36'b0, {28{1'b1}}};
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32 : avl_byteenable <= {50'b0, {14{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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7 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {32'b0, {32{1'b1}}};
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32 : avl_byteenable <= {48'b0, {16{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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8 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {28'b0, {36{1'b1}}};
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32 : avl_byteenable <= {46'b0, {18{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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9 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {24'b0, {40{1'b1}}};
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32 : avl_byteenable <= {44'b0, {20{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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10 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {20'b0, {44{1'b1}}};
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32 : avl_byteenable <= {42'b0, {22{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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11 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {16'b0, {48{1'b1}}};
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32 : avl_byteenable <= {40'b0, {24{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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12 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {12'b0, {52{1'b1}}};
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32 : avl_byteenable <= {38'b0, {26{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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13 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {8'b0, {56{1'b1}}};
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32 : avl_byteenable <= {36'b0, {28{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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14 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {4'b0, {60{1'b1}}};
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32 : avl_byteenable <= {34'b0, {30{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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15 : begin
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case (MEM_RATIO)
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32 : avl_byteenable <= {32'b0, {32{1'b1}}};
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default: avl_byteenable <= {64{1'b1}};
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endcase
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end
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16 : begin
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avl_byteenable <= {30'b0, {34{1'b1}}};
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end
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17 : begin
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avl_byteenable <= {28'b0, {36{1'b1}}};
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end
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18 : begin
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avl_byteenable <= {26'b0, {38{1'b1}}};
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end
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19 : begin
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avl_byteenable <= {24'b0, {40{1'b1}}};
|
||||
end
|
||||
20 : begin
|
||||
avl_byteenable <= {22'b0, {42{1'b1}}};
|
||||
end
|
||||
21 : begin
|
||||
avl_byteenable <= {20'b0, {44{1'b1}}};
|
||||
end
|
||||
22 : begin
|
||||
avl_byteenable <= {18'b0, {46{1'b1}}};
|
||||
end
|
||||
23 : begin
|
||||
avl_byteenable <= {16'b0, {48{1'b1}}};
|
||||
end
|
||||
24 : begin
|
||||
avl_byteenable <= {14'b0, {50{1'b1}}};
|
||||
end
|
||||
25 : begin
|
||||
avl_byteenable <= {12'b0, {52{1'b1}}};
|
||||
end
|
||||
26 : begin
|
||||
avl_byteenable <= {10'b0, {54{1'b1}}};
|
||||
end
|
||||
27 : begin
|
||||
avl_byteenable <= {8'b0, {56{1'b1}}};
|
||||
end
|
||||
28 : begin
|
||||
avl_byteenable <= {6'b0, {58{1'b1}}};
|
||||
end
|
||||
29 : begin
|
||||
avl_byteenable <= {4'b0, {60{1'b1}}};
|
||||
end
|
||||
30 : begin
|
||||
avl_byteenable <= {2'b0, {62{1'b1}}};
|
||||
end
|
||||
default : avl_byteenable <= {64{1'b1}};
|
||||
endcase
|
||||
end else begin
|
||||
avl_byteenable <= {64{1'b1}};
|
||||
end
|
||||
end
|
||||
avl_dacfifo_byteenable_coder #(
|
||||
.MEM_RATIO(MEM_RATIO),
|
||||
.LAST_BEATS_WIDTH(MEM_WIDTH_DIFF)
|
||||
) i_byteenable_coder (
|
||||
.avl_clk (avl_clk),
|
||||
.avl_last_beats (avl_last_beats),
|
||||
.avl_enable (avl_last_transfer_req_s),
|
||||
.avl_byteenable (avl_byteenable));
|
||||
|
||||
assign avl_burstcount = 6'b1;
|
||||
|
||||
|
|
Loading…
Reference in New Issue