zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

xilinx:adxcvr: PRBS support 

The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
main
Laszlo Nagy 2020-12-18 14:43:28 +00:00 committed by Laszlo Nagy
parent b989ba36d1
commit 14307856ea
9 changed files with 633 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
library/interfaces/interfaces_ip.tcl
View File

@ -16,6 +16,11 @@ adi_if_ports input 1 pll_locked
adi_if_ports output 1 rst adi_if_ports output 1 rst
adi_if_ports output 1 user_ready adi_if_ports output 1 user_ready
adi_if_ports input 1 rst_done adi_if_ports input 1 rst_done
adi_if_ports output 4 prbssel
adi_if_ports output 1 prbsforceerr
adi_if_ports output 1 prbscntreset
adi_if_ports input 1 prbserr
adi_if_ports input 1 prbslocked
adi_if_ports output 1 lpm_dfe_n adi_if_ports output 1 lpm_dfe_n
adi_if_ports output 3 rate adi_if_ports output 3 rate
adi_if_ports output 2 sys_clk_sel adi_if_ports output 2 sys_clk_sel

296
library/xilinx/axi_adxcvr/axi_adxcvr.v
View File

@ -77,6 +77,11 @@ module axi_adxcvr #(
output up_ch_rst_0, output up_ch_rst_0,
output up_ch_user_ready_0, output up_ch_user_ready_0,
input up_ch_rst_done_0, input up_ch_rst_done_0,
output up_ch_prbsforceerr_0,
output [ 3:0] up_ch_prbssel_0,
output up_ch_prbscntreset_0,
input up_ch_prbserr_0,
input up_ch_prbslocked_0,
output up_ch_lpm_dfe_n_0, output up_ch_lpm_dfe_n_0,
output [ 2:0] up_ch_rate_0, output [ 2:0] up_ch_rate_0,
output [ 1:0] up_ch_sys_clk_sel_0, output [ 1:0] up_ch_sys_clk_sel_0,
@ -103,6 +108,11 @@ module axi_adxcvr #(
output up_ch_rst_1, output up_ch_rst_1,
output up_ch_user_ready_1, output up_ch_user_ready_1,
input up_ch_rst_done_1, input up_ch_rst_done_1,
output up_ch_prbsforceerr_1,
output [ 3:0] up_ch_prbssel_1,
output up_ch_prbscntreset_1,
input up_ch_prbserr_1,
input up_ch_prbslocked_1,
output up_ch_lpm_dfe_n_1, output up_ch_lpm_dfe_n_1,
output [ 2:0] up_ch_rate_1, output [ 2:0] up_ch_rate_1,
output [ 1:0] up_ch_sys_clk_sel_1, output [ 1:0] up_ch_sys_clk_sel_1,
@ -129,6 +139,11 @@ module axi_adxcvr #(
output up_ch_rst_2, output up_ch_rst_2,
output up_ch_user_ready_2, output up_ch_user_ready_2,
input up_ch_rst_done_2, input up_ch_rst_done_2,
output up_ch_prbsforceerr_2,
output [ 3:0] up_ch_prbssel_2,
output up_ch_prbscntreset_2,
input up_ch_prbserr_2,
input up_ch_prbslocked_2,
output up_ch_lpm_dfe_n_2, output up_ch_lpm_dfe_n_2,
output [ 2:0] up_ch_rate_2, output [ 2:0] up_ch_rate_2,
output [ 1:0] up_ch_sys_clk_sel_2, output [ 1:0] up_ch_sys_clk_sel_2,
@ -155,6 +170,11 @@ module axi_adxcvr #(
output up_ch_rst_3, output up_ch_rst_3,
output up_ch_user_ready_3, output up_ch_user_ready_3,
input up_ch_rst_done_3, input up_ch_rst_done_3,
output up_ch_prbsforceerr_3,
output [ 3:0] up_ch_prbssel_3,
output up_ch_prbscntreset_3,
input up_ch_prbserr_3,
input up_ch_prbslocked_3,
output up_ch_lpm_dfe_n_3, output up_ch_lpm_dfe_n_3,
output [ 2:0] up_ch_rate_3, output [ 2:0] up_ch_rate_3,
output [ 1:0] up_ch_sys_clk_sel_3, output [ 1:0] up_ch_sys_clk_sel_3,
@ -188,6 +208,11 @@ module axi_adxcvr #(
output up_ch_rst_4, output up_ch_rst_4,
output up_ch_user_ready_4, output up_ch_user_ready_4,
input up_ch_rst_done_4, input up_ch_rst_done_4,
output up_ch_prbsforceerr_4,
output [ 3:0] up_ch_prbssel_4,
output up_ch_prbscntreset_4,
input up_ch_prbserr_4,
input up_ch_prbslocked_4,
output up_ch_lpm_dfe_n_4, output up_ch_lpm_dfe_n_4,
output [ 2:0] up_ch_rate_4, output [ 2:0] up_ch_rate_4,
output [ 1:0] up_ch_sys_clk_sel_4, output [ 1:0] up_ch_sys_clk_sel_4,
@ -214,6 +239,11 @@ module axi_adxcvr #(
output up_ch_rst_5, output up_ch_rst_5,
output up_ch_user_ready_5, output up_ch_user_ready_5,
input up_ch_rst_done_5, input up_ch_rst_done_5,
output up_ch_prbsforceerr_5,
output [ 3:0] up_ch_prbssel_5,
output up_ch_prbscntreset_5,
input up_ch_prbserr_5,
input up_ch_prbslocked_5,
output up_ch_lpm_dfe_n_5, output up_ch_lpm_dfe_n_5,
output [ 2:0] up_ch_rate_5, output [ 2:0] up_ch_rate_5,
output [ 1:0] up_ch_sys_clk_sel_5, output [ 1:0] up_ch_sys_clk_sel_5,
@ -240,6 +270,11 @@ module axi_adxcvr #(
output up_ch_rst_6, output up_ch_rst_6,
output up_ch_user_ready_6, output up_ch_user_ready_6,
input up_ch_rst_done_6, input up_ch_rst_done_6,
output up_ch_prbsforceerr_6,
output [ 3:0] up_ch_prbssel_6,
output up_ch_prbscntreset_6,
input up_ch_prbserr_6,
input up_ch_prbslocked_6,
output up_ch_lpm_dfe_n_6, output up_ch_lpm_dfe_n_6,
output [ 2:0] up_ch_rate_6, output [ 2:0] up_ch_rate_6,
output [ 1:0] up_ch_sys_clk_sel_6, output [ 1:0] up_ch_sys_clk_sel_6,
@ -266,6 +301,11 @@ module axi_adxcvr #(
output up_ch_rst_7, output up_ch_rst_7,
output up_ch_user_ready_7, output up_ch_user_ready_7,
input up_ch_rst_done_7, input up_ch_rst_done_7,
output up_ch_prbsforceerr_7,
output [ 3:0] up_ch_prbssel_7,
output up_ch_prbscntreset_7,
input up_ch_prbserr_7,
input up_ch_prbslocked_7,
output up_ch_lpm_dfe_n_7, output up_ch_lpm_dfe_n_7,
output [ 2:0] up_ch_rate_7, output [ 2:0] up_ch_rate_7,
output [ 1:0] up_ch_sys_clk_sel_7, output [ 1:0] up_ch_sys_clk_sel_7,
@ -299,6 +339,11 @@ module axi_adxcvr #(
output up_ch_rst_8, output up_ch_rst_8,
output up_ch_user_ready_8, output up_ch_user_ready_8,
input up_ch_rst_done_8, input up_ch_rst_done_8,
output up_ch_prbsforceerr_8,
output [ 3:0] up_ch_prbssel_8,
output up_ch_prbscntreset_8,
input up_ch_prbserr_8,
input up_ch_prbslocked_8,
output up_ch_lpm_dfe_n_8, output up_ch_lpm_dfe_n_8,
output [ 2:0] up_ch_rate_8, output [ 2:0] up_ch_rate_8,
output [ 1:0] up_ch_sys_clk_sel_8, output [ 1:0] up_ch_sys_clk_sel_8,
@ -325,6 +370,11 @@ module axi_adxcvr #(
output up_ch_rst_9, output up_ch_rst_9,
output up_ch_user_ready_9, output up_ch_user_ready_9,
input up_ch_rst_done_9, input up_ch_rst_done_9,
output up_ch_prbsforceerr_9,
output [ 3:0] up_ch_prbssel_9,
output up_ch_prbscntreset_9,
input up_ch_prbserr_9,
input up_ch_prbslocked_9,
output up_ch_lpm_dfe_n_9, output up_ch_lpm_dfe_n_9,
output [ 2:0] up_ch_rate_9, output [ 2:0] up_ch_rate_9,
output [ 1:0] up_ch_sys_clk_sel_9, output [ 1:0] up_ch_sys_clk_sel_9,
@ -351,6 +401,11 @@ module axi_adxcvr #(
output up_ch_rst_10, output up_ch_rst_10,
output up_ch_user_ready_10, output up_ch_user_ready_10,
input up_ch_rst_done_10, input up_ch_rst_done_10,
output up_ch_prbsforceerr_10,
output [ 3:0] up_ch_prbssel_10,
output up_ch_prbscntreset_10,
input up_ch_prbserr_10,
input up_ch_prbslocked_10,
output up_ch_lpm_dfe_n_10, output up_ch_lpm_dfe_n_10,
output [ 2:0] up_ch_rate_10, output [ 2:0] up_ch_rate_10,
output [ 1:0] up_ch_sys_clk_sel_10, output [ 1:0] up_ch_sys_clk_sel_10,
@ -377,6 +432,11 @@ module axi_adxcvr #(
output up_ch_rst_11, output up_ch_rst_11,
output up_ch_user_ready_11, output up_ch_user_ready_11,
input up_ch_rst_done_11, input up_ch_rst_done_11,
output up_ch_prbsforceerr_11,
output [ 3:0] up_ch_prbssel_11,
output up_ch_prbscntreset_11,
input up_ch_prbserr_11,
input up_ch_prbslocked_11,
output up_ch_lpm_dfe_n_11, output up_ch_lpm_dfe_n_11,
output [ 2:0] up_ch_rate_11, output [ 2:0] up_ch_rate_11,
output [ 1:0] up_ch_sys_clk_sel_11, output [ 1:0] up_ch_sys_clk_sel_11,
@ -410,6 +470,11 @@ module axi_adxcvr #(
output up_ch_rst_12, output up_ch_rst_12,
output up_ch_user_ready_12, output up_ch_user_ready_12,
input up_ch_rst_done_12, input up_ch_rst_done_12,
output up_ch_prbsforceerr_12,
output [ 3:0] up_ch_prbssel_12,
output up_ch_prbscntreset_12,
input up_ch_prbserr_12,
input up_ch_prbslocked_12,
output up_ch_lpm_dfe_n_12, output up_ch_lpm_dfe_n_12,
output [ 2:0] up_ch_rate_12, output [ 2:0] up_ch_rate_12,
output [ 1:0] up_ch_sys_clk_sel_12, output [ 1:0] up_ch_sys_clk_sel_12,
@ -436,6 +501,11 @@ module axi_adxcvr #(
output up_ch_rst_13, output up_ch_rst_13,
output up_ch_user_ready_13, output up_ch_user_ready_13,
input up_ch_rst_done_13, input up_ch_rst_done_13,
output up_ch_prbsforceerr_13,
output [ 3:0] up_ch_prbssel_13,
output up_ch_prbscntreset_13,
input up_ch_prbserr_13,
input up_ch_prbslocked_13,
output up_ch_lpm_dfe_n_13, output up_ch_lpm_dfe_n_13,
output [ 2:0] up_ch_rate_13, output [ 2:0] up_ch_rate_13,
output [ 1:0] up_ch_sys_clk_sel_13, output [ 1:0] up_ch_sys_clk_sel_13,
@ -462,6 +532,11 @@ module axi_adxcvr #(
output up_ch_rst_14, output up_ch_rst_14,
output up_ch_user_ready_14, output up_ch_user_ready_14,
input up_ch_rst_done_14, input up_ch_rst_done_14,
output up_ch_prbsforceerr_14,
output [ 3:0] up_ch_prbssel_14,
output up_ch_prbscntreset_14,
input up_ch_prbserr_14,
input up_ch_prbslocked_14,
output up_ch_lpm_dfe_n_14, output up_ch_lpm_dfe_n_14,
output [ 2:0] up_ch_rate_14, output [ 2:0] up_ch_rate_14,
output [ 1:0] up_ch_sys_clk_sel_14, output [ 1:0] up_ch_sys_clk_sel_14,
@ -488,6 +563,11 @@ module axi_adxcvr #(
output up_ch_rst_15, output up_ch_rst_15,
output up_ch_user_ready_15, output up_ch_user_ready_15,
input up_ch_rst_done_15, input up_ch_rst_done_15,
output up_ch_prbsforceerr_15,
output [ 3:0] up_ch_prbssel_15,
output up_ch_prbscntreset_15,
input up_ch_prbserr_15,
input up_ch_prbslocked_15,
output up_ch_lpm_dfe_n_15, output up_ch_lpm_dfe_n_15,
output [ 2:0] up_ch_rate_15, output [ 2:0] up_ch_rate_15,
output [ 1:0] up_ch_sys_clk_sel_15, output [ 1:0] up_ch_sys_clk_sel_15,
@ -608,38 +688,73 @@ module axi_adxcvr #(
wire [ 4:0] up_ch_tx_diffctrl; wire [ 4:0] up_ch_tx_diffctrl;
wire [ 4:0] up_ch_tx_postcursor; wire [ 4:0] up_ch_tx_postcursor;
wire [ 4:0] up_ch_tx_precursor; wire [ 4:0] up_ch_tx_precursor;
wire up_ch_prbsforceerr;
wire [ 3:0] up_ch_prbssel;
wire up_ch_prbscntreset;
wire up_ch_pll_locked_0_s; wire up_ch_pll_locked_0_s;
wire up_ch_rst_done_0_s; wire up_ch_rst_done_0_s;
wire up_ch_prbserr_0_s;
wire up_ch_prbslocked_0_s;
wire up_ch_pll_locked_1_s; wire up_ch_pll_locked_1_s;
wire up_ch_rst_done_1_s; wire up_ch_rst_done_1_s;
wire up_ch_prbserr_1_s;
wire up_ch_prbslocked_1_s;
wire up_ch_pll_locked_2_s; wire up_ch_pll_locked_2_s;
wire up_ch_rst_done_2_s; wire up_ch_rst_done_2_s;
wire up_ch_prbserr_2_s;
wire up_ch_prbslocked_2_s;
wire up_ch_pll_locked_3_s; wire up_ch_pll_locked_3_s;
wire up_ch_rst_done_3_s; wire up_ch_rst_done_3_s;
wire up_ch_prbserr_3_s;
wire up_ch_prbslocked_3_s;
wire up_ch_pll_locked_4_s; wire up_ch_pll_locked_4_s;
wire up_ch_rst_done_4_s; wire up_ch_rst_done_4_s;
wire up_ch_prbserr_4_s;
wire up_ch_prbslocked_4_s;
wire up_ch_pll_locked_5_s; wire up_ch_pll_locked_5_s;
wire up_ch_rst_done_5_s; wire up_ch_rst_done_5_s;
wire up_ch_prbserr_5_s;
wire up_ch_prbslocked_5_s;
wire up_ch_pll_locked_6_s; wire up_ch_pll_locked_6_s;
wire up_ch_rst_done_6_s; wire up_ch_rst_done_6_s;
wire up_ch_prbserr_6_s;
wire up_ch_prbslocked_6_s;
wire up_ch_pll_locked_7_s; wire up_ch_pll_locked_7_s;
wire up_ch_rst_done_7_s; wire up_ch_rst_done_7_s;
wire up_ch_prbserr_7_s;
wire up_ch_prbslocked_7_s;
wire up_ch_pll_locked_8_s; wire up_ch_pll_locked_8_s;
wire up_ch_rst_done_8_s; wire up_ch_rst_done_8_s;
wire up_ch_prbserr_8_s;
wire up_ch_prbslocked_8_s;
wire up_ch_pll_locked_9_s; wire up_ch_pll_locked_9_s;
wire up_ch_rst_done_9_s; wire up_ch_rst_done_9_s;
wire up_ch_prbserr_9_s;
wire up_ch_prbslocked_9_s;
wire up_ch_pll_locked_10_s; wire up_ch_pll_locked_10_s;
wire up_ch_rst_done_10_s; wire up_ch_rst_done_10_s;
wire up_ch_prbserr_10_s;
wire up_ch_prbslocked_10_s;
wire up_ch_pll_locked_11_s; wire up_ch_pll_locked_11_s;
wire up_ch_rst_done_11_s; wire up_ch_rst_done_11_s;
wire up_ch_prbserr_11_s;
wire up_ch_prbslocked_11_s;
wire up_ch_pll_locked_12_s; wire up_ch_pll_locked_12_s;
wire up_ch_rst_done_12_s; wire up_ch_rst_done_12_s;
wire up_ch_prbserr_12_s;
wire up_ch_prbslocked_12_s;
wire up_ch_pll_locked_13_s; wire up_ch_pll_locked_13_s;
wire up_ch_rst_done_13_s; wire up_ch_rst_done_13_s;
wire up_ch_prbserr_13_s;
wire up_ch_prbslocked_13_s;
wire up_ch_pll_locked_14_s; wire up_ch_pll_locked_14_s;
wire up_ch_rst_done_14_s; wire up_ch_rst_done_14_s;
wire up_ch_prbserr_14_s;
wire up_ch_prbslocked_14_s;
wire up_ch_pll_locked_15_s; wire up_ch_pll_locked_15_s;
wire up_ch_rst_done_15_s; wire up_ch_rst_done_15_s;
wire up_ch_prbserr_15_s;
wire up_ch_prbslocked_15_s;
wire [ 7:0] up_ch_sel; wire [ 7:0] up_ch_sel;
wire up_ch_enb; wire up_ch_enb;
wire [11:0] up_ch_addr; wire [11:0] up_ch_addr;
@ -772,6 +887,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_0 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_0 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_0 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_0 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_0 = up_ch_tx_precursor; assign up_ch_tx_precursor_0 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_0 = up_ch_prbsforceerr;
assign up_ch_prbssel_0 = up_ch_prbssel;
assign up_ch_prbscntreset_0 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (0), .XCVR_ID (0),
@ -781,10 +899,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (1'd1), .up_pll_locked_in (1'd1),
.up_rst_done_in (1'd1), .up_rst_done_in (1'd1),
.up_prbserr_in (1'd0),
.up_prbslocked_in (1'd1),
.up_pll_locked (up_ch_pll_locked_0), .up_pll_locked (up_ch_pll_locked_0),
.up_rst_done (up_ch_rst_done_0), .up_rst_done (up_ch_rst_done_0),
.up_prbserr (up_ch_prbserr_0),
.up_prbslocked (up_ch_prbslocked_0),
.up_pll_locked_out (up_ch_pll_locked_0_s), .up_pll_locked_out (up_ch_pll_locked_0_s),
.up_rst_done_out (up_ch_rst_done_0_s)); .up_rst_done_out (up_ch_rst_done_0_s),
.up_prbserr_out (up_ch_prbserr_0_s),
.up_prbslocked_out (up_ch_prbslocked_0_s));
assign up_ch_addr_0 = up_ch_addr; assign up_ch_addr_0 = up_ch_addr;
assign up_ch_wr_0 = up_ch_wr; assign up_ch_wr_0 = up_ch_wr;
@ -835,6 +959,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_1 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_1 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_1 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_1 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_1 = up_ch_tx_precursor; assign up_ch_tx_precursor_1 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_1 = up_ch_prbsforceerr;
assign up_ch_prbssel_1 = up_ch_prbssel;
assign up_ch_prbscntreset_1 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (1), .XCVR_ID (1),
@ -844,10 +971,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_0_s), .up_pll_locked_in (up_ch_pll_locked_0_s),
.up_rst_done_in (up_ch_rst_done_0_s), .up_rst_done_in (up_ch_rst_done_0_s),
.up_prbserr_in (up_ch_prbserr_0_s),
.up_prbslocked_in (up_ch_prbslocked_0_s),
.up_pll_locked (up_ch_pll_locked_1), .up_pll_locked (up_ch_pll_locked_1),
.up_rst_done (up_ch_rst_done_1), .up_rst_done (up_ch_rst_done_1),
.up_prbserr (up_ch_prbserr_1),
.up_prbslocked (up_ch_prbslocked_1),
.up_pll_locked_out (up_ch_pll_locked_1_s), .up_pll_locked_out (up_ch_pll_locked_1_s),
.up_rst_done_out (up_ch_rst_done_1_s)); .up_rst_done_out (up_ch_rst_done_1_s),
.up_prbserr_out (up_ch_prbserr_1_s),
.up_prbslocked_out (up_ch_prbslocked_1_s));
assign up_ch_addr_1 = up_ch_addr; assign up_ch_addr_1 = up_ch_addr;
assign up_ch_wr_1 = up_ch_wr; assign up_ch_wr_1 = up_ch_wr;
@ -898,6 +1031,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_2 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_2 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_2 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_2 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_2 = up_ch_tx_precursor; assign up_ch_tx_precursor_2 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_2 = up_ch_prbsforceerr;
assign up_ch_prbssel_2 = up_ch_prbssel;
assign up_ch_prbscntreset_2 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (2), .XCVR_ID (2),
@ -907,10 +1043,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_1_s), .up_pll_locked_in (up_ch_pll_locked_1_s),
.up_rst_done_in (up_ch_rst_done_1_s), .up_rst_done_in (up_ch_rst_done_1_s),
.up_prbserr_in (up_ch_prbserr_1_s),
.up_prbslocked_in (up_ch_prbslocked_1_s),
.up_pll_locked (up_ch_pll_locked_2), .up_pll_locked (up_ch_pll_locked_2),
.up_rst_done (up_ch_rst_done_2), .up_rst_done (up_ch_rst_done_2),
.up_prbserr (up_ch_prbserr_2),
.up_prbslocked (up_ch_prbslocked_2),
.up_pll_locked_out (up_ch_pll_locked_2_s), .up_pll_locked_out (up_ch_pll_locked_2_s),
.up_rst_done_out (up_ch_rst_done_2_s)); .up_rst_done_out (up_ch_rst_done_2_s),
.up_prbserr_out (up_ch_prbserr_2_s),
.up_prbslocked_out (up_ch_prbslocked_2_s));
assign up_ch_addr_2 = up_ch_addr; assign up_ch_addr_2 = up_ch_addr;
assign up_ch_wr_2 = up_ch_wr; assign up_ch_wr_2 = up_ch_wr;
@ -961,6 +1103,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_3 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_3 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_3 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_3 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_3 = up_ch_tx_precursor; assign up_ch_tx_precursor_3 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_3 = up_ch_prbsforceerr;
assign up_ch_prbssel_3 = up_ch_prbssel;
assign up_ch_prbscntreset_3 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (3), .XCVR_ID (3),
@ -970,10 +1115,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_2_s), .up_pll_locked_in (up_ch_pll_locked_2_s),
.up_rst_done_in (up_ch_rst_done_2_s), .up_rst_done_in (up_ch_rst_done_2_s),
.up_prbserr_in (up_ch_prbserr_2_s),
.up_prbslocked_in (up_ch_prbslocked_2_s),
.up_pll_locked (up_ch_pll_locked_3), .up_pll_locked (up_ch_pll_locked_3),
.up_rst_done (up_ch_rst_done_3), .up_rst_done (up_ch_rst_done_3),
.up_prbserr (up_ch_prbserr_3),
.up_prbslocked (up_ch_prbslocked_3),
.up_pll_locked_out (up_ch_pll_locked_3_s), .up_pll_locked_out (up_ch_pll_locked_3_s),
.up_rst_done_out (up_ch_rst_done_3_s)); .up_rst_done_out (up_ch_rst_done_3_s),
.up_prbserr_out (up_ch_prbserr_3_s),
.up_prbslocked_out (up_ch_prbslocked_3_s));
assign up_ch_addr_3 = up_ch_addr; assign up_ch_addr_3 = up_ch_addr;
assign up_ch_wr_3 = up_ch_wr; assign up_ch_wr_3 = up_ch_wr;
@ -1044,6 +1195,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_4 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_4 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_4 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_4 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_4 = up_ch_tx_precursor; assign up_ch_tx_precursor_4 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_4 = up_ch_prbsforceerr;
assign up_ch_prbssel_4 = up_ch_prbssel;
assign up_ch_prbscntreset_4 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (4), .XCVR_ID (4),
@ -1053,10 +1207,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_3_s), .up_pll_locked_in (up_ch_pll_locked_3_s),
.up_rst_done_in (up_ch_rst_done_3_s), .up_rst_done_in (up_ch_rst_done_3_s),
.up_prbserr_in (up_ch_prbserr_3_s),
.up_prbslocked_in (up_ch_prbslocked_3_s),
.up_pll_locked (up_ch_pll_locked_4), .up_pll_locked (up_ch_pll_locked_4),
.up_rst_done (up_ch_rst_done_4), .up_rst_done (up_ch_rst_done_4),
.up_prbserr (up_ch_prbserr_4),
.up_prbslocked (up_ch_prbslocked_4),
.up_pll_locked_out (up_ch_pll_locked_4_s), .up_pll_locked_out (up_ch_pll_locked_4_s),
.up_rst_done_out (up_ch_rst_done_4_s)); .up_rst_done_out (up_ch_rst_done_4_s),
.up_prbserr_out (up_ch_prbserr_4_s),
.up_prbslocked_out (up_ch_prbslocked_4_s));
assign up_ch_addr_4 = up_ch_addr; assign up_ch_addr_4 = up_ch_addr;
assign up_ch_wr_4 = up_ch_wr; assign up_ch_wr_4 = up_ch_wr;
@ -1107,6 +1267,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_5 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_5 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_5 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_5 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_5 = up_ch_tx_precursor; assign up_ch_tx_precursor_5 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_5 = up_ch_prbsforceerr;
assign up_ch_prbssel_5 = up_ch_prbssel;
assign up_ch_prbscntreset_5 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (5), .XCVR_ID (5),
@ -1116,10 +1279,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_4_s), .up_pll_locked_in (up_ch_pll_locked_4_s),
.up_rst_done_in (up_ch_rst_done_4_s), .up_rst_done_in (up_ch_rst_done_4_s),
.up_prbserr_in (up_ch_prbserr_4_s),
.up_prbslocked_in (up_ch_prbslocked_4_s),
.up_pll_locked (up_ch_pll_locked_5), .up_pll_locked (up_ch_pll_locked_5),
.up_rst_done (up_ch_rst_done_5), .up_rst_done (up_ch_rst_done_5),
.up_prbserr (up_ch_prbserr_5),
.up_prbslocked (up_ch_prbslocked_5),
.up_pll_locked_out (up_ch_pll_locked_5_s), .up_pll_locked_out (up_ch_pll_locked_5_s),
.up_rst_done_out (up_ch_rst_done_5_s)); .up_rst_done_out (up_ch_rst_done_5_s),
.up_prbserr_out (up_ch_prbserr_5_s),
.up_prbslocked_out (up_ch_prbslocked_5_s));
assign up_ch_addr_5 = up_ch_addr; assign up_ch_addr_5 = up_ch_addr;
assign up_ch_wr_5 = up_ch_wr; assign up_ch_wr_5 = up_ch_wr;
@ -1170,6 +1339,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_6 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_6 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_6 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_6 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_6 = up_ch_tx_precursor; assign up_ch_tx_precursor_6 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_6 = up_ch_prbsforceerr;
assign up_ch_prbssel_6 = up_ch_prbssel;
assign up_ch_prbscntreset_6 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (6), .XCVR_ID (6),
@ -1179,10 +1351,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_5_s), .up_pll_locked_in (up_ch_pll_locked_5_s),
.up_rst_done_in (up_ch_rst_done_5_s), .up_rst_done_in (up_ch_rst_done_5_s),
.up_prbserr_in (up_ch_prbserr_5_s),
.up_prbslocked_in (up_ch_prbslocked_5_s),
.up_pll_locked (up_ch_pll_locked_6), .up_pll_locked (up_ch_pll_locked_6),
.up_rst_done (up_ch_rst_done_6), .up_rst_done (up_ch_rst_done_6),
.up_prbserr (up_ch_prbserr_6),
.up_prbslocked (up_ch_prbslocked_6),
.up_pll_locked_out (up_ch_pll_locked_6_s), .up_pll_locked_out (up_ch_pll_locked_6_s),
.up_rst_done_out (up_ch_rst_done_6_s)); .up_rst_done_out (up_ch_rst_done_6_s),
.up_prbserr_out (up_ch_prbserr_6_s),
.up_prbslocked_out (up_ch_prbslocked_6_s));
assign up_ch_addr_6 = up_ch_addr; assign up_ch_addr_6 = up_ch_addr;
assign up_ch_wr_6 = up_ch_wr; assign up_ch_wr_6 = up_ch_wr;
@ -1233,6 +1411,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_7 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_7 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_7 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_7 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_7 = up_ch_tx_precursor; assign up_ch_tx_precursor_7 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_7 = up_ch_prbsforceerr;
assign up_ch_prbssel_7 = up_ch_prbssel;
assign up_ch_prbscntreset_7 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (7), .XCVR_ID (7),
@ -1242,10 +1423,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_6_s), .up_pll_locked_in (up_ch_pll_locked_6_s),
.up_rst_done_in (up_ch_rst_done_6_s), .up_rst_done_in (up_ch_rst_done_6_s),
.up_prbserr_in (up_ch_prbserr_6_s),
.up_prbslocked_in (up_ch_prbslocked_6_s),
.up_pll_locked (up_ch_pll_locked_7), .up_pll_locked (up_ch_pll_locked_7),
.up_rst_done (up_ch_rst_done_7), .up_rst_done (up_ch_rst_done_7),
.up_prbserr (up_ch_prbserr_7),
.up_prbslocked (up_ch_prbslocked_7),
.up_pll_locked_out (up_ch_pll_locked_7_s), .up_pll_locked_out (up_ch_pll_locked_7_s),
.up_rst_done_out (up_ch_rst_done_7_s)); .up_rst_done_out (up_ch_rst_done_7_s),
.up_prbserr_out (up_ch_prbserr_7_s),
.up_prbslocked_out (up_ch_prbslocked_7_s));
assign up_ch_addr_7 = up_ch_addr; assign up_ch_addr_7 = up_ch_addr;
assign up_ch_wr_7 = up_ch_wr; assign up_ch_wr_7 = up_ch_wr;
@ -1316,6 +1503,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_8 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_8 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_8 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_8 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_8 = up_ch_tx_precursor; assign up_ch_tx_precursor_8 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_8 = up_ch_prbsforceerr;
assign up_ch_prbssel_8 = up_ch_prbssel;
assign up_ch_prbscntreset_8 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (8), .XCVR_ID (8),
@ -1325,10 +1515,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_7_s), .up_pll_locked_in (up_ch_pll_locked_7_s),
.up_rst_done_in (up_ch_rst_done_7_s), .up_rst_done_in (up_ch_rst_done_7_s),
.up_prbserr_in (up_ch_prbserr_7_s),
.up_prbslocked_in (up_ch_prbslocked_7_s),
.up_pll_locked (up_ch_pll_locked_8), .up_pll_locked (up_ch_pll_locked_8),
.up_rst_done (up_ch_rst_done_8), .up_rst_done (up_ch_rst_done_8),
.up_prbserr (up_ch_prbserr_8),
.up_prbslocked (up_ch_prbslocked_8),
.up_pll_locked_out (up_ch_pll_locked_8_s), .up_pll_locked_out (up_ch_pll_locked_8_s),
.up_rst_done_out (up_ch_rst_done_8_s)); .up_rst_done_out (up_ch_rst_done_8_s),
.up_prbserr_out (up_ch_prbserr_8_s),
.up_prbslocked_out (up_ch_prbslocked_8_s));
assign up_ch_addr_8 = up_ch_addr; assign up_ch_addr_8 = up_ch_addr;
assign up_ch_wr_8 = up_ch_wr; assign up_ch_wr_8 = up_ch_wr;
@ -1379,6 +1575,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_9 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_9 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_9 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_9 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_9 = up_ch_tx_precursor; assign up_ch_tx_precursor_9 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_9 = up_ch_prbsforceerr;
assign up_ch_prbssel_9 = up_ch_prbssel;
assign up_ch_prbscntreset_9 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (9), .XCVR_ID (9),
@ -1388,10 +1587,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_8_s), .up_pll_locked_in (up_ch_pll_locked_8_s),
.up_rst_done_in (up_ch_rst_done_8_s), .up_rst_done_in (up_ch_rst_done_8_s),
.up_prbserr_in (up_ch_prbserr_8_s),
.up_prbslocked_in (up_ch_prbslocked_8_s),
.up_pll_locked (up_ch_pll_locked_9), .up_pll_locked (up_ch_pll_locked_9),
.up_rst_done (up_ch_rst_done_9), .up_rst_done (up_ch_rst_done_9),
.up_prbserr (up_ch_prbserr_9),
.up_prbslocked (up_ch_prbslocked_9),
.up_pll_locked_out (up_ch_pll_locked_9_s), .up_pll_locked_out (up_ch_pll_locked_9_s),
.up_rst_done_out (up_ch_rst_done_9_s)); .up_rst_done_out (up_ch_rst_done_9_s),
.up_prbserr_out (up_ch_prbserr_9_s),
.up_prbslocked_out (up_ch_prbslocked_9_s));
assign up_ch_addr_9 = up_ch_addr; assign up_ch_addr_9 = up_ch_addr;
assign up_ch_wr_9 = up_ch_wr; assign up_ch_wr_9 = up_ch_wr;
@ -1442,6 +1647,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_10 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_10 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_10 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_10 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_10 = up_ch_tx_precursor; assign up_ch_tx_precursor_10 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_10 = up_ch_prbsforceerr;
assign up_ch_prbssel_10 = up_ch_prbssel;
assign up_ch_prbscntreset_10 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (10), .XCVR_ID (10),
@ -1451,10 +1659,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_9_s), .up_pll_locked_in (up_ch_pll_locked_9_s),
.up_rst_done_in (up_ch_rst_done_9_s), .up_rst_done_in (up_ch_rst_done_9_s),
.up_prbserr_in (up_ch_prbserr_9_s),
.up_prbslocked_in (up_ch_prbslocked_9_s),
.up_pll_locked (up_ch_pll_locked_10), .up_pll_locked (up_ch_pll_locked_10),
.up_rst_done (up_ch_rst_done_10), .up_rst_done (up_ch_rst_done_10),
.up_prbserr (up_ch_prbserr_10),
.up_prbslocked (up_ch_prbslocked_10),
.up_pll_locked_out (up_ch_pll_locked_10_s), .up_pll_locked_out (up_ch_pll_locked_10_s),
.up_rst_done_out (up_ch_rst_done_10_s)); .up_rst_done_out (up_ch_rst_done_10_s),
.up_prbserr_out (up_ch_prbserr_10_s),
.up_prbslocked_out (up_ch_prbslocked_10_s));
assign up_ch_addr_10 = up_ch_addr; assign up_ch_addr_10 = up_ch_addr;
assign up_ch_wr_10 = up_ch_wr; assign up_ch_wr_10 = up_ch_wr;
@ -1505,6 +1719,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_11 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_11 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_11 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_11 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_11 = up_ch_tx_precursor; assign up_ch_tx_precursor_11 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_11 = up_ch_prbsforceerr;
assign up_ch_prbssel_11 = up_ch_prbssel;
assign up_ch_prbscntreset_11 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (11), .XCVR_ID (11),
@ -1514,10 +1731,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_10_s), .up_pll_locked_in (up_ch_pll_locked_10_s),
.up_rst_done_in (up_ch_rst_done_10_s), .up_rst_done_in (up_ch_rst_done_10_s),
.up_prbserr_in (up_ch_prbserr_10_s),
.up_prbslocked_in (up_ch_prbslocked_10_s),
.up_pll_locked (up_ch_pll_locked_11), .up_pll_locked (up_ch_pll_locked_11),
.up_rst_done (up_ch_rst_done_11), .up_rst_done (up_ch_rst_done_11),
.up_prbserr (up_ch_prbserr_11),
.up_prbslocked (up_ch_prbslocked_11),
.up_pll_locked_out (up_ch_pll_locked_11_s), .up_pll_locked_out (up_ch_pll_locked_11_s),
.up_rst_done_out (up_ch_rst_done_11_s)); .up_rst_done_out (up_ch_rst_done_11_s),
.up_prbserr_out (up_ch_prbserr_11_s),
.up_prbslocked_out (up_ch_prbslocked_11_s));
assign up_ch_addr_11 = up_ch_addr; assign up_ch_addr_11 = up_ch_addr;
assign up_ch_wr_11 = up_ch_wr; assign up_ch_wr_11 = up_ch_wr;
@ -1588,6 +1811,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_12 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_12 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_12 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_12 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_12 = up_ch_tx_precursor; assign up_ch_tx_precursor_12 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_12 = up_ch_prbsforceerr;
assign up_ch_prbssel_12 = up_ch_prbssel;
assign up_ch_prbscntreset_12 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (12), .XCVR_ID (12),
@ -1597,10 +1823,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_11_s), .up_pll_locked_in (up_ch_pll_locked_11_s),
.up_rst_done_in (up_ch_rst_done_11_s), .up_rst_done_in (up_ch_rst_done_11_s),
.up_prbserr_in (up_ch_prbserr_11_s),
.up_prbslocked_in (up_ch_prbslocked_11_s),
.up_pll_locked (up_ch_pll_locked_12), .up_pll_locked (up_ch_pll_locked_12),
.up_rst_done (up_ch_rst_done_12), .up_rst_done (up_ch_rst_done_12),
.up_prbserr (up_ch_prbserr_12),
.up_prbslocked (up_ch_prbslocked_12),
.up_pll_locked_out (up_ch_pll_locked_12_s), .up_pll_locked_out (up_ch_pll_locked_12_s),
.up_rst_done_out (up_ch_rst_done_12_s)); .up_rst_done_out (up_ch_rst_done_12_s),
.up_prbserr_out (up_ch_prbserr_12_s),
.up_prbslocked_out (up_ch_prbslocked_12_s));
assign up_ch_addr_12 = up_ch_addr; assign up_ch_addr_12 = up_ch_addr;
assign up_ch_wr_12 = up_ch_wr; assign up_ch_wr_12 = up_ch_wr;
@ -1651,6 +1883,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_13 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_13 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_13 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_13 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_13 = up_ch_tx_precursor; assign up_ch_tx_precursor_13 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_13 = up_ch_prbsforceerr;
assign up_ch_prbssel_13 = up_ch_prbssel;
assign up_ch_prbscntreset_13 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (13), .XCVR_ID (13),
@ -1660,10 +1895,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_12_s), .up_pll_locked_in (up_ch_pll_locked_12_s),
.up_rst_done_in (up_ch_rst_done_12_s), .up_rst_done_in (up_ch_rst_done_12_s),
.up_prbserr_in (up_ch_prbserr_12_s),
.up_prbslocked_in (up_ch_prbslocked_12_s),
.up_pll_locked (up_ch_pll_locked_13), .up_pll_locked (up_ch_pll_locked_13),
.up_rst_done (up_ch_rst_done_13), .up_rst_done (up_ch_rst_done_13),
.up_prbserr (up_ch_prbserr_13),
.up_prbslocked (up_ch_prbslocked_13),
.up_pll_locked_out (up_ch_pll_locked_13_s), .up_pll_locked_out (up_ch_pll_locked_13_s),
.up_rst_done_out (up_ch_rst_done_13_s)); .up_rst_done_out (up_ch_rst_done_13_s),
.up_prbserr_out (up_ch_prbserr_13_s),
.up_prbslocked_out (up_ch_prbslocked_13_s));
assign up_ch_addr_13 = up_ch_addr; assign up_ch_addr_13 = up_ch_addr;
assign up_ch_wr_13 = up_ch_wr; assign up_ch_wr_13 = up_ch_wr;
@ -1714,6 +1955,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_14 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_14 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_14 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_14 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_14 = up_ch_tx_precursor; assign up_ch_tx_precursor_14 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_14 = up_ch_prbsforceerr;
assign up_ch_prbssel_14 = up_ch_prbssel;
assign up_ch_prbscntreset_14 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (14), .XCVR_ID (14),
@ -1723,10 +1967,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_13_s), .up_pll_locked_in (up_ch_pll_locked_13_s),
.up_rst_done_in (up_ch_rst_done_13_s), .up_rst_done_in (up_ch_rst_done_13_s),
.up_prbserr_in (up_ch_prbserr_13_s),
.up_prbslocked_in (up_ch_prbslocked_13_s),
.up_pll_locked (up_ch_pll_locked_14), .up_pll_locked (up_ch_pll_locked_14),
.up_rst_done (up_ch_rst_done_14), .up_rst_done (up_ch_rst_done_14),
.up_prbserr (up_ch_prbserr_14),
.up_prbslocked (up_ch_prbslocked_14),
.up_pll_locked_out (up_ch_pll_locked_14_s), .up_pll_locked_out (up_ch_pll_locked_14_s),
.up_rst_done_out (up_ch_rst_done_14_s)); .up_rst_done_out (up_ch_rst_done_14_s),
.up_prbserr_out (up_ch_prbserr_14_s),
.up_prbslocked_out (up_ch_prbslocked_14_s));
assign up_ch_addr_14 = up_ch_addr; assign up_ch_addr_14 = up_ch_addr;
assign up_ch_wr_14 = up_ch_wr; assign up_ch_wr_14 = up_ch_wr;
@ -1777,6 +2027,9 @@ module axi_adxcvr #(
assign up_ch_tx_diffctrl_15 = up_ch_tx_diffctrl; assign up_ch_tx_diffctrl_15 = up_ch_tx_diffctrl;
assign up_ch_tx_postcursor_15 = up_ch_tx_postcursor; assign up_ch_tx_postcursor_15 = up_ch_tx_postcursor;
assign up_ch_tx_precursor_15 = up_ch_tx_precursor; assign up_ch_tx_precursor_15 = up_ch_tx_precursor;
assign up_ch_prbsforceerr_15 = up_ch_prbsforceerr;
assign up_ch_prbssel_15 = up_ch_prbssel;
assign up_ch_prbscntreset_15 = up_ch_prbscntreset;
axi_adxcvr_mstatus #( axi_adxcvr_mstatus #(
.XCVR_ID (15), .XCVR_ID (15),
@ -1786,10 +2039,16 @@ module axi_adxcvr #(
.up_clk (up_clk), .up_clk (up_clk),
.up_pll_locked_in (up_ch_pll_locked_14_s), .up_pll_locked_in (up_ch_pll_locked_14_s),
.up_rst_done_in (up_ch_rst_done_14_s), .up_rst_done_in (up_ch_rst_done_14_s),
.up_prbserr_in (up_ch_prbserr_14_s),
.up_prbslocked_in (up_ch_prbslocked_14_s),
.up_pll_locked (up_ch_pll_locked_15), .up_pll_locked (up_ch_pll_locked_15),
.up_rst_done (up_ch_rst_done_15), .up_rst_done (up_ch_rst_done_15),
.up_prbserr (up_ch_prbserr_15),
.up_prbslocked (up_ch_prbslocked_15),
.up_pll_locked_out (up_ch_pll_locked_15_s), .up_pll_locked_out (up_ch_pll_locked_15_s),
.up_rst_done_out (up_ch_rst_done_15_s)); .up_rst_done_out (up_ch_rst_done_15_s),
.up_prbserr_out (up_ch_prbserr_15_s),
.up_prbslocked_out (up_ch_prbslocked_15_s));
assign up_ch_addr_15 = up_ch_addr; assign up_ch_addr_15 = up_ch_addr;
assign up_ch_wr_15 = up_ch_wr; assign up_ch_wr_15 = up_ch_wr;
@ -1886,6 +2145,11 @@ module axi_adxcvr #(
.up_ch_rst (up_ch_rst), .up_ch_rst (up_ch_rst),
.up_ch_user_ready (up_ch_user_ready), .up_ch_user_ready (up_ch_user_ready),
.up_ch_rst_done (up_ch_rst_done_15_s), .up_ch_rst_done (up_ch_rst_done_15_s),
.up_ch_prbsforceerr (up_ch_prbsforceerr),
.up_ch_prbssel (up_ch_prbssel),
.up_ch_prbscntreset (up_ch_prbscntreset),
.up_ch_prbserr (up_ch_prbserr_15_s),
.up_ch_prbslocked (up_ch_prbslocked_15_s),
.up_ch_lpm_dfe_n (up_ch_lpm_dfe_n), .up_ch_lpm_dfe_n (up_ch_lpm_dfe_n),
.up_ch_rate (up_ch_rate), .up_ch_rate (up_ch_rate),
.up_ch_sys_clk_sel (up_ch_sys_clk_sel), .up_ch_sys_clk_sel (up_ch_sys_clk_sel),

5
library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
View File

@ -51,6 +51,11 @@ for {set n 0} {$n < 16} {incr n} {
"rst up_ch_rst_${n} "\ "rst up_ch_rst_${n} "\
"user_ready up_ch_user_ready_${n} "\ "user_ready up_ch_user_ready_${n} "\
"rst_done up_ch_rst_done_${n} "\ "rst_done up_ch_rst_done_${n} "\
"prbsforceerr up_ch_prbsforceerr_${n}"\
"prbssel up_ch_prbssel_${n} "\
"prbscntreset up_ch_prbscntreset_${n}"\
"prbserr up_ch_prbserr_${n} "\
"prbslocked up_ch_prbslocked_${n} "\
"lpm_dfe_n up_ch_lpm_dfe_n_${n} "\ "lpm_dfe_n up_ch_lpm_dfe_n_${n} "\
"rate up_ch_rate_${n} "\ "rate up_ch_rate_${n} "\
"sys_clk_sel up_ch_sys_clk_sel_${n} "\ "sys_clk_sel up_ch_sys_clk_sel_${n} "\

20
library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
View File

@ -42,10 +42,16 @@ module axi_adxcvr_mstatus (
input up_pll_locked_in, input up_pll_locked_in,
input up_rst_done_in, input up_rst_done_in,
input up_prbserr_in,
input up_prbslocked_in,
input up_pll_locked, input up_pll_locked,
input up_rst_done, input up_rst_done,
input up_prbserr,
input up_prbslocked,
output up_pll_locked_out, output up_pll_locked_out,
output up_rst_done_out); output up_rst_done_out,
output up_prbserr_out,
output up_prbslocked_out);
// parameters // parameters
@ -56,27 +62,39 @@ module axi_adxcvr_mstatus (
reg up_pll_locked_int = 'd0; reg up_pll_locked_int = 'd0;
reg up_rst_done_int = 'd0; reg up_rst_done_int = 'd0;
reg up_prbserr_int = 'd0;
reg up_prbslocked_int = 'd0;
// internal signals // internal signals
wire up_pll_locked_s; wire up_pll_locked_s;
wire up_rst_done_s; wire up_rst_done_s;
wire up_prbserr_s;
wire up_prbslocked_s;
// daisy-chain the signals // daisy-chain the signals
assign up_pll_locked_out = up_pll_locked_int; assign up_pll_locked_out = up_pll_locked_int;
assign up_rst_done_out = up_rst_done_int; assign up_rst_done_out = up_rst_done_int;
assign up_prbserr_out = up_prbserr_int;
assign up_prbslocked_out = up_prbslocked_int;
assign up_pll_locked_s = (XCVR_ID < NUM_OF_LANES) ? up_pll_locked : 1'b1; assign up_pll_locked_s = (XCVR_ID < NUM_OF_LANES) ? up_pll_locked : 1'b1;
assign up_rst_done_s = (XCVR_ID < NUM_OF_LANES) ? up_rst_done : 1'b1; assign up_rst_done_s = (XCVR_ID < NUM_OF_LANES) ? up_rst_done : 1'b1;
assign up_prbserr_s = (XCVR_ID < NUM_OF_LANES) ? up_prbserr : 1'b0;
assign up_prbslocked_s = (XCVR_ID < NUM_OF_LANES) ? up_prbslocked : 1'b1;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin if (up_rstn == 1'b0) begin
up_pll_locked_int <= 1'd0; up_pll_locked_int <= 1'd0;
up_rst_done_int <= 1'd0; up_rst_done_int <= 1'd0;
up_prbserr_int <= 1'd0;
up_prbslocked_int <= 1'd0;
end else begin end else begin
up_pll_locked_int <= up_pll_locked_in & up_pll_locked_s; up_pll_locked_int <= up_pll_locked_in & up_pll_locked_s;
up_rst_done_int <= up_rst_done_in & up_rst_done_s; up_rst_done_int <= up_rst_done_in & up_rst_done_s;
up_prbserr_int <= up_prbserr_in | up_prbserr_s;
up_prbslocked_int <= up_prbslocked_in & up_prbslocked_s;
end end
end end

26
library/xilinx/axi_adxcvr/axi_adxcvr_up.v
View File

@ -73,6 +73,11 @@ module axi_adxcvr_up #(
output up_ch_rst, output up_ch_rst,
output up_ch_user_ready, output up_ch_user_ready,
input up_ch_rst_done, input up_ch_rst_done,
output up_ch_prbsforceerr,
output [ 3:0] up_ch_prbssel,
output up_ch_prbscntreset,
input up_ch_prbserr,
input up_ch_prbslocked,
output up_ch_lpm_dfe_n, output up_ch_lpm_dfe_n,
output [ 2:0] up_ch_rate, output [ 2:0] up_ch_rate,
output [ 1:0] up_ch_sys_clk_sel, output [ 1:0] up_ch_sys_clk_sel,
@ -169,6 +174,9 @@ module axi_adxcvr_up #(
reg up_ies_status = 'd0; reg up_ies_status = 'd0;
reg up_rreq_d = 'd0; reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0; reg [31:0] up_rdata_d = 'd0;
reg [3:0] up_prbssel = 'd0;
reg up_prbscntreset = 'd1;
reg up_prbsforceerr = 'd0;
// internal signals // internal signals
@ -247,6 +255,9 @@ module axi_adxcvr_up #(
assign up_ch_tx_diffctrl = up_tx_diffctrl; assign up_ch_tx_diffctrl = up_tx_diffctrl;
assign up_ch_tx_postcursor = up_tx_postcursor; assign up_ch_tx_postcursor = up_tx_postcursor;
assign up_ch_tx_precursor = up_tx_precursor; assign up_ch_tx_precursor = up_tx_precursor;
assign up_ch_prbssel = up_prbssel;
assign up_ch_prbscntreset = up_prbscntreset;
assign up_ch_prbsforceerr = up_prbsforceerr;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
@ -257,6 +268,9 @@ module axi_adxcvr_up #(
up_tx_diffctrl <= TX_DIFFCTRL; up_tx_diffctrl <= TX_DIFFCTRL;
up_tx_postcursor <= TX_POSTCURSOR; up_tx_postcursor <= TX_POSTCURSOR;
up_tx_precursor <= TX_PRECURSOR; up_tx_precursor <= TX_PRECURSOR;
up_prbssel <= 4'b0;
up_prbscntreset <= 1'b1;
up_prbsforceerr <= 1'b0;
end else begin end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin
up_lpm_dfe_n <= up_wdata[12]; up_lpm_dfe_n <= up_wdata[12];
@ -273,6 +287,11 @@ module axi_adxcvr_up #(
if ((up_wreq == 1'b1) && (up_waddr == 10'h032)) begin if ((up_wreq == 1'b1) && (up_waddr == 10'h032)) begin
up_tx_precursor <= up_wdata[4:0]; up_tx_precursor <= up_wdata[4:0];
end end
if ((up_wreq == 1'b1) && (up_waddr == 10'h060)) begin
up_prbssel <= up_wdata[3:0];
up_prbscntreset <= up_wdata[8];
up_prbsforceerr <= up_wdata[15];
end
end end
end end
@ -528,6 +547,13 @@ module axi_adxcvr_up #(
10'h031: up_rdata_d <= up_tx_postcursor; 10'h031: up_rdata_d <= up_tx_postcursor;
10'h032: up_rdata_d <= up_tx_precursor; 10'h032: up_rdata_d <= up_tx_precursor;
10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV 10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV
10'h060: up_rdata_d <= {8'b0,
7'b0,up_prbsforceerr,
7'b0,up_prbscntreset,
4'b0,up_prbssel};
10'h061: up_rdata_d <= {16'b0,
7'b0,up_ch_prbserr,
7'b0,up_ch_prbslocked};
default: up_rdata_d <= 32'd0; default: up_rdata_d <= 32'd0;
endcase endcase
end else begin end else begin

192
library/xilinx/util_adxcvr/util_adxcvr.v
View File

@ -153,6 +153,10 @@ module util_adxcvr #(
input up_rx_rst_0, input up_rx_rst_0,
input up_rx_user_ready_0, input up_rx_user_ready_0,
output up_rx_rst_done_0, output up_rx_rst_done_0,
input [ 3:0] up_rx_prbssel_0,
input up_rx_prbscntreset_0,
output up_rx_prbserr_0,
output up_rx_prbslocked_0,
input up_rx_lpm_dfe_n_0, input up_rx_lpm_dfe_n_0,
input [ 2:0] up_rx_rate_0, input [ 2:0] up_rx_rate_0,
input [ 1:0] up_rx_sys_clk_sel_0, input [ 1:0] up_rx_sys_clk_sel_0,
@ -167,6 +171,8 @@ module util_adxcvr #(
input up_tx_rst_0, input up_tx_rst_0,
input up_tx_user_ready_0, input up_tx_user_ready_0,
output up_tx_rst_done_0, output up_tx_rst_done_0,
input up_tx_prbsforceerr_0,
input [ 3:0] up_tx_prbssel_0,
input up_tx_lpm_dfe_n_0, input up_tx_lpm_dfe_n_0,
input [ 2:0] up_tx_rate_0, input [ 2:0] up_tx_rate_0,
input [ 1:0] up_tx_sys_clk_sel_0, input [ 1:0] up_tx_sys_clk_sel_0,
@ -212,6 +218,10 @@ module util_adxcvr #(
input up_rx_rst_1, input up_rx_rst_1,
input up_rx_user_ready_1, input up_rx_user_ready_1,
output up_rx_rst_done_1, output up_rx_rst_done_1,
input [ 3:0] up_rx_prbssel_1,
input up_rx_prbscntreset_1,
output up_rx_prbserr_1,
output up_rx_prbslocked_1,
input up_rx_lpm_dfe_n_1, input up_rx_lpm_dfe_n_1,
input [ 2:0] up_rx_rate_1, input [ 2:0] up_rx_rate_1,
input [ 1:0] up_rx_sys_clk_sel_1, input [ 1:0] up_rx_sys_clk_sel_1,
@ -226,6 +236,8 @@ module util_adxcvr #(
input up_tx_rst_1, input up_tx_rst_1,
input up_tx_user_ready_1, input up_tx_user_ready_1,
output up_tx_rst_done_1, output up_tx_rst_done_1,
input up_tx_prbsforceerr_1,
input [ 3:0] up_tx_prbssel_1,
input up_tx_lpm_dfe_n_1, input up_tx_lpm_dfe_n_1,
input [ 2:0] up_tx_rate_1, input [ 2:0] up_tx_rate_1,
input [ 1:0] up_tx_sys_clk_sel_1, input [ 1:0] up_tx_sys_clk_sel_1,
@ -271,6 +283,10 @@ module util_adxcvr #(
input up_rx_rst_2, input up_rx_rst_2,
input up_rx_user_ready_2, input up_rx_user_ready_2,
output up_rx_rst_done_2, output up_rx_rst_done_2,
input [ 3:0] up_rx_prbssel_2,
input up_rx_prbscntreset_2,
output up_rx_prbserr_2,
output up_rx_prbslocked_2,
input up_rx_lpm_dfe_n_2, input up_rx_lpm_dfe_n_2,
input [ 2:0] up_rx_rate_2, input [ 2:0] up_rx_rate_2,
input [ 1:0] up_rx_sys_clk_sel_2, input [ 1:0] up_rx_sys_clk_sel_2,
@ -285,6 +301,8 @@ module util_adxcvr #(
input up_tx_rst_2, input up_tx_rst_2,
input up_tx_user_ready_2, input up_tx_user_ready_2,
output up_tx_rst_done_2, output up_tx_rst_done_2,
input up_tx_prbsforceerr_2,
input [ 3:0] up_tx_prbssel_2,
input up_tx_lpm_dfe_n_2, input up_tx_lpm_dfe_n_2,
input [ 2:0] up_tx_rate_2, input [ 2:0] up_tx_rate_2,
input [ 1:0] up_tx_sys_clk_sel_2, input [ 1:0] up_tx_sys_clk_sel_2,
@ -330,6 +348,10 @@ module util_adxcvr #(
input up_rx_rst_3, input up_rx_rst_3,
input up_rx_user_ready_3, input up_rx_user_ready_3,
output up_rx_rst_done_3, output up_rx_rst_done_3,
input [ 3:0] up_rx_prbssel_3,
input up_rx_prbscntreset_3,
output up_rx_prbserr_3,
output up_rx_prbslocked_3,
input up_rx_lpm_dfe_n_3, input up_rx_lpm_dfe_n_3,
input [ 2:0] up_rx_rate_3, input [ 2:0] up_rx_rate_3,
input [ 1:0] up_rx_sys_clk_sel_3, input [ 1:0] up_rx_sys_clk_sel_3,
@ -344,6 +366,8 @@ module util_adxcvr #(
input up_tx_rst_3, input up_tx_rst_3,
input up_tx_user_ready_3, input up_tx_user_ready_3,
output up_tx_rst_done_3, output up_tx_rst_done_3,
input up_tx_prbsforceerr_3,
input [ 3:0] up_tx_prbssel_3,
input up_tx_lpm_dfe_n_3, input up_tx_lpm_dfe_n_3,
input [ 2:0] up_tx_rate_3, input [ 2:0] up_tx_rate_3,
input [ 1:0] up_tx_sys_clk_sel_3, input [ 1:0] up_tx_sys_clk_sel_3,
@ -397,6 +421,10 @@ module util_adxcvr #(
input up_rx_rst_4, input up_rx_rst_4,
input up_rx_user_ready_4, input up_rx_user_ready_4,
output up_rx_rst_done_4, output up_rx_rst_done_4,
input [ 3:0] up_rx_prbssel_4,
input up_rx_prbscntreset_4,
output up_rx_prbserr_4,
output up_rx_prbslocked_4,
input up_rx_lpm_dfe_n_4, input up_rx_lpm_dfe_n_4,
input [ 2:0] up_rx_rate_4, input [ 2:0] up_rx_rate_4,
input [ 1:0] up_rx_sys_clk_sel_4, input [ 1:0] up_rx_sys_clk_sel_4,
@ -411,6 +439,8 @@ module util_adxcvr #(
input up_tx_rst_4, input up_tx_rst_4,
input up_tx_user_ready_4, input up_tx_user_ready_4,
output up_tx_rst_done_4, output up_tx_rst_done_4,
input up_tx_prbsforceerr_4,
input [ 3:0] up_tx_prbssel_4,
input up_tx_lpm_dfe_n_4, input up_tx_lpm_dfe_n_4,
input [ 2:0] up_tx_rate_4, input [ 2:0] up_tx_rate_4,
input [ 1:0] up_tx_sys_clk_sel_4, input [ 1:0] up_tx_sys_clk_sel_4,
@ -456,6 +486,10 @@ module util_adxcvr #(
input up_rx_rst_5, input up_rx_rst_5,
input up_rx_user_ready_5, input up_rx_user_ready_5,
output up_rx_rst_done_5, output up_rx_rst_done_5,
input [ 3:0] up_rx_prbssel_5,
input up_rx_prbscntreset_5,
output up_rx_prbserr_5,
output up_rx_prbslocked_5,
input up_rx_lpm_dfe_n_5, input up_rx_lpm_dfe_n_5,
input [ 2:0] up_rx_rate_5, input [ 2:0] up_rx_rate_5,
input [ 1:0] up_rx_sys_clk_sel_5, input [ 1:0] up_rx_sys_clk_sel_5,
@ -470,6 +504,8 @@ module util_adxcvr #(
input up_tx_rst_5, input up_tx_rst_5,
input up_tx_user_ready_5, input up_tx_user_ready_5,
output up_tx_rst_done_5, output up_tx_rst_done_5,
input up_tx_prbsforceerr_5,
input [ 3:0] up_tx_prbssel_5,
input up_tx_lpm_dfe_n_5, input up_tx_lpm_dfe_n_5,
input [ 2:0] up_tx_rate_5, input [ 2:0] up_tx_rate_5,
input [ 1:0] up_tx_sys_clk_sel_5, input [ 1:0] up_tx_sys_clk_sel_5,
@ -515,6 +551,10 @@ module util_adxcvr #(
input up_rx_rst_6, input up_rx_rst_6,
input up_rx_user_ready_6, input up_rx_user_ready_6,
output up_rx_rst_done_6, output up_rx_rst_done_6,
input [ 3:0] up_rx_prbssel_6,
input up_rx_prbscntreset_6,
output up_rx_prbserr_6,
output up_rx_prbslocked_6,
input up_rx_lpm_dfe_n_6, input up_rx_lpm_dfe_n_6,
input [ 2:0] up_rx_rate_6, input [ 2:0] up_rx_rate_6,
input [ 1:0] up_rx_sys_clk_sel_6, input [ 1:0] up_rx_sys_clk_sel_6,
@ -529,6 +569,8 @@ module util_adxcvr #(
input up_tx_rst_6, input up_tx_rst_6,
input up_tx_user_ready_6, input up_tx_user_ready_6,
output up_tx_rst_done_6, output up_tx_rst_done_6,
input up_tx_prbsforceerr_6,
input [ 3:0] up_tx_prbssel_6,
input up_tx_lpm_dfe_n_6, input up_tx_lpm_dfe_n_6,
input [ 2:0] up_tx_rate_6, input [ 2:0] up_tx_rate_6,
input [ 1:0] up_tx_sys_clk_sel_6, input [ 1:0] up_tx_sys_clk_sel_6,
@ -574,6 +616,10 @@ module util_adxcvr #(
input up_rx_rst_7, input up_rx_rst_7,
input up_rx_user_ready_7, input up_rx_user_ready_7,
output up_rx_rst_done_7, output up_rx_rst_done_7,
input [ 3:0] up_rx_prbssel_7,
input up_rx_prbscntreset_7,
output up_rx_prbserr_7,
output up_rx_prbslocked_7,
input up_rx_lpm_dfe_n_7, input up_rx_lpm_dfe_n_7,
input [ 2:0] up_rx_rate_7, input [ 2:0] up_rx_rate_7,
input [ 1:0] up_rx_sys_clk_sel_7, input [ 1:0] up_rx_sys_clk_sel_7,
@ -588,6 +634,8 @@ module util_adxcvr #(
input up_tx_rst_7, input up_tx_rst_7,
input up_tx_user_ready_7, input up_tx_user_ready_7,
output up_tx_rst_done_7, output up_tx_rst_done_7,
input up_tx_prbsforceerr_7,
input [ 3:0] up_tx_prbssel_7,
input up_tx_lpm_dfe_n_7, input up_tx_lpm_dfe_n_7,
input [ 2:0] up_tx_rate_7, input [ 2:0] up_tx_rate_7,
input [ 1:0] up_tx_sys_clk_sel_7, input [ 1:0] up_tx_sys_clk_sel_7,
@ -641,6 +689,10 @@ module util_adxcvr #(
input up_rx_rst_8, input up_rx_rst_8,
input up_rx_user_ready_8, input up_rx_user_ready_8,
output up_rx_rst_done_8, output up_rx_rst_done_8,
input [ 3:0] up_rx_prbssel_8,
input up_rx_prbscntreset_8,
output up_rx_prbserr_8,
output up_rx_prbslocked_8,
input up_rx_lpm_dfe_n_8, input up_rx_lpm_dfe_n_8,
input [ 2:0] up_rx_rate_8, input [ 2:0] up_rx_rate_8,
input [ 1:0] up_rx_sys_clk_sel_8, input [ 1:0] up_rx_sys_clk_sel_8,
@ -655,6 +707,8 @@ module util_adxcvr #(
input up_tx_rst_8, input up_tx_rst_8,
input up_tx_user_ready_8, input up_tx_user_ready_8,
output up_tx_rst_done_8, output up_tx_rst_done_8,
input up_tx_prbsforceerr_8,
input [ 3:0] up_tx_prbssel_8,
input up_tx_lpm_dfe_n_8, input up_tx_lpm_dfe_n_8,
input [ 2:0] up_tx_rate_8, input [ 2:0] up_tx_rate_8,
input [ 1:0] up_tx_sys_clk_sel_8, input [ 1:0] up_tx_sys_clk_sel_8,
@ -700,6 +754,10 @@ module util_adxcvr #(
input up_rx_rst_9, input up_rx_rst_9,
input up_rx_user_ready_9, input up_rx_user_ready_9,
output up_rx_rst_done_9, output up_rx_rst_done_9,
input [ 3:0] up_rx_prbssel_9,
input up_rx_prbscntreset_9,
output up_rx_prbserr_9,
output up_rx_prbslocked_9,
input up_rx_lpm_dfe_n_9, input up_rx_lpm_dfe_n_9,
input [ 2:0] up_rx_rate_9, input [ 2:0] up_rx_rate_9,
input [ 1:0] up_rx_sys_clk_sel_9, input [ 1:0] up_rx_sys_clk_sel_9,
@ -714,6 +772,8 @@ module util_adxcvr #(
input up_tx_rst_9, input up_tx_rst_9,
input up_tx_user_ready_9, input up_tx_user_ready_9,
output up_tx_rst_done_9, output up_tx_rst_done_9,
input up_tx_prbsforceerr_9,
input [ 3:0] up_tx_prbssel_9,
input up_tx_lpm_dfe_n_9, input up_tx_lpm_dfe_n_9,
input [ 2:0] up_tx_rate_9, input [ 2:0] up_tx_rate_9,
input [ 1:0] up_tx_sys_clk_sel_9, input [ 1:0] up_tx_sys_clk_sel_9,
@ -759,6 +819,10 @@ module util_adxcvr #(
input up_rx_rst_10, input up_rx_rst_10,
input up_rx_user_ready_10, input up_rx_user_ready_10,
output up_rx_rst_done_10, output up_rx_rst_done_10,
input [ 3:0] up_rx_prbssel_10,
input up_rx_prbscntreset_10,
output up_rx_prbserr_10,
output up_rx_prbslocked_10,
input up_rx_lpm_dfe_n_10, input up_rx_lpm_dfe_n_10,
input [ 2:0] up_rx_rate_10, input [ 2:0] up_rx_rate_10,
input [ 1:0] up_rx_sys_clk_sel_10, input [ 1:0] up_rx_sys_clk_sel_10,
@ -773,6 +837,8 @@ module util_adxcvr #(
input up_tx_rst_10, input up_tx_rst_10,
input up_tx_user_ready_10, input up_tx_user_ready_10,
output up_tx_rst_done_10, output up_tx_rst_done_10,
input up_tx_prbsforceerr_10,
input [ 3:0] up_tx_prbssel_10,
input up_tx_lpm_dfe_n_10, input up_tx_lpm_dfe_n_10,
input [ 2:0] up_tx_rate_10, input [ 2:0] up_tx_rate_10,
input [ 1:0] up_tx_sys_clk_sel_10, input [ 1:0] up_tx_sys_clk_sel_10,
@ -818,6 +884,10 @@ module util_adxcvr #(
input up_rx_rst_11, input up_rx_rst_11,
input up_rx_user_ready_11, input up_rx_user_ready_11,
output up_rx_rst_done_11, output up_rx_rst_done_11,
input [ 3:0] up_rx_prbssel_11,
input up_rx_prbscntreset_11,
output up_rx_prbserr_11,
output up_rx_prbslocked_11,
input up_rx_lpm_dfe_n_11, input up_rx_lpm_dfe_n_11,
input [ 2:0] up_rx_rate_11, input [ 2:0] up_rx_rate_11,
input [ 1:0] up_rx_sys_clk_sel_11, input [ 1:0] up_rx_sys_clk_sel_11,
@ -832,6 +902,8 @@ module util_adxcvr #(
input up_tx_rst_11, input up_tx_rst_11,
input up_tx_user_ready_11, input up_tx_user_ready_11,
output up_tx_rst_done_11, output up_tx_rst_done_11,
input up_tx_prbsforceerr_11,
input [ 3:0] up_tx_prbssel_11,
input up_tx_lpm_dfe_n_11, input up_tx_lpm_dfe_n_11,
input [ 2:0] up_tx_rate_11, input [ 2:0] up_tx_rate_11,
input [ 1:0] up_tx_sys_clk_sel_11, input [ 1:0] up_tx_sys_clk_sel_11,
@ -885,6 +957,10 @@ module util_adxcvr #(
input up_rx_rst_12, input up_rx_rst_12,
input up_rx_user_ready_12, input up_rx_user_ready_12,
output up_rx_rst_done_12, output up_rx_rst_done_12,
input [ 3:0] up_rx_prbssel_12,
input up_rx_prbscntreset_12,
output up_rx_prbserr_12,
output up_rx_prbslocked_12,
input up_rx_lpm_dfe_n_12, input up_rx_lpm_dfe_n_12,
input [ 2:0] up_rx_rate_12, input [ 2:0] up_rx_rate_12,
input [ 1:0] up_rx_sys_clk_sel_12, input [ 1:0] up_rx_sys_clk_sel_12,
@ -899,6 +975,8 @@ module util_adxcvr #(
input up_tx_rst_12, input up_tx_rst_12,
input up_tx_user_ready_12, input up_tx_user_ready_12,
output up_tx_rst_done_12, output up_tx_rst_done_12,
input up_tx_prbsforceerr_12,
input [ 3:0] up_tx_prbssel_12,
input up_tx_lpm_dfe_n_12, input up_tx_lpm_dfe_n_12,
input [ 2:0] up_tx_rate_12, input [ 2:0] up_tx_rate_12,
input [ 1:0] up_tx_sys_clk_sel_12, input [ 1:0] up_tx_sys_clk_sel_12,
@ -944,6 +1022,10 @@ module util_adxcvr #(
input up_rx_rst_13, input up_rx_rst_13,
input up_rx_user_ready_13, input up_rx_user_ready_13,
output up_rx_rst_done_13, output up_rx_rst_done_13,
input [ 3:0] up_rx_prbssel_13,
input up_rx_prbscntreset_13,
output up_rx_prbserr_13,
output up_rx_prbslocked_13,
input up_rx_lpm_dfe_n_13, input up_rx_lpm_dfe_n_13,
input [ 2:0] up_rx_rate_13, input [ 2:0] up_rx_rate_13,
input [ 1:0] up_rx_sys_clk_sel_13, input [ 1:0] up_rx_sys_clk_sel_13,
@ -958,6 +1040,8 @@ module util_adxcvr #(
input up_tx_rst_13, input up_tx_rst_13,
input up_tx_user_ready_13, input up_tx_user_ready_13,
output up_tx_rst_done_13, output up_tx_rst_done_13,
input up_tx_prbsforceerr_13,
input [ 3:0] up_tx_prbssel_13,
input up_tx_lpm_dfe_n_13, input up_tx_lpm_dfe_n_13,
input [ 2:0] up_tx_rate_13, input [ 2:0] up_tx_rate_13,
input [ 1:0] up_tx_sys_clk_sel_13, input [ 1:0] up_tx_sys_clk_sel_13,
@ -1003,6 +1087,10 @@ module util_adxcvr #(
input up_rx_rst_14, input up_rx_rst_14,
input up_rx_user_ready_14, input up_rx_user_ready_14,
output up_rx_rst_done_14, output up_rx_rst_done_14,
input [ 3:0] up_rx_prbssel_14,
input up_rx_prbscntreset_14,
output up_rx_prbserr_14,
output up_rx_prbslocked_14,
input up_rx_lpm_dfe_n_14, input up_rx_lpm_dfe_n_14,
input [ 2:0] up_rx_rate_14, input [ 2:0] up_rx_rate_14,
input [ 1:0] up_rx_sys_clk_sel_14, input [ 1:0] up_rx_sys_clk_sel_14,
@ -1017,6 +1105,8 @@ module util_adxcvr #(
input up_tx_rst_14, input up_tx_rst_14,
input up_tx_user_ready_14, input up_tx_user_ready_14,
output up_tx_rst_done_14, output up_tx_rst_done_14,
input up_tx_prbsforceerr_14,
input [ 3:0] up_tx_prbssel_14,
input up_tx_lpm_dfe_n_14, input up_tx_lpm_dfe_n_14,
input [ 2:0] up_tx_rate_14, input [ 2:0] up_tx_rate_14,
input [ 1:0] up_tx_sys_clk_sel_14, input [ 1:0] up_tx_sys_clk_sel_14,
@ -1062,6 +1152,10 @@ module util_adxcvr #(
input up_rx_rst_15, input up_rx_rst_15,
input up_rx_user_ready_15, input up_rx_user_ready_15,
output up_rx_rst_done_15, output up_rx_rst_done_15,
input [ 3:0] up_rx_prbssel_15,
input up_rx_prbscntreset_15,
output up_rx_prbserr_15,
output up_rx_prbslocked_15,
input up_rx_lpm_dfe_n_15, input up_rx_lpm_dfe_n_15,
input [ 2:0] up_rx_rate_15, input [ 2:0] up_rx_rate_15,
input [ 1:0] up_rx_sys_clk_sel_15, input [ 1:0] up_rx_sys_clk_sel_15,
@ -1076,6 +1170,8 @@ module util_adxcvr #(
input up_tx_rst_15, input up_tx_rst_15,
input up_tx_user_ready_15, input up_tx_user_ready_15,
output up_tx_rst_done_15, output up_tx_rst_done_15,
input up_tx_prbsforceerr_15,
input [ 3:0] up_tx_prbssel_15,
input up_tx_lpm_dfe_n_15, input up_tx_lpm_dfe_n_15,
input [ 2:0] up_tx_rate_15, input [ 2:0] up_tx_rate_15,
input [ 1:0] up_tx_sys_clk_sel_15, input [ 1:0] up_tx_sys_clk_sel_15,
@ -1275,6 +1371,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_0), .up_rx_rst (up_rx_rst_0),
.up_rx_user_ready (up_rx_user_ready_0), .up_rx_user_ready (up_rx_user_ready_0),
.up_rx_rst_done (up_rx_rst_done_0), .up_rx_rst_done (up_rx_rst_done_0),
.up_rx_prbssel (up_rx_prbssel_0),
.up_rx_prbscntreset (up_rx_prbscntreset_0),
.up_rx_prbserr (up_rx_prbserr_0),
.up_rx_prbslocked (up_rx_prbslocked_0),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_0), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_0),
.up_rx_rate (up_rx_rate_0), .up_rx_rate (up_rx_rate_0),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_0), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_0),
@ -1289,6 +1389,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_0), .up_tx_rst (up_tx_rst_0),
.up_tx_user_ready (up_tx_user_ready_0), .up_tx_user_ready (up_tx_user_ready_0),
.up_tx_rst_done (up_tx_rst_done_0), .up_tx_rst_done (up_tx_rst_done_0),
.up_tx_prbsforceerr (up_tx_prbsforceerr_0),
.up_tx_prbssel (up_tx_prbssel_0),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_0), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_0),
.up_tx_rate (up_tx_rate_0), .up_tx_rate (up_tx_rate_0),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_0), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_0),
@ -1405,6 +1507,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_1), .up_rx_rst (up_rx_rst_1),
.up_rx_user_ready (up_rx_user_ready_1), .up_rx_user_ready (up_rx_user_ready_1),
.up_rx_rst_done (up_rx_rst_done_1), .up_rx_rst_done (up_rx_rst_done_1),
.up_rx_prbssel (up_rx_prbssel_1),
.up_rx_prbscntreset (up_rx_prbscntreset_1),
.up_rx_prbserr (up_rx_prbserr_1),
.up_rx_prbslocked (up_rx_prbslocked_1),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_1), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_1),
.up_rx_rate (up_rx_rate_1), .up_rx_rate (up_rx_rate_1),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_1), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_1),
@ -1419,6 +1525,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_1), .up_tx_rst (up_tx_rst_1),
.up_tx_user_ready (up_tx_user_ready_1), .up_tx_user_ready (up_tx_user_ready_1),
.up_tx_rst_done (up_tx_rst_done_1), .up_tx_rst_done (up_tx_rst_done_1),
.up_tx_prbsforceerr (up_tx_prbsforceerr_1),
.up_tx_prbssel (up_tx_prbssel_1),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_1), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_1),
.up_tx_rate (up_tx_rate_1), .up_tx_rate (up_tx_rate_1),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_1), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_1),
@ -1535,6 +1643,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_2), .up_rx_rst (up_rx_rst_2),
.up_rx_user_ready (up_rx_user_ready_2), .up_rx_user_ready (up_rx_user_ready_2),
.up_rx_rst_done (up_rx_rst_done_2), .up_rx_rst_done (up_rx_rst_done_2),
.up_rx_prbssel (up_rx_prbssel_2),
.up_rx_prbscntreset (up_rx_prbscntreset_2),
.up_rx_prbserr (up_rx_prbserr_2),
.up_rx_prbslocked (up_rx_prbslocked_2),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_2), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_2),
.up_rx_rate (up_rx_rate_2), .up_rx_rate (up_rx_rate_2),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_2), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_2),
@ -1549,6 +1661,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_2), .up_tx_rst (up_tx_rst_2),
.up_tx_user_ready (up_tx_user_ready_2), .up_tx_user_ready (up_tx_user_ready_2),
.up_tx_rst_done (up_tx_rst_done_2), .up_tx_rst_done (up_tx_rst_done_2),
.up_tx_prbsforceerr (up_tx_prbsforceerr_2),
.up_tx_prbssel (up_tx_prbssel_2),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_2), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_2),
.up_tx_rate (up_tx_rate_2), .up_tx_rate (up_tx_rate_2),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_2), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_2),
@ -1665,6 +1779,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_3), .up_rx_rst (up_rx_rst_3),
.up_rx_user_ready (up_rx_user_ready_3), .up_rx_user_ready (up_rx_user_ready_3),
.up_rx_rst_done (up_rx_rst_done_3), .up_rx_rst_done (up_rx_rst_done_3),
.up_rx_prbssel (up_rx_prbssel_3),
.up_rx_prbscntreset (up_rx_prbscntreset_3),
.up_rx_prbserr (up_rx_prbserr_3),
.up_rx_prbslocked (up_rx_prbslocked_3),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_3), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_3),
.up_rx_rate (up_rx_rate_3), .up_rx_rate (up_rx_rate_3),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_3), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_3),
@ -1679,6 +1797,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_3), .up_tx_rst (up_tx_rst_3),
.up_tx_user_ready (up_tx_user_ready_3), .up_tx_user_ready (up_tx_user_ready_3),
.up_tx_rst_done (up_tx_rst_done_3), .up_tx_rst_done (up_tx_rst_done_3),
.up_tx_prbsforceerr (up_tx_prbsforceerr_3),
.up_tx_prbssel (up_tx_prbssel_3),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_3), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_3),
.up_tx_rate (up_tx_rate_3), .up_tx_rate (up_tx_rate_3),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_3), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_3),
@ -1844,6 +1964,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_4), .up_rx_rst (up_rx_rst_4),
.up_rx_user_ready (up_rx_user_ready_4), .up_rx_user_ready (up_rx_user_ready_4),
.up_rx_rst_done (up_rx_rst_done_4), .up_rx_rst_done (up_rx_rst_done_4),
.up_rx_prbssel (up_rx_prbssel_4),
.up_rx_prbscntreset (up_rx_prbscntreset_4),
.up_rx_prbserr (up_rx_prbserr_4),
.up_rx_prbslocked (up_rx_prbslocked_4),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_4), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_4),
.up_rx_rate (up_rx_rate_4), .up_rx_rate (up_rx_rate_4),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_4), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_4),
@ -1858,6 +1982,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_4), .up_tx_rst (up_tx_rst_4),
.up_tx_user_ready (up_tx_user_ready_4), .up_tx_user_ready (up_tx_user_ready_4),
.up_tx_rst_done (up_tx_rst_done_4), .up_tx_rst_done (up_tx_rst_done_4),
.up_tx_prbsforceerr (up_tx_prbsforceerr_4),
.up_tx_prbssel (up_tx_prbssel_4),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_4), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_4),
.up_tx_rate (up_tx_rate_4), .up_tx_rate (up_tx_rate_4),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_4), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_4),
@ -1974,6 +2100,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_5), .up_rx_rst (up_rx_rst_5),
.up_rx_user_ready (up_rx_user_ready_5), .up_rx_user_ready (up_rx_user_ready_5),
.up_rx_rst_done (up_rx_rst_done_5), .up_rx_rst_done (up_rx_rst_done_5),
.up_rx_prbssel (up_rx_prbssel_5),
.up_rx_prbscntreset (up_rx_prbscntreset_5),
.up_rx_prbserr (up_rx_prbserr_5),
.up_rx_prbslocked (up_rx_prbslocked_5),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_5), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_5),
.up_rx_rate (up_rx_rate_5), .up_rx_rate (up_rx_rate_5),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_5), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_5),
@ -1988,6 +2118,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_5), .up_tx_rst (up_tx_rst_5),
.up_tx_user_ready (up_tx_user_ready_5), .up_tx_user_ready (up_tx_user_ready_5),
.up_tx_rst_done (up_tx_rst_done_5), .up_tx_rst_done (up_tx_rst_done_5),
.up_tx_prbsforceerr (up_tx_prbsforceerr_5),
.up_tx_prbssel (up_tx_prbssel_5),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_5), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_5),
.up_tx_rate (up_tx_rate_5), .up_tx_rate (up_tx_rate_5),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_5), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_5),
@ -2104,6 +2236,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_6), .up_rx_rst (up_rx_rst_6),
.up_rx_user_ready (up_rx_user_ready_6), .up_rx_user_ready (up_rx_user_ready_6),
.up_rx_rst_done (up_rx_rst_done_6), .up_rx_rst_done (up_rx_rst_done_6),
.up_rx_prbssel (up_rx_prbssel_6),
.up_rx_prbscntreset (up_rx_prbscntreset_6),
.up_rx_prbserr (up_rx_prbserr_6),
.up_rx_prbslocked (up_rx_prbslocked_6),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_6), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_6),
.up_rx_rate (up_rx_rate_6), .up_rx_rate (up_rx_rate_6),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_6), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_6),
@ -2118,6 +2254,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_6), .up_tx_rst (up_tx_rst_6),
.up_tx_user_ready (up_tx_user_ready_6), .up_tx_user_ready (up_tx_user_ready_6),
.up_tx_rst_done (up_tx_rst_done_6), .up_tx_rst_done (up_tx_rst_done_6),
.up_tx_prbsforceerr (up_tx_prbsforceerr_6),
.up_tx_prbssel (up_tx_prbssel_6),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_6), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_6),
.up_tx_rate (up_tx_rate_6), .up_tx_rate (up_tx_rate_6),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_6), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_6),
@ -2234,6 +2372,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_7), .up_rx_rst (up_rx_rst_7),
.up_rx_user_ready (up_rx_user_ready_7), .up_rx_user_ready (up_rx_user_ready_7),
.up_rx_rst_done (up_rx_rst_done_7), .up_rx_rst_done (up_rx_rst_done_7),
.up_rx_prbssel (up_rx_prbssel_7),
.up_rx_prbscntreset (up_rx_prbscntreset_7),
.up_rx_prbserr (up_rx_prbserr_7),
.up_rx_prbslocked (up_rx_prbslocked_7),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_7), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_7),
.up_rx_rate (up_rx_rate_7), .up_rx_rate (up_rx_rate_7),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_7), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_7),
@ -2248,6 +2390,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_7), .up_tx_rst (up_tx_rst_7),
.up_tx_user_ready (up_tx_user_ready_7), .up_tx_user_ready (up_tx_user_ready_7),
.up_tx_rst_done (up_tx_rst_done_7), .up_tx_rst_done (up_tx_rst_done_7),
.up_tx_prbsforceerr (up_tx_prbsforceerr_7),
.up_tx_prbssel (up_tx_prbssel_7),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_7), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_7),
.up_tx_rate (up_tx_rate_7), .up_tx_rate (up_tx_rate_7),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_7), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_7),
@ -2413,6 +2557,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_8), .up_rx_rst (up_rx_rst_8),
.up_rx_user_ready (up_rx_user_ready_8), .up_rx_user_ready (up_rx_user_ready_8),
.up_rx_rst_done (up_rx_rst_done_8), .up_rx_rst_done (up_rx_rst_done_8),
.up_rx_prbssel (up_rx_prbssel_8),
.up_rx_prbscntreset (up_rx_prbscntreset_8),
.up_rx_prbserr (up_rx_prbserr_8),
.up_rx_prbslocked (up_rx_prbslocked_8),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_8), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_8),
.up_rx_rate (up_rx_rate_8), .up_rx_rate (up_rx_rate_8),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_8), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_8),
@ -2427,6 +2575,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_8), .up_tx_rst (up_tx_rst_8),
.up_tx_user_ready (up_tx_user_ready_8), .up_tx_user_ready (up_tx_user_ready_8),
.up_tx_rst_done (up_tx_rst_done_8), .up_tx_rst_done (up_tx_rst_done_8),
.up_tx_prbsforceerr (up_tx_prbsforceerr_8),
.up_tx_prbssel (up_tx_prbssel_8),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_8), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_8),
.up_tx_rate (up_tx_rate_8), .up_tx_rate (up_tx_rate_8),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_8), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_8),
@ -2543,6 +2693,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_9), .up_rx_rst (up_rx_rst_9),
.up_rx_user_ready (up_rx_user_ready_9), .up_rx_user_ready (up_rx_user_ready_9),
.up_rx_rst_done (up_rx_rst_done_9), .up_rx_rst_done (up_rx_rst_done_9),
.up_rx_prbssel (up_rx_prbssel_9),
.up_rx_prbscntreset (up_rx_prbscntreset_9),
.up_rx_prbserr (up_rx_prbserr_9),
.up_rx_prbslocked (up_rx_prbslocked_9),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_9), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_9),
.up_rx_rate (up_rx_rate_9), .up_rx_rate (up_rx_rate_9),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_9), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_9),
@ -2557,6 +2711,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_9), .up_tx_rst (up_tx_rst_9),
.up_tx_user_ready (up_tx_user_ready_9), .up_tx_user_ready (up_tx_user_ready_9),
.up_tx_rst_done (up_tx_rst_done_9), .up_tx_rst_done (up_tx_rst_done_9),
.up_tx_prbsforceerr (up_tx_prbsforceerr_9),
.up_tx_prbssel (up_tx_prbssel_9),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_9), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_9),
.up_tx_rate (up_tx_rate_9), .up_tx_rate (up_tx_rate_9),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_9), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_9),
@ -2673,6 +2829,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_10), .up_rx_rst (up_rx_rst_10),
.up_rx_user_ready (up_rx_user_ready_10), .up_rx_user_ready (up_rx_user_ready_10),
.up_rx_rst_done (up_rx_rst_done_10), .up_rx_rst_done (up_rx_rst_done_10),
.up_rx_prbssel (up_rx_prbssel_10),
.up_rx_prbscntreset (up_rx_prbscntreset_10),
.up_rx_prbserr (up_rx_prbserr_10),
.up_rx_prbslocked (up_rx_prbslocked_10),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_10), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_10),
.up_rx_rate (up_rx_rate_10), .up_rx_rate (up_rx_rate_10),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_10), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_10),
@ -2687,6 +2847,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_10), .up_tx_rst (up_tx_rst_10),
.up_tx_user_ready (up_tx_user_ready_10), .up_tx_user_ready (up_tx_user_ready_10),
.up_tx_rst_done (up_tx_rst_done_10), .up_tx_rst_done (up_tx_rst_done_10),
.up_tx_prbsforceerr (up_tx_prbsforceerr_10),
.up_tx_prbssel (up_tx_prbssel_10),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_10), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_10),
.up_tx_rate (up_tx_rate_10), .up_tx_rate (up_tx_rate_10),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_10), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_10),
@ -2803,6 +2965,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_11), .up_rx_rst (up_rx_rst_11),
.up_rx_user_ready (up_rx_user_ready_11), .up_rx_user_ready (up_rx_user_ready_11),
.up_rx_rst_done (up_rx_rst_done_11), .up_rx_rst_done (up_rx_rst_done_11),
.up_rx_prbssel (up_rx_prbssel_11),
.up_rx_prbscntreset (up_rx_prbscntreset_11),
.up_rx_prbserr (up_rx_prbserr_11),
.up_rx_prbslocked (up_rx_prbslocked_11),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_11), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_11),
.up_rx_rate (up_rx_rate_11), .up_rx_rate (up_rx_rate_11),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_11), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_11),
@ -2817,6 +2983,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_11), .up_tx_rst (up_tx_rst_11),
.up_tx_user_ready (up_tx_user_ready_11), .up_tx_user_ready (up_tx_user_ready_11),
.up_tx_rst_done (up_tx_rst_done_11), .up_tx_rst_done (up_tx_rst_done_11),
.up_tx_prbsforceerr (up_tx_prbsforceerr_11),
.up_tx_prbssel (up_tx_prbssel_11),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_11), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_11),
.up_tx_rate (up_tx_rate_11), .up_tx_rate (up_tx_rate_11),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_11), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_11),
@ -2982,6 +3150,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_12), .up_rx_rst (up_rx_rst_12),
.up_rx_user_ready (up_rx_user_ready_12), .up_rx_user_ready (up_rx_user_ready_12),
.up_rx_rst_done (up_rx_rst_done_12), .up_rx_rst_done (up_rx_rst_done_12),
.up_rx_prbssel (up_rx_prbssel_12),
.up_rx_prbscntreset (up_rx_prbscntreset_12),
.up_rx_prbserr (up_rx_prbserr_12),
.up_rx_prbslocked (up_rx_prbslocked_12),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_12), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_12),
.up_rx_rate (up_rx_rate_12), .up_rx_rate (up_rx_rate_12),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_12), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_12),
@ -2996,6 +3168,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_12), .up_tx_rst (up_tx_rst_12),
.up_tx_user_ready (up_tx_user_ready_12), .up_tx_user_ready (up_tx_user_ready_12),
.up_tx_rst_done (up_tx_rst_done_12), .up_tx_rst_done (up_tx_rst_done_12),
.up_tx_prbsforceerr (up_tx_prbsforceerr_12),
.up_tx_prbssel (up_tx_prbssel_12),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_12), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_12),
.up_tx_rate (up_tx_rate_12), .up_tx_rate (up_tx_rate_12),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_12), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_12),
@ -3112,6 +3286,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_13), .up_rx_rst (up_rx_rst_13),
.up_rx_user_ready (up_rx_user_ready_13), .up_rx_user_ready (up_rx_user_ready_13),
.up_rx_rst_done (up_rx_rst_done_13), .up_rx_rst_done (up_rx_rst_done_13),
.up_rx_prbssel (up_rx_prbssel_13),
.up_rx_prbscntreset (up_rx_prbscntreset_13),
.up_rx_prbserr (up_rx_prbserr_13),
.up_rx_prbslocked (up_rx_prbslocked_13),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_13), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_13),
.up_rx_rate (up_rx_rate_13), .up_rx_rate (up_rx_rate_13),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_13), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_13),
@ -3126,6 +3304,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_13), .up_tx_rst (up_tx_rst_13),
.up_tx_user_ready (up_tx_user_ready_13), .up_tx_user_ready (up_tx_user_ready_13),
.up_tx_rst_done (up_tx_rst_done_13), .up_tx_rst_done (up_tx_rst_done_13),
.up_tx_prbsforceerr (up_tx_prbsforceerr_13),
.up_tx_prbssel (up_tx_prbssel_13),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_13), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_13),
.up_tx_rate (up_tx_rate_13), .up_tx_rate (up_tx_rate_13),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_13), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_13),
@ -3242,6 +3422,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_14), .up_rx_rst (up_rx_rst_14),
.up_rx_user_ready (up_rx_user_ready_14), .up_rx_user_ready (up_rx_user_ready_14),
.up_rx_rst_done (up_rx_rst_done_14), .up_rx_rst_done (up_rx_rst_done_14),
.up_rx_prbssel (up_rx_prbssel_14),
.up_rx_prbscntreset (up_rx_prbscntreset_14),
.up_rx_prbserr (up_rx_prbserr_14),
.up_rx_prbslocked (up_rx_prbslocked_14),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_14), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_14),
.up_rx_rate (up_rx_rate_14), .up_rx_rate (up_rx_rate_14),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_14), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_14),
@ -3256,6 +3440,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_14), .up_tx_rst (up_tx_rst_14),
.up_tx_user_ready (up_tx_user_ready_14), .up_tx_user_ready (up_tx_user_ready_14),
.up_tx_rst_done (up_tx_rst_done_14), .up_tx_rst_done (up_tx_rst_done_14),
.up_tx_prbsforceerr (up_tx_prbsforceerr_14),
.up_tx_prbssel (up_tx_prbssel_14),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_14), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_14),
.up_tx_rate (up_tx_rate_14), .up_tx_rate (up_tx_rate_14),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_14), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_14),
@ -3372,6 +3558,10 @@ module util_adxcvr #(
.up_rx_rst (up_rx_rst_15), .up_rx_rst (up_rx_rst_15),
.up_rx_user_ready (up_rx_user_ready_15), .up_rx_user_ready (up_rx_user_ready_15),
.up_rx_rst_done (up_rx_rst_done_15), .up_rx_rst_done (up_rx_rst_done_15),
.up_rx_prbssel (up_rx_prbssel_15),
.up_rx_prbscntreset (up_rx_prbscntreset_15),
.up_rx_prbserr (up_rx_prbserr_15),
.up_rx_prbslocked (up_rx_prbslocked_15),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_15), .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_15),
.up_rx_rate (up_rx_rate_15), .up_rx_rate (up_rx_rate_15),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_15), .up_rx_sys_clk_sel (up_rx_sys_clk_sel_15),
@ -3386,6 +3576,8 @@ module util_adxcvr #(
.up_tx_rst (up_tx_rst_15), .up_tx_rst (up_tx_rst_15),
.up_tx_user_ready (up_tx_user_ready_15), .up_tx_user_ready (up_tx_user_ready_15),
.up_tx_rst_done (up_tx_rst_done_15), .up_tx_rst_done (up_tx_rst_done_15),
.up_tx_prbsforceerr (up_tx_prbsforceerr_15),
.up_tx_prbssel (up_tx_prbssel_15),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_15), .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_15),
.up_tx_rate (up_tx_rate_15), .up_tx_rate (up_tx_rate_15),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_15), .up_tx_sys_clk_sel (up_tx_sys_clk_sel_15),

16
library/xilinx/util_adxcvr/util_adxcvr_constr.xdc
View File

@ -9,3 +9,19 @@ set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && I
set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}]
# sync bits i_sync_bits_tx_prbs_in
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_tx_prbs_in* && IS_SEQUENTIAL}
]
# sync bits i_sync_bits_rx_prbs_in
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_rx_prbs_in* && IS_SEQUENTIAL}
]
# sync bits i_sync_bits_rx_prbs_out
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_rx_prbs_out* && IS_SEQUENTIAL}]

10
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
View File

@ -16,6 +16,10 @@ adi_ip_properties_lite util_adxcvr
adi_ip_bd util_adxcvr "bd/bd.tcl" adi_ip_bd util_adxcvr "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
ipx::remove_all_bus_interface [ipx::current_core] ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
@ -173,6 +177,10 @@ for {set n 0} {$n < 16} {incr n} {
"rst up_rx_rst_${n} "\ "rst up_rx_rst_${n} "\
"user_ready up_rx_user_ready_${n} "\ "user_ready up_rx_user_ready_${n} "\
"rst_done up_rx_rst_done_${n} "\ "rst_done up_rx_rst_done_${n} "\
"prbssel up_rx_prbssel_${n} "\
"prbscntreset up_rx_prbscntreset_${n}"\
"prbserr up_rx_prbserr_${n} "\
"prbslocked up_rx_prbslocked_${n} "\
"lpm_dfe_n up_rx_lpm_dfe_n_${n} "\ "lpm_dfe_n up_rx_lpm_dfe_n_${n} "\
"rate up_rx_rate_${n} "\ "rate up_rx_rate_${n} "\
"sys_clk_sel up_rx_sys_clk_sel_${n} "\ "sys_clk_sel up_rx_sys_clk_sel_${n} "\
@ -189,6 +197,8 @@ for {set n 0} {$n < 16} {incr n} {
"rst up_tx_rst_${n} "\ "rst up_tx_rst_${n} "\
"user_ready up_tx_user_ready_${n} "\ "user_ready up_tx_user_ready_${n} "\
"rst_done up_tx_rst_done_${n} "\ "rst_done up_tx_rst_done_${n} "\
"prbsforceerr up_tx_prbsforceerr_${n}"\
"prbssel up_tx_prbssel_${n} "\
"lpm_dfe_n up_tx_lpm_dfe_n_${n} "\ "lpm_dfe_n up_tx_lpm_dfe_n_${n} "\
"rate up_tx_rate_${n} "\ "rate up_tx_rate_${n} "\
"sys_clk_sel up_tx_sys_clk_sel_${n} "\ "sys_clk_sel up_tx_sys_clk_sel_${n} "\

103
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -134,6 +134,10 @@ module util_adxcvr_xch #(
input up_rx_rst, input up_rx_rst,
input up_rx_user_ready, input up_rx_user_ready,
output up_rx_rst_done, output up_rx_rst_done,
input [ 3:0] up_rx_prbssel,
input up_rx_prbscntreset,
output up_rx_prbserr,
output up_rx_prbslocked,
input up_rx_lpm_dfe_n, input up_rx_lpm_dfe_n,
input [ 2:0] up_rx_rate, input [ 2:0] up_rx_rate,
input [ 1:0] up_rx_sys_clk_sel, input [ 1:0] up_rx_sys_clk_sel,
@ -148,6 +152,8 @@ module util_adxcvr_xch #(
input up_tx_rst, input up_tx_rst,
input up_tx_user_ready, input up_tx_user_ready,
output up_tx_rst_done, output up_tx_rst_done,
input up_tx_prbsforceerr,
input [ 3:0] up_tx_prbssel,
input up_tx_lpm_dfe_n, input up_tx_lpm_dfe_n,
input [ 2:0] up_tx_rate, input [ 2:0] up_tx_rate,
input [ 1:0] up_tx_sys_clk_sel, input [ 1:0] up_tx_sys_clk_sel,
@ -160,7 +166,8 @@ module util_adxcvr_xch #(
input up_tx_wr, input up_tx_wr,
input [15:0] up_tx_wdata, input [15:0] up_tx_wdata,
output [15:0] up_tx_rdata, output [15:0] up_tx_rdata,
output up_tx_ready); output up_tx_ready
);
localparam GTXE2_TRANSCEIVERS = 2; localparam GTXE2_TRANSCEIVERS = 2;
localparam GTHE3_TRANSCEIVERS = 5; localparam GTHE3_TRANSCEIVERS = 5;
@ -319,6 +326,52 @@ module util_adxcvr_xch #(
tx_rate_m2 <= tx_rate_m1; tx_rate_m2 <= tx_rate_m1;
end end
// Rx PRBS interface logic
wire rx_prbscntreset;
wire rx_prbserr;
wire rx_prbslocked;
wire [ 3:0] rx_prbssel;
reg rx_prbserr_sticky = 1'b0;
sync_bits #(.NUM_OF_BITS(5)) i_sync_bits_rx_prbs_in (
.in_bits ({up_rx_prbssel,
up_rx_prbscntreset}),
.out_resetn (1'b1),
.out_clk (rx_clk),
.out_bits ({rx_prbssel,
rx_prbscntreset})
);
always @(posedge rx_clk) begin
if (rx_prbscntreset) begin
rx_prbserr_sticky <= 1'b0;
end else if (rx_prbserr) begin
rx_prbserr_sticky <= 1'b1;
end
end
sync_bits #(.NUM_OF_BITS(2)) i_sync_bits_rx_prbs_out (
.in_bits ({rx_prbslocked,
rx_prbserr_sticky}),
.out_resetn (up_rstn),
.out_clk (up_clk),
.out_bits ({up_rx_prbslocked,
up_rx_prbserr})
);
// Tx PRBS interface logic
wire tx_prbsforceerr;
wire [ 3:0] tx_prbssel;
sync_bits #(.NUM_OF_BITS(5)) i_sync_bits_tx_prbs_in (
.in_bits ({up_tx_prbssel,
up_tx_prbsforceerr}),
.out_resetn (1'b1),
.out_clk (rx_clk),
.out_bits ({tx_prbssel,
tx_prbsforceerr})
);
// instantiations // instantiations
generate generate
@ -703,9 +756,9 @@ module util_adxcvr_xch #(
.RXPHOVRDEN (1'h0), .RXPHOVRDEN (1'h0),
.RXPMARESET (1'h0), .RXPMARESET (1'h0),
.RXPOLARITY (RX_POLARITY), .RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (1'h0), .RXPRBSCNTRESET (rx_prbscntreset),
.RXPRBSERR (), .RXPRBSERR (rx_prbserr),
.RXPRBSSEL (3'h0), .RXPRBSSEL (rx_prbssel[2:0]),
.RXQPIEN (1'h0), .RXQPIEN (1'h0),
.RXRATE (rx_rate_m2), .RXRATE (rx_rate_m2),
.RXRESETDONE (rx_rst_done_s), .RXRESETDONE (rx_rst_done_s),
@ -762,8 +815,8 @@ module util_adxcvr_xch #(
.TXPOLARITY (TX_POLARITY), .TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor), .TXPOSTCURSOR (up_tx_postcursor),
.TXPOSTCURSORINV (1'h0), .TXPOSTCURSORINV (1'h0),
.TXPRBSFORCEERR (1'h0), .TXPRBSFORCEERR (tx_prbsforceerr),
.TXPRBSSEL (3'd0), .TXPRBSSEL (tx_prbssel[2:0]),
.TXPRECURSOR (up_tx_precursor), .TXPRECURSOR (up_tx_precursor),
.TXPRECURSORINV (1'h0), .TXPRECURSORINV (1'h0),
.TXQPIBIASEN (1'h0), .TXQPIBIASEN (1'h0),
@ -778,6 +831,8 @@ module util_adxcvr_xch #(
.TXUSERRDY (up_tx_user_ready), .TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_clk), .TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk)); .TXUSRCLK2 (tx_clk));
// Emulate PRBS lock
assign rx_prbslocked = ~rx_prbserr_sticky;
end end
endgenerate endgenerate
@ -1414,10 +1469,10 @@ module util_adxcvr_xch #(
.RXPMARESET (1'h0), .RXPMARESET (1'h0),
.RXPMARESETDONE (), .RXPMARESETDONE (),
.RXPOLARITY (RX_POLARITY), .RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (1'h0), .RXPRBSCNTRESET (rx_prbscntreset),
.RXPRBSERR (), .RXPRBSERR (rx_prbserr),
.RXPRBSLOCKED (), .RXPRBSLOCKED (rx_prbslocked),
.RXPRBSSEL (4'h0), .RXPRBSSEL (rx_prbssel),
.RXPRGDIVRESETDONE (), .RXPRGDIVRESETDONE (),
.RXPROGDIVRESET (1'h0), .RXPROGDIVRESET (1'h0),
.RXQPIEN (1'h0), .RXQPIEN (1'h0),
@ -1507,8 +1562,8 @@ module util_adxcvr_xch #(
.TXPOLARITY (TX_POLARITY), .TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor), .TXPOSTCURSOR (up_tx_postcursor),
.TXPOSTCURSORINV (1'h0), .TXPOSTCURSORINV (1'h0),
.TXPRBSFORCEERR (1'h0), .TXPRBSFORCEERR (tx_prbsforceerr),
.TXPRBSSEL (4'h0), .TXPRBSSEL (tx_prbssel),
.TXPRECURSOR (up_tx_precursor), .TXPRECURSOR (up_tx_precursor),
.TXPRECURSORINV (1'h0), .TXPRECURSORINV (1'h0),
.TXPRGDIVRESETDONE (), .TXPRGDIVRESETDONE (),
@ -2291,10 +2346,10 @@ module util_adxcvr_xch #(
.RXPMARESET (1'd0), .RXPMARESET (1'd0),
.RXPMARESETDONE (), .RXPMARESETDONE (),
.RXPOLARITY (RX_POLARITY), .RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (1'd0), .RXPRBSCNTRESET (rx_prbscntreset),
.RXPRBSERR (), .RXPRBSERR (rx_prbserr),
.RXPRBSLOCKED (), .RXPRBSLOCKED (rx_prbslocked),
.RXPRBSSEL (4'd0), .RXPRBSSEL (rx_prbssel),
.RXPRGDIVRESETDONE (), .RXPRGDIVRESETDONE (),
.RXPROGDIVRESET (1'd0), .RXPROGDIVRESET (1'd0),
.RXQPIEN (1'd0), .RXQPIEN (1'd0),
@ -2391,8 +2446,8 @@ module util_adxcvr_xch #(
.TXPMARESETDONE (), .TXPMARESETDONE (),
.TXPOLARITY (TX_POLARITY), .TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor), .TXPOSTCURSOR (up_tx_postcursor),
.TXPRBSFORCEERR (1'd0), .TXPRBSFORCEERR (tx_prbsforceerr),
.TXPRBSSEL (4'd0), .TXPRBSSEL (tx_prbssel),
.TXPRECURSOR (up_tx_precursor), .TXPRECURSOR (up_tx_precursor),
.TXPRGDIVRESETDONE (), .TXPRGDIVRESETDONE (),
.TXPROGDIVRESET (up_tx_rst), .TXPROGDIVRESET (up_tx_rst),
@ -3089,8 +3144,8 @@ module util_adxcvr_xch #(
.RXPLLCLKSEL (rx_pll_clk_sel_s), .RXPLLCLKSEL (rx_pll_clk_sel_s),
.RXPMARESET (1'b0), .RXPMARESET (1'b0),
.RXPOLARITY (RX_POLARITY), .RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (1'b0), .RXPRBSCNTRESET (rx_prbscntreset),
.RXPRBSSEL (4'b0000), .RXPRBSSEL (rx_prbssel),
.RXPROGDIVRESET (1'b0), .RXPROGDIVRESET (1'b0),
.RXRATE (rx_rate_m2), .RXRATE (rx_rate_m2),
.RXRATEMODE (1'b0), .RXRATEMODE (1'b0),
@ -3161,8 +3216,8 @@ module util_adxcvr_xch #(
.TXPMARESET (1'b0), .TXPMARESET (1'b0),
.TXPOLARITY (TX_POLARITY), .TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor), .TXPOSTCURSOR (up_tx_postcursor),
.TXPRBSFORCEERR (1'b0), .TXPRBSFORCEERR (tx_prbsforceerr),
.TXPRBSSEL (4'b0000), .TXPRBSSEL (tx_prbssel),
.TXPRECURSOR (up_tx_precursor), .TXPRECURSOR (up_tx_precursor),
.TXPROGDIVRESET (up_tx_rst), .TXPROGDIVRESET (up_tx_rst),
.TXRATE (tx_rate_m2), .TXRATE (tx_rate_m2),
@ -3246,8 +3301,8 @@ module util_adxcvr_xch #(
.RXPHALIGNDONE (), .RXPHALIGNDONE (),
.RXPHALIGNERR (), .RXPHALIGNERR (),
.RXPMARESETDONE (), .RXPMARESETDONE (),
.RXPRBSERR (), .RXPRBSERR (rx_prbserr),
.RXPRBSLOCKED (), .RXPRBSLOCKED (rx_prbslocked),
.RXPRGDIVRESETDONE (), .RXPRGDIVRESETDONE (),
.RXRATEDONE (), .RXRATEDONE (),
.RXRECCLKOUT (), .RXRECCLKOUT (),