prcfg: common files
Rejeesh Kutty
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a8d4c916c1
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013 (c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg (
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clk,
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// gpio
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dac_gpio_input,
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dac_gpio_output,
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adc_gpio_input,
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adc_gpio_output,
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// tx side
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dma_dac_en,
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dma_dac_dvalid,
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dma_dac_ddata,
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dma_dac_dunf,
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core_dac_en,
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core_dac_dvalid,
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core_dac_ddata,
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core_dac_dunf,
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// rx side
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core_adc_dwr,
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core_adc_dsync,
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core_adc_ddata,
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core_adc_ovf,
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dma_adc_dwr,
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dma_adc_dsync,
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dma_adc_ddata,
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dma_adc_ovf);
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input clk;
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// gpio
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input [31:0] adc_gpio_input;
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output [31:0] adc_gpio_output;
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input [31:0] dac_gpio_input;
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output [31:0] dac_gpio_output;
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// tx side
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output dma_dac_en;
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input dma_dac_dvalid;
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input [63:0] dma_dac_ddata;
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input dma_dac_dunf;
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input core_dac_en;
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output core_dac_dvalid;
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output [63:0] core_dac_ddata;
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output core_dac_dunf;
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// rx side
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input core_adc_dwr;
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input core_adc_dsync;
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input [63:0] core_adc_ddata;
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output core_adc_ovf;
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output dma_adc_dwr;
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output dma_adc_dsync;
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output [63:0] dma_adc_ddata;
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input dma_adc_ovf;
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// fmcomms2 configuration
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localparam NUM_OF_CHANNELS = 2;
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localparam ADC_ENABLE = 1;
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localparam DAC_ENABLE = 1;
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// default top
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prcfg_top # (
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.NUM_CHANNEL (NUM_OF_CHANNELS),
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.ADC_EN (ADC_ENABLE),
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.DAC_EN (DAC_ENABLE))
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i_prcfg_top (
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.clk (clk),
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.adc_gpio_input (adc_gpio_input),
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.adc_gpio_output (adc_gpio_output),
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.dac_gpio_input (dac_gpio_input),
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.dac_gpio_output (dac_gpio_output),
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.dma_dac_en (dma_dac_en),
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.dma_dac_dunf (dma_dac_dunf),
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.dma_dac_ddata (dma_dac_ddata),
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.dma_dac_dvalid (dma_dac_dvalid),
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.core_dac_en (core_dac_en),
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.core_dac_dunf (core_dac_dunf),
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.core_dac_ddata (core_dac_ddata),
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.core_dac_dvalid (core_dac_dvalid),
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.core_adc_dwr (core_adc_dwr),
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.core_adc_dsync (core_adc_dsync),
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.core_adc_ddata (core_adc_ddata),
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.core_adc_ovf (core_adc_ovf),
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.dma_adc_dwr (dma_adc_dwr),
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.dma_adc_dsync (dma_adc_dsync),
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.dma_adc_ddata (dma_adc_ddata),
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.dma_adc_ovf (dma_adc_ovf));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,16 @@
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create_pblock pb_prcfg
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add_cells_to_pblock [get_pblocks pb_prcfg] [get_cells -quiet [list i_prcfg]]
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resize_pblock [get_pblocks pb_prcfg] -add {SLICE_X90Y0:SLICE_X161Y149}
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resize_pblock [get_pblocks pb_prcfg] -add {SLICE_X90Y150:SLICE_X122Y199}
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resize_pblock [get_pblocks pb_prcfg] -add {RAMB18_X4Y0:RAMB18_X7Y59}
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resize_pblock [get_pblocks pb_prcfg] -add {RAMB18_X4Y60:RAMB18_X4Y79}
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resize_pblock [get_pblocks pb_prcfg] -add {RAMB36_X4Y0:RAMB36_X7Y29}
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resize_pblock [get_pblocks pb_prcfg] -add {DSP48_X4Y0:DSP48_X6Y59}
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resize_pblock [get_pblocks pb_prcfg] -add {DSP48_X4Y60:DSP48_X4Y79}
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set_property SNAPPING_MODE ON [get_pblocks pb_prcfg]
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set_property RESET_AFTER_RECONFIG 1 [get_pblocks pb_prcfg]
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@ -0,0 +1,106 @@
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# prcfg io
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create_bd_port -dir O clk
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create_bd_port -dir I dma_dac_en
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create_bd_port -dir O dma_dac_dvalid
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create_bd_port -dir O -from 63 -to 0 dma_dac_ddata
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create_bd_port -dir O dma_dac_dunf
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create_bd_port -dir O core_dac_en
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create_bd_port -dir I core_dac_dvalid
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create_bd_port -dir I -from 63 -to 0 core_dac_ddata
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create_bd_port -dir I core_dac_dunf
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create_bd_port -dir O core_adc_dwr
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create_bd_port -dir O core_adc_dsync
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create_bd_port -dir O -from 63 -to 0 core_adc_ddata
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create_bd_port -dir I core_adc_ovf
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create_bd_port -dir I dma_adc_dwr
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create_bd_port -dir I dma_adc_dsync
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create_bd_port -dir I -from 63 -to 0 dma_adc_ddata
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create_bd_port -dir O dma_adc_ovf
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create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in
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create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in
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create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out
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create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out
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# re-wiring
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]]
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ad_connect clk axi_ad9361/clk
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ad_connect dma_dac_en axi_ad9361_dac_dma/fifo_rd_en
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ad_connect dma_dac_dvalid axi_ad9361_dac_dma/fifo_rd_valid
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ad_connect dma_dac_ddata axi_ad9361_dac_dma/fifo_rd_dout
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ad_connect dma_dac_dunf axi_ad9361_dac_dma/fifo_rd_underflow
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ad_connect core_dac_en util_dac_unpack/dma_rd
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ad_connect core_dac_dvalid util_dac_unpack/fifo_valid
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ad_connect core_dac_ddata util_dac_unpack/dma_data
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ad_connect core_dac_dunf axi_ad9361/dac_dunf
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ad_connect up_dac_gpio_in axi_ad9361/up_dac_gpio_in
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ad_connect up_dac_gpio_out axi_ad9361/up_dac_gpio_out
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ad_connect dma_adc_dwr axi_ad9361_adc_dma/fifo_wr_en
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ad_connect dma_adc_dsync axi_ad9361_adc_dma/fifo_wr_sync
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ad_connect dma_adc_ddata axi_ad9361_adc_dma/fifo_wr_din
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ad_connect dma_adc_ovf axi_ad9361_adc_dma/fifo_wr_overflow
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ad_connect core_adc_dwr util_adc_pack/dvalid
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ad_connect core_adc_dsync util_adc_pack/dsync
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ad_connect core_adc_ddata util_adc_pack/ddata
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ad_connect core_adc_ovf axi_ad9361/adc_dovf
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ad_connect up_adc_gpio_in axi_ad9361/up_adc_gpio_in
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ad_connect up_adc_gpio_out axi_ad9361/up_adc_gpio_out
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# monitoring
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set ila_adc_core [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc_core]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_core
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc_core
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc_core
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc_core
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_core
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ad_connect clk ila_adc_core/clk
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ad_connect util_adc_pack/dvalid ila_adc_core/probe0
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ad_connect util_adc_pack/ddata ila_adc_core/probe1
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set ila_dac_core [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_dac_core]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dac_core
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_dac_core
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dac_core
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_dac_core
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_dac_core
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ad_connect clk ila_dac_core/clk
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ad_connect util_dac_unpack/fifo_valid ila_dac_core/probe0
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ad_connect util_dac_unpack/dma_data ila_dac_core/probe1
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set ila_adc_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc_dma]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_dma
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc_dma
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc_dma
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc_dma
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_dma
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ad_connect clk ila_adc_dma/clk
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ad_connect axi_ad9361_adc_dma/fifo_wr_en ila_adc_dma/probe0
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ad_connect axi_ad9361_adc_dma/fifo_wr_din ila_adc_dma/probe1
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set ila_dac_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_dac_dma]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dac_dma
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_dac_dma
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dac_dma
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_dac_dma
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_dac_dma
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ad_connect clk ila_dac_dma/clk
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ad_connect axi_ad9361_dac_dma/fifo_rd_en ila_dac_dma/probe0
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ad_connect axi_ad9361_dac_dma/fifo_rd_dout ila_dac_dma/probe1
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