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fmcadc2: Update JESD204 TPL instance 

Updated the JESD204B transport layer instance to instantiate the new TPL IP
module.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
main
Dan Hotoleanu 2021-12-03 10:57:27 +00:00 committed by hotoleanudan
parent 41525f348b
commit 13a282d9c4
4 changed files with 20 additions and 26 deletions
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24
projects/fmcadc2/common/fmcadc2_bd.tcl
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@ -1,13 +1,22 @@
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# JESD204B interface configuration parameters
set RX_NUM_OF_LANES 8
set RX_NUM_OF_CONVERTERS 1
set RX_SAMPLES_PER_FRAME 4
set RX_SAMPLE_WIDTH 16
set adc_fifo_name axi_ad9625_fifo set adc_fifo_name axi_ad9625_fifo
set adc_data_width 256 set adc_data_width 256
set adc_dma_data_width 64 set adc_dma_data_width 64
# adc peripherals # adc peripherals
ad_ip_instance axi_ad9625 axi_ad9625_core adi_tpl_jesd204_rx_create axi_ad9625_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH \
adi_axi_jesd204_rx_create axi_ad9625_jesd 8 adi_axi_jesd204_rx_create axi_ad9625_jesd 8
@ -59,17 +68,18 @@ ad_connect $sys_cpu_clk util_fmcadc2_xcvr/up_clk
# connections (adc) # connections (adc)
ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd
ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/link_clk
ad_connect rx_core_clk util_fmcadc2_xcvr/rx_out_clk_0 ad_connect rx_core_clk util_fmcadc2_xcvr/rx_out_clk_0
ad_connect axi_ad9625_jesd/rx_data_tdata axi_ad9625_core/rx_data ad_connect axi_ad9625_jesd/rx_data_tdata axi_ad9625_core/link_data
ad_connect axi_ad9625_jesd/rx_sof axi_ad9625_core/rx_sof ad_connect axi_ad9625_jesd/rx_sof axi_ad9625_core/link_sof
ad_connect axi_ad9625_jesd/rx_data_tvalid axi_ad9625_core/link_valid
ad_connect $sys_cpu_clk axi_ad9625_fifo/dma_clk ad_connect $sys_cpu_clk axi_ad9625_fifo/dma_clk
ad_connect $sys_cpu_clk axi_ad9625_dma/s_axis_aclk ad_connect $sys_cpu_clk axi_ad9625_dma/s_axis_aclk
ad_connect $sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn ad_connect $sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk ad_connect axi_ad9625_core/link_clk axi_ad9625_fifo/adc_clk
ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr ad_connect axi_ad9625_core/adc_enable_0 axi_ad9625_fifo/adc_wr
ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata ad_connect axi_ad9625_core/adc_data_0 axi_ad9625_fifo/adc_wdata
ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data

2
projects/fmcadc2/vc707/Makefile
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@ -17,9 +17,9 @@ M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_iobuf.v
LIB_DEPS += axi_ad9625
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid LIB_DEPS += axi_sysid
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/axi_jesd204_rx LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += sysid_rom LIB_DEPS += sysid_rom

2
projects/fmcadc2/zc706/Makefile
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@ -17,12 +17,12 @@ M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_iobuf.v
LIB_DEPS += axi_ad9625
LIB_DEPS += axi_clkgen LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx LIB_DEPS += axi_spdif_tx
LIB_DEPS += axi_sysid LIB_DEPS += axi_sysid
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/axi_jesd204_rx LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += sysid_rom LIB_DEPS += sysid_rom

16
projects/fmcadc2/zc706/system_project.tcl
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@ -14,19 +14,3 @@ adi_project_files fmcadc2_zc706 [list \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run fmcadc2_zc706 adi_project_run fmcadc2_zc706
ad_ip_instance ila ila_core
ad_ip_parameter ila_core CONFIG.C_MONITOR_TYPE Native
ad_ip_parameter ila_core CONFIG.C_TRIGIN_EN false
ad_ip_parameter ila_core CONFIG.C_EN_STRG_QUAL 1
ad_ip_parameter ila_core CONFIG.C_NUM_OF_PROBES 4
ad_ip_parameter ila_core CONFIG.C_PROBE0_WIDTH 1
ad_ip_parameter ila_core CONFIG.C_PROBE1_WIDTH 1
ad_ip_parameter ila_core CONFIG.C_PROBE2_WIDTH 1
ad_ip_parameter ila_core CONFIG.C_PROBE3_WIDTH 256
ad_connect axi_ad9625_core/adc_clk ila_core/clk
ad_connect axi_ad9625_core/adc_rst ila_core/probe0
ad_connect axi_ad9625_core/adc_valid ila_core/probe1
ad_connect axi_ad9625_core/rx_ready ila_core/probe2
ad_connect axi_ad9625_core/adc_data ila_core/probe3