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daq3: Use new pack/unpack infrastructure 

Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-10-04 12:41:11 +02:00 committed by Adrian Costina
parent b9958cac00
commit 1375dcfeaa
7 changed files with 60 additions and 50 deletions
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4
projects/daq3/a10gx/Makefile
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@ -16,8 +16,8 @@ LIB_DEPS += axi_ad9152
LIB_DEPS += axi_ad9680
LIB_DEPS += axi_dmac
LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
include ../../scripts/project-altera.mk

60
projects/daq3/common/daq3_bd.tcl
View File

@ -12,9 +12,11 @@ adi_axi_jesd204_tx_create axi_ad9152_jesd 4
ad_ip_instance axi_ad9152 axi_ad9152_core
ad_ip_instance util_upack axi_ad9152_upack
ad_ip_parameter axi_ad9152_upack CONFIG.CHANNEL_DATA_WIDTH 64
ad_ip_parameter axi_ad9152_upack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance util_upack2 axi_ad9152_upack { \
NUM_OF_CHANNELS 2 \
SAMPLES_PER_CHANNEL 4 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance axi_dmac axi_ad9152_dma
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_SRC 0
@ -39,9 +41,11 @@ adi_axi_jesd204_rx_create axi_ad9680_jesd 4
ad_ip_instance axi_ad9680 axi_ad9680_core
ad_ip_instance util_cpack axi_ad9680_cpack
ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64
ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance util_cpack2 axi_ad9680_cpack { \
NUM_OF_CHANNELS 2 \
SAMPLE_DATA_WIDTH 16 \
SAMPLES_PER_CHANNEL 4 \
}
ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
@ -87,13 +91,14 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_*
ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd {0 2 3 1}
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk
ad_connect axi_ad9152_jesd/tx_data_tdata axi_ad9152_core/tx_data
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk
ad_connect axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0
ad_connect axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0
ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0
ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1
ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1
ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/clk
ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_upack/reset
ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/fifo_rd_en
for {set i 0} {$i < 2} {incr i} {
ad_connect axi_ad9152_core/dac_enable_$i axi_ad9152_upack/enable_$i
ad_connect axi_ad9152_core/dac_ddata_$i axi_ad9152_upack/fifo_rd_data_$i
}
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_connect sys_cpu_clk axi_ad9152_fifo/dma_clk
@ -104,8 +109,12 @@ if {$sys_zynq == 0 || $sys_zynq == 1} {
}
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_fifo/dac_rst
ad_connect axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid
ad_connect axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data
# TODO: Add streaming AXI interface for DAC FIFO
ad_connect axi_ad9152_upack/s_axis_valid VCC
ad_connect axi_ad9152_upack/s_axis_ready axi_ad9152_fifo/dac_valid
ad_connect axi_ad9152_upack/s_axis_data axi_ad9152_fifo/dac_data
ad_connect axi_ad9152_core/dac_dunf axi_ad9152_fifo/dac_dunf
ad_connect axi_ad9152_fifo/dma_xfer_req axi_ad9152_dma/m_axis_xfer_req
ad_connect axi_ad9152_fifo/dma_ready axi_ad9152_dma/m_axis_ready
@ -119,20 +128,12 @@ ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core/rx_sof
ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_core/rx_data
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
@ -143,6 +144,15 @@ if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
}
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
for {set i 0} {$i < 2} {incr i} {
ad_connect axi_ad9680_core/adc_enable_$i axi_ad9680_cpack/enable_$i
ad_connect axi_ad9680_core/adc_data_$i axi_ad9680_cpack/fifo_wr_data_$i
}
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr

28
projects/daq3/common/daq3_qsys.tcl
View File

@ -31,11 +31,14 @@ add_connection sys_clk.clk axi_ad9152_core.s_axi_clock
# ad9152-unpack
add_instance util_ad9152_upack util_upack
set_instance_parameter_value util_ad9152_upack {CHANNEL_DATA_WIDTH} {64}
add_instance util_ad9152_upack util_upack2
set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} {2}
set_instance_parameter_value util_ad9152_upack {SAMPLES_PER_CHANNEL} {4}
set_instance_parameter_value util_ad9152_upack {SAMPLE_DATA_WIDTH} {16}
set_instance_parameter_value util_ad9152_upack {INTERFACE_TYPE} {1}
add_connection ad9152_jesd204.link_clk util_ad9152_upack.if_dac_clk
add_connection ad9152_jesd204.link_clk util_ad9152_upack.clk
add_connection ad9152_jesd204.link_reset util_ad9152_upack.reset
add_connection axi_ad9152_core.dac_ch_0 util_ad9152_upack.dac_ch_0
add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1
@ -46,9 +49,9 @@ set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9152_fifo.if_bypass
add_connection ad9152_jesd204.link_clk avl_ad9152_fifo.if_dac_clk
add_connection ad9152_jesd204.link_reset avl_ad9152_fifo.if_dac_rst
add_connection util_ad9152_upack.if_dac_valid avl_ad9152_fifo.if_dac_valid
add_connection avl_ad9152_fifo.if_dac_data util_ad9152_upack.if_dac_data
#add_connection avl_ad9152_fifo.if_dac_dunf util_ad9152_upack.if_dac_dunf
add_connection util_ad9152_upack.if_packed_fifo_rd_en avl_ad9152_fifo.if_dac_valid
add_connection avl_ad9152_fifo.if_dac_data util_ad9152_upack.if_packed_fifo_rd_data
add_connection avl_ad9152_fifo.if_dac_dunf axi_ad9152_core.if_dac_dunf
# ad9152-dma
@ -107,12 +110,13 @@ add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
# ad9680-pack
add_instance util_ad9680_cpack util_cpack
set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64}
add_instance util_ad9680_cpack util_cpack2
set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
set_instance_parameter_value util_ad9680_cpack {SAMPLES_PER_CHANNEL} {4}
set_instance_parameter_value util_ad9680_cpack {SAMPLE_DATA_WIDTH} {16}
add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
add_connection ad9680_jesd204.link_clk util_ad9680_cpack.if_adc_clk
add_connection ad9680_jesd204.link_clk util_ad9680_cpack.clk
add_connection ad9680_jesd204.link_reset util_ad9680_cpack.reset
add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
@ -125,8 +129,8 @@ set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk
add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
add_connection util_ad9680_cpack.if_packed_fifo_wr_en ad9680_adcfifo.if_adc_wr
add_connection util_ad9680_cpack.if_packed_fifo_wr_data ad9680_adcfifo.if_adc_wdata
add_connection sys_clk.clk ad9680_adcfifo.if_dma_clk
# ad9680-dma

4
projects/daq3/kcu105/Makefile
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@ -22,9 +22,9 @@ LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

4
projects/daq3/zc706/Makefile
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@ -25,9 +25,9 @@ LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adcfifo
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

6
projects/daq3/zcu102/Makefile
View File

@ -10,7 +10,6 @@ M_DEPS += ../common/daq3_bd.tcl
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
@ -21,10 +20,9 @@ LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_adcfifo
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

4
projects/daq3/zcu102/system_bd.tcl
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@ -67,9 +67,7 @@ ad_connect axi_ad9152_fifo/bypass dac_fifo_bypass
ad_connect sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn
ad_connect axi_ad9680_dma/fifo_wr_clk util_daq3_xcvr/rx_out_clk_0
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_dma/fifo_wr_din
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_dma/fifo_wr_en
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_dma/fifo_wr_sync
ad_connect axi_ad9680_cpack/packed_fifo_wr axi_ad9680_dma/fifo_wr
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi