From 1202286c3dd816205528875da42c21739ea32357 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 17 May 2017 19:28:50 +0200 Subject: [PATCH] Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen --- library/Makefile | 16 + library/jesd204/README.md | 62 +++ library/jesd204/axi_jesd204_common/Makefile | 47 +++ .../axi_jesd204_common_ip.tcl | 60 +++ .../axi_jesd204_common/jesd204_up_common.v | 293 +++++++++++++++ .../axi_jesd204_common/jesd204_up_sysref.v | 96 +++++ library/jesd204/axi_jesd204_rx/Makefile | 69 ++++ .../jesd204/axi_jesd204_rx/axi_jesd204_rx.v | 272 ++++++++++++++ .../axi_jesd204_rx/axi_jesd204_rx_constr.xdc | 111 ++++++ .../axi_jesd204_rx/axi_jesd204_rx_ip.tcl | 116 ++++++ .../axi_jesd204_rx/jesd204_up_ilas_mem.v | 94 +++++ .../jesd204/axi_jesd204_rx/jesd204_up_rx.v | 170 +++++++++ .../axi_jesd204_rx/jesd204_up_rx_lane.v | 136 +++++++ library/jesd204/axi_jesd204_tx/Makefile | 69 ++++ .../jesd204/axi_jesd204_tx/axi_jesd204_tx.v | 297 +++++++++++++++ .../axi_jesd204_tx/axi_jesd204_tx_constr.xdc | 128 +++++++ .../axi_jesd204_tx/axi_jesd204_tx_ip.tcl | 121 ++++++ .../jesd204/axi_jesd204_tx/jesd204_up_tx.v | 303 +++++++++++++++ library/jesd204/interfaces/Makefile | 49 +++ library/jesd204/interfaces/interfaces_ip.tcl | 105 ++++++ library/jesd204/jesd204_common/Makefile | 49 +++ library/jesd204/jesd204_common/eof.v | 152 ++++++++ .../jesd204_common/jesd204_common_ip.tcl | 62 +++ library/jesd204/jesd204_common/lmfc.v | 187 +++++++++ .../jesd204/jesd204_common/pipeline_stage.v | 60 +++ library/jesd204/jesd204_common/scrambler.v | 91 +++++ library/jesd204/jesd204_rx/Makefile | 67 ++++ library/jesd204/jesd204_rx/align_mux.v | 80 ++++ library/jesd204/jesd204_rx/elastic_buffer.v | 90 +++++ library/jesd204/jesd204_rx/ilas_monitor.v | 159 ++++++++ .../jesd204/jesd204_rx/jesd204_rx_constr.xdc | 52 +++ library/jesd204/jesd204_rx/jesd204_rx_ip.tcl | 134 +++++++ .../jesd204/jesd204_rx/lane_latency_monitor.v | 101 +++++ library/jesd204/jesd204_rx/rx.v | 351 +++++++++++++++++ library/jesd204/jesd204_rx/rx_cgs.v | 123 ++++++ library/jesd204/jesd204_rx/rx_ctrl.v | 176 +++++++++ library/jesd204/jesd204_rx/rx_lane.v | 261 +++++++++++++ .../jesd204/jesd204_rx_static_config/Makefile | 51 +++ .../jesd204_rx_static_config_ip.tcl | 69 ++++ .../rx_static_config.v | 78 ++++ library/jesd204/jesd204_tx/Makefile | 65 ++++ library/jesd204/jesd204_tx/ilas_cfg_static.v | 98 +++++ .../jesd204/jesd204_tx/jesd204_tx_constr.xdc | 52 +++ library/jesd204/jesd204_tx/jesd204_tx_ip.tcl | 135 +++++++ library/jesd204/jesd204_tx/tx.v | 224 +++++++++++ library/jesd204/jesd204_tx/tx_ctrl.v | 270 +++++++++++++ library/jesd204/jesd204_tx/tx_lane.v | 120 ++++++ .../jesd204/jesd204_tx_static_config/Makefile | 54 +++ .../ilas_cfg_static.v | 123 ++++++ .../jesd204_tx_static_config_ip.tcl | 85 +++++ .../tx_static_config.v | 111 ++++++ library/jesd204/scripts/jesd204.tcl | 185 +++++++++ library/jesd204/tb/.gitignore | 2 + library/jesd204/tb/axi_jesd204_rx_regmap_tb | 16 + library/jesd204/tb/axi_jesd204_rx_regmap_tb.v | 301 +++++++++++++++ library/jesd204/tb/axi_jesd204_tx_regmap_tb | 15 + library/jesd204/tb/axi_jesd204_tx_regmap_tb.v | 354 ++++++++++++++++++ library/jesd204/tb/loopback_tb | 15 + library/jesd204/tb/loopback_tb.v | 311 +++++++++++++++ library/jesd204/tb/run_tb.sh | 8 + library/jesd204/tb/rx_cgs_tb | 7 + library/jesd204/tb/rx_cgs_tb.v | 93 +++++ library/jesd204/tb/rx_ctrl_tb | 7 + library/jesd204/tb/rx_ctrl_tb.v | 112 ++++++ library/jesd204/tb/rx_lane_tb | 10 + library/jesd204/tb/rx_lane_tb.v | 104 +++++ library/jesd204/tb/rx_tb | 12 + library/jesd204/tb/rx_tb.v | 189 ++++++++++ library/jesd204/tb/scrambler_tb | 7 + library/jesd204/tb/scrambler_tb.v | 89 +++++ library/jesd204/tb/tb_base.v | 94 +++++ library/jesd204/tb/tx_ctrl_phase_tb | 7 + library/jesd204/tb/tx_ctrl_phase_tb.v | 210 +++++++++++ library/jesd204/tb/tx_tb | 9 + library/jesd204/tb/tx_tb.v | 147 ++++++++ 75 files changed, 8648 insertions(+) create mode 100644 library/jesd204/README.md create mode 100644 library/jesd204/axi_jesd204_common/Makefile create mode 100644 library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl create mode 100644 library/jesd204/axi_jesd204_common/jesd204_up_common.v create mode 100644 library/jesd204/axi_jesd204_common/jesd204_up_sysref.v create mode 100644 library/jesd204/axi_jesd204_rx/Makefile create mode 100644 library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v create mode 100644 library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc create mode 100644 library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl create mode 100644 library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v create mode 100644 library/jesd204/axi_jesd204_rx/jesd204_up_rx.v create mode 100644 library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v create mode 100644 library/jesd204/axi_jesd204_tx/Makefile create mode 100644 library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v create mode 100644 library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc create mode 100644 library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl create mode 100644 library/jesd204/axi_jesd204_tx/jesd204_up_tx.v create mode 100644 library/jesd204/interfaces/Makefile create mode 100644 library/jesd204/interfaces/interfaces_ip.tcl create mode 100644 library/jesd204/jesd204_common/Makefile create mode 100644 library/jesd204/jesd204_common/eof.v create mode 100644 library/jesd204/jesd204_common/jesd204_common_ip.tcl create mode 100644 library/jesd204/jesd204_common/lmfc.v create mode 100644 library/jesd204/jesd204_common/pipeline_stage.v create mode 100644 library/jesd204/jesd204_common/scrambler.v create mode 100644 library/jesd204/jesd204_rx/Makefile create mode 100644 library/jesd204/jesd204_rx/align_mux.v create mode 100644 library/jesd204/jesd204_rx/elastic_buffer.v create mode 100644 library/jesd204/jesd204_rx/ilas_monitor.v create mode 100644 library/jesd204/jesd204_rx/jesd204_rx_constr.xdc create mode 100644 library/jesd204/jesd204_rx/jesd204_rx_ip.tcl create mode 100644 library/jesd204/jesd204_rx/lane_latency_monitor.v create mode 100644 library/jesd204/jesd204_rx/rx.v create mode 100644 library/jesd204/jesd204_rx/rx_cgs.v create mode 100644 library/jesd204/jesd204_rx/rx_ctrl.v create mode 100644 library/jesd204/jesd204_rx/rx_lane.v create mode 100644 library/jesd204/jesd204_rx_static_config/Makefile create mode 100644 library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl create mode 100644 library/jesd204/jesd204_rx_static_config/rx_static_config.v create mode 100644 library/jesd204/jesd204_tx/Makefile create mode 100644 library/jesd204/jesd204_tx/ilas_cfg_static.v create mode 100644 library/jesd204/jesd204_tx/jesd204_tx_constr.xdc create mode 100644 library/jesd204/jesd204_tx/jesd204_tx_ip.tcl create mode 100644 library/jesd204/jesd204_tx/tx.v create mode 100644 library/jesd204/jesd204_tx/tx_ctrl.v create mode 100644 library/jesd204/jesd204_tx/tx_lane.v create mode 100644 library/jesd204/jesd204_tx_static_config/Makefile create mode 100644 library/jesd204/jesd204_tx_static_config/ilas_cfg_static.v create mode 100644 library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl create mode 100644 library/jesd204/jesd204_tx_static_config/tx_static_config.v create mode 100644 library/jesd204/scripts/jesd204.tcl create mode 100644 library/jesd204/tb/.gitignore create mode 100755 library/jesd204/tb/axi_jesd204_rx_regmap_tb create mode 100644 library/jesd204/tb/axi_jesd204_rx_regmap_tb.v create mode 100755 library/jesd204/tb/axi_jesd204_tx_regmap_tb create mode 100644 library/jesd204/tb/axi_jesd204_tx_regmap_tb.v create mode 100755 library/jesd204/tb/loopback_tb create mode 100644 library/jesd204/tb/loopback_tb.v create mode 100644 library/jesd204/tb/run_tb.sh create mode 100755 library/jesd204/tb/rx_cgs_tb create mode 100644 library/jesd204/tb/rx_cgs_tb.v create mode 100755 library/jesd204/tb/rx_ctrl_tb create mode 100644 library/jesd204/tb/rx_ctrl_tb.v create mode 100755 library/jesd204/tb/rx_lane_tb create mode 100644 library/jesd204/tb/rx_lane_tb.v create mode 100755 library/jesd204/tb/rx_tb create mode 100644 library/jesd204/tb/rx_tb.v create mode 100755 library/jesd204/tb/scrambler_tb create mode 100644 library/jesd204/tb/scrambler_tb.v create mode 100644 library/jesd204/tb/tb_base.v create mode 100755 library/jesd204/tb/tx_ctrl_phase_tb create mode 100644 library/jesd204/tb/tx_ctrl_phase_tb.v create mode 100755 library/jesd204/tb/tx_tb create mode 100644 library/jesd204/tb/tx_tb.v diff --git a/library/Makefile b/library/Makefile index b69a72058..9c6587891 100644 --- a/library/Makefile +++ b/library/Makefile @@ -55,6 +55,14 @@ clean: make -C cn0363/cn0363_dma_sequencer clean make -C cn0363/cn0363_phase_data_sync clean make -C cordic_demod clean + make -C jesd204/axi_jesd204_common clean + make -C jesd204/axi_jesd204_rx clean + make -C jesd204/axi_jesd204_tx clean + make -C jesd204/jesd204_common clean + make -C jesd204/jesd204_rx clean + make -C jesd204/jesd204_rx_static_config clean + make -C jesd204/jesd204_tx clean + make -C jesd204/jesd204_tx_static_config clean make -C spi_engine/axi_spi_engine clean make -C spi_engine/spi_engine_execution clean make -C spi_engine/spi_engine_interconnect clean @@ -142,6 +150,14 @@ lib: make -C cn0363/cn0363_dma_sequencer make -C cn0363/cn0363_phase_data_sync make -C cordic_demod + make -C jesd204/axi_jesd204_common + make -C jesd204/axi_jesd204_rx + make -C jesd204/axi_jesd204_tx + make -C jesd204/jesd204_common + make -C jesd204/jesd204_rx + make -C jesd204/jesd204_rx_static_config + make -C jesd204/jesd204_tx + make -C jesd204/jesd204_tx_static_config make -C spi_engine/axi_spi_engine make -C spi_engine/spi_engine_execution make -C spi_engine/spi_engine_interconnect diff --git a/library/jesd204/README.md b/library/jesd204/README.md new file mode 100644 index 000000000..e294f8e82 --- /dev/null +++ b/library/jesd204/README.md @@ -0,0 +1,62 @@ +# Analog Devices JESD204B HDL Support + +## Licensing + +The ADI JESD204 Core is released under the following license, which is +different than all other HDL cores in this repository. + +Please read this, and understand the freedoms and responsibilities you have by +using this source code/core. + +The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. + +This core is free software, you can use run, copy, study, change, ask questions +about and improve this core. Distribution of source, or resulting binaries +(including those inside an FPGA or ASIC) require you to release the source of +the entire project (excluding the system libraries provide by the +tools/compiler/FPGA vendor). These are the terms of the GNU General Public +License version 2 as published by the Free Software Foundation. + +This core is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License version 2 +along with this source code, and binary. If not, see +. + +Commercial licenses (with commercial support) of this JESD204 core are also +available under terms different than the General Public License. (e.g. they do +not require you to accompany any image (FPGA or ASIC) using the JESD204 core +with any corresponding source code.) For these alternate terms you must +purchase a license from Analog Devices Technology Licensing Office. Users +interested in such a license should contact jesd204-licensing@analog.com for +more information. This commercial license is sub-licensable (if you purchase +chips from Analog Devices, incorporate them into your PCB level product, and +purchase a JESD204 license, end users of your product will also have a license +to use this core in a commercial setting without releasing their source code). + +In addition, we kindly ask you to acknowledge ADI in any program, application +or publication in which you use this JESD204 HDL core. (You are not required to +do so; it is up to your common sense to decide whether you want to comply with +this request or not.) For general publications, we suggest referencing : “The +design and implementation of the JESD204 HDL Core used in this project is +copyright © 2016-2017, Analog Devices, Inc.” + +## Support + +Analog Devices will provide limited online support for anyone using the core +with Analog Devices components (ADC, DAC, Clock, etc) via +https://ez.analog.com/community/fpga under the GPL license. If you would like +deterministic support when using this core with an ADI component, please +investigate a commercial license. Using a non-ADI JESD204 device with this core +is possible under the GPL, but Analog Devices will not help with issues you may +encounter. + +## Documenation + + - [JESD204B overview](https://wiki.analog.com/resources/fpga/peripherals/jesd204) + - [Analog Devices JESD204B Transmit Peripheral](https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx) + - [Analog Devices JESD204B Receive Peripheral](https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx) + + diff --git a/library/jesd204/axi_jesd204_common/Makefile b/library/jesd204/axi_jesd204_common/Makefile new file mode 100644 index 000000000..9f762a831 --- /dev/null +++ b/library/jesd204/axi_jesd204_common/Makefile @@ -0,0 +1,47 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += axi_jesd204_common_ip.tcl +M_DEPS += jesd204_up_common.v +M_DEPS += jesd204_up_sysref.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_jesd204_common.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_jesd204_common.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_jesd204_common_ip.tcl >> axi_jesd204_common_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl b/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl new file mode 100644 index 000000000..04d7c61a4 --- /dev/null +++ b/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl @@ -0,0 +1,60 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_jesd204_common +adi_ip_files axi_jesd204_common [list \ + "jesd204_up_common.v" \ + "jesd204_up_sysref.v" \ +] + +adi_ip_properties_lite axi_jesd204_common + +set_property display_name "ADI AXI JESD204B Common Library" [ipx::current_core] +set_property description "ADI AXI JESD204B Common Library" [ipx::current_core] +set_property hide_in_gui {1} [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_common.v b/library/jesd204/axi_jesd204_common/jesd204_up_common.v new file mode 100644 index 000000000..beb535267 --- /dev/null +++ b/library/jesd204/axi_jesd204_common/jesd204_up_common.v @@ -0,0 +1,293 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_up_common # ( + parameter PCORE_VERSION = 0, + parameter PCORE_MAGIC = 0, + parameter ID = 0, + parameter NUM_LANES = 1, + parameter DATA_PATH_WIDTH = 2, + parameter MAX_OCTETS_PER_FRAME = 256, + parameter NUM_IRQS = 1, + parameter EXTRA_CFG_WIDTH = 1 +) ( + input up_clk, + input ext_resetn, + + output up_reset, + + output up_reset_synchronizer, + + input core_clk, + output core_reset, + + input [11:0] up_raddr, + output reg [31:0] up_rdata, + + input up_wreq, + input [11:0] up_waddr, + input [31:0] up_wdata, + + input [EXTRA_CFG_WIDTH-1:0] up_extra_cfg, + + input [NUM_IRQS-1:0] up_irq_trigger, + output reg irq, + + output up_cfg_is_writeable, + + output reg [NUM_LANES-1:0] core_cfg_lanes_disable, + output reg [7:0] core_cfg_beats_per_multiframe, + output reg [7:0] core_cfg_octets_per_frame, + output reg core_cfg_disable_scrambler, + output reg core_cfg_disable_char_replacement, + output reg [EXTRA_CFG_WIDTH-1:0] core_extra_cfg +); + +localparam MAX_BEATS_PER_MULTIFRAME = (MAX_OCTETS_PER_FRAME * 32) / DATA_PATH_WIDTH; + +reg [31:0] up_scratch = 32'h00000000; + +/* Reset for the register map */ +reg [2:0] up_reset_vector = 3'b111; +assign up_reset = up_reset_vector[0]; + +/* Reset signal generation for the JESD core */ +reg [4:0] core_reset_vector = 5'b11111; +assign core_reset = core_reset_vector[0]; + +/* Transfer the reset signal back to the up domain, used to keep the + * synchronizers in reset until the core is ready. This is done in order to + * prevent bogus data to propagate to the register map. */ +reg [1:0] up_reset_synchronizer_vector = 2'b11; +assign up_reset_synchronizer = up_reset_synchronizer_vector[0]; + +/* Transfer two cycles before the core comes out of reset */ +assign core_cfg_transfer_en = core_reset_vector[2] ^ core_reset_vector[1]; + +reg up_reset_core = 1'b1; + +assign up_cfg_is_writeable = up_reset_core; + +always @(posedge up_clk or negedge ext_resetn) begin + if (ext_resetn == 1'b0) begin + up_reset_vector <= 3'b111; + end else begin + up_reset_vector <= {1'b0,up_reset_vector[2:1]}; + end +end + +always @(posedge core_clk or posedge up_reset_core) begin + if (up_reset_core == 1'b1) begin + core_reset_vector <= 5'b11111; + end else begin + core_reset_vector <= {1'b0,core_reset_vector[4:1]}; + end +end + +always @(posedge up_clk or posedge up_reset_core) begin + if (up_reset_core == 1'b1) begin + up_reset_synchronizer_vector <= 2'b11; + end else begin + up_reset_synchronizer_vector <= {core_reset,up_reset_synchronizer_vector[1]}; + end +end + +always @(posedge core_clk) begin + if (core_cfg_transfer_en == 1'b1) begin + core_cfg_beats_per_multiframe <= up_cfg_beats_per_multiframe; + core_cfg_octets_per_frame <= up_cfg_octets_per_frame; + core_cfg_lanes_disable <= up_cfg_lanes_disable; + core_cfg_disable_scrambler <= up_cfg_disable_scrambler; + core_cfg_disable_char_replacement <= up_cfg_disable_char_replacement; + core_extra_cfg <= up_extra_cfg; + end +end + +/* Interupt handling */ +reg [NUM_IRQS-1:0] up_irq_enable = {NUM_IRQS{1'b0}}; +reg [NUM_IRQS-1:0] up_irq_source = 'h00; +reg [NUM_IRQS-1:0] up_irq_clear; +wire [NUM_IRQS-1:0] up_irq_pending; + +assign up_irq_pending = up_irq_source & up_irq_enable; + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + irq <= 1'b0; + end else begin + irq <= |up_irq_pending; + end +end + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_irq_source <= 'h00; + end else begin + up_irq_source <= (up_irq_source & ~up_irq_clear) | up_irq_trigger; + end +end + +reg [7:0] up_cfg_octets_per_frame = 'h00; +reg [9-DATA_PATH_WIDTH:0] up_cfg_beats_per_multiframe = 'h00; +reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}}; +reg up_cfg_disable_char_replacement = 1'b0; +reg up_cfg_disable_scrambler = 1'b0; + +wire [20:0] clk_mon_count; + +always @(*) begin + case (up_raddr) + /* Standard registers */ + 12'h000: up_rdata <= PCORE_VERSION; + 12'h001: up_rdata <= ID; + 12'h002: up_rdata <= up_scratch; + 12'h003: up_rdata <= PCORE_MAGIC; + + /* Core configuration */ + 12'h004: up_rdata <= NUM_LANES; + 12'h005: up_rdata <= DATA_PATH_WIDTH; + /* 0x06-0x0f reserved for future use */ + /* 0x10-0x1f reserved for core specific HDL configuration information */ + + /* IRQ block */ + 12'h020: up_rdata <= up_irq_enable; + 12'h021: up_rdata <= up_irq_pending; + 12'h022: up_rdata <= up_irq_source; + /* 0x23-0x30 reserved for future use */ + + /* JESD common control */ + 12'h030: up_rdata <= up_reset_core; + 12'h031: up_rdata <= up_reset_synchronizer; /* core ready */ + 12'h032: up_rdata <= {11'h00, clk_mon_count}; /* Make it 16.16 */ + /* 0x32-0x34 reserver for future use */ + + 12'h080: up_rdata <= up_cfg_lanes_disable; + /* 0x81-0x83 reserved for future lane disable bits (max 128 lanes) */ + 12'h084: up_rdata <= { + /* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */ + /* 16-23 */ up_cfg_octets_per_frame, + /* 10-15 */ 6'b000000, /* Reserved for future extensions of beats_per_multiframe */ + /* 00-09 */ up_cfg_beats_per_multiframe,{DATA_PATH_WIDTH{1'b1}} + }; + 12'h85: up_rdata <= { + /* 02-31 */ 30'h00, /* Reserved for future additions */ + /* 01 */ up_cfg_disable_char_replacement, /* Disable character replacement */ + /* 00 */ up_cfg_disable_scrambler /* Disable scrambler */ + }; + /* 0x86-0x8f reserved for future use */ + + /* 0x90-0x9f reserved for core specific configuration options */ + + default: up_rdata <= 'h00; + endcase +end + +/* IRQ pending register is write-1-to-clear */ +always @(*) begin + if (up_wreq == 1'b1 && up_waddr == 12'h21) begin + up_irq_clear <= up_wdata[NUM_IRQS-1:0]; + end else begin + up_irq_clear <= {NUM_IRQS{1'b0}}; + end +end + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_scratch <= 'h00; + up_irq_enable <= {NUM_IRQS{1'b0}}; + up_reset_core <= 1'b1; + + up_cfg_octets_per_frame <= 'h00; + up_cfg_beats_per_multiframe <= 'h00; + up_cfg_lanes_disable <= {NUM_LANES{1'b0}}; + + up_cfg_disable_char_replacement <= 1'b0; + up_cfg_disable_scrambler <= 1'b0; + end else if (up_wreq == 1'b1) begin + case (up_waddr) + /* Standard registers */ + 12'h002: up_scratch <= up_wdata; + + /* IRQ block */ + 12'h020: up_irq_enable <= up_wdata[NUM_IRQS-1:0]; + + /* JESD common control */ + 12'h030: up_reset_core <= up_wdata[0]; + + endcase + + /* + * The configuration needs to be static while the core is + * active. To enforce this writes to configuration registers + * will be ignored while the core is out of reset. + */ + if (up_cfg_is_writeable == 1'b1) begin + case (up_waddr) + 12'h080: begin + up_cfg_lanes_disable <= up_wdata[NUM_LANES-1:0]; + end + 12'h084: begin + up_cfg_octets_per_frame <= up_wdata[23:16]; + up_cfg_beats_per_multiframe <= up_wdata[9:DATA_PATH_WIDTH]; + end + 12'h085: begin + up_cfg_disable_char_replacement <= up_wdata[1]; + up_cfg_disable_scrambler <= up_wdata[0]; + end + endcase + end + end +end + +up_clock_mon #( + .TOTAL_WIDTH(21) +) i_clk_mon ( + .up_rstn(~up_reset), + .up_clk(up_clk), + .up_d_count(clk_mon_count), + .d_rst(1'b0), + .d_clk(core_clk) +); + +endmodule diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v new file mode 100644 index 000000000..81d17550a --- /dev/null +++ b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v @@ -0,0 +1,96 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_up_sysref ( + input up_clk, + input up_reset, + + input core_clk, + + input [11:0] up_raddr, + output reg [31:0] up_rdata, + + input up_wreq, + input [11:0] up_waddr, + input [31:0] up_wdata, + + input up_cfg_is_writeable, + + output reg up_cfg_sysref_oneshot, + output reg [7:0] up_cfg_lmfc_offset, + output reg up_cfg_sysref_required, + + input core_event_sysref_alignment_error +); + +reg up_status_sysref_alignment_error = 1'b0; +wire up_status_sysref_captured; + +always @(*) begin + case (up_raddr) + /* JESD SYSREF configuraton */ + 12'h040: up_rdata <= {30'h00,up_cfg_sysref_required,up_cfg_sysref_oneshot}; + 12'h041: up_rdata <= up_cfg_lmfc_offset; + default: up_rdata <= 32'h00000000; + endcase +end + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_cfg_sysref_oneshot <= 1'b0; + up_cfg_lmfc_offset <= 'h00; + up_cfg_sysref_required <= 1'b1; + end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin + case (up_waddr) + /* JESD SYSREF configuraton */ + 12'h040: begin + up_cfg_sysref_required <= up_wdata[1]; + up_cfg_sysref_oneshot <= up_wdata[0]; + end + 12'h041: up_cfg_lmfc_offset <= up_wdata[7:0]; + endcase + end +end + +endmodule diff --git a/library/jesd204/axi_jesd204_rx/Makefile b/library/jesd204/axi_jesd204_rx/Makefile new file mode 100644 index 000000000..23e8dfb55 --- /dev/null +++ b/library/jesd204/axi_jesd204_rx/Makefile @@ -0,0 +1,69 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../common/up_axi.v +M_DEPS += ../../common/up_clock_mon.v +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc +M_DEPS += axi_jesd204_rx.v +M_DEPS += axi_jesd204_rx_constr.xdc +M_DEPS += axi_jesd204_rx_ip.tcl +M_DEPS += jesd204_up_ilas_mem.v +M_DEPS += jesd204_up_rx.v +M_DEPS += jesd204_up_rx_lane.v + +M_DEPS += ../../jesd204/axi_jesd204_common/axi_jesd204_common.xpr +M_DEPS += ../../util_cdc/util_cdc.xpr + +M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all dep clean clean-all +all: dep axi_jesd204_rx.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_jesd204_rx.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_jesd204_rx_ip.tcl >> axi_jesd204_rx_ip.log 2>&1 + +dep: + make -C ../../jesd204/axi_jesd204_common/ + make -C ../../util_cdc/ + make -C ../../jesd204/interfaces/ +#################################################################################### +#################################################################################### diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v new file mode 100644 index 000000000..e1eb84a55 --- /dev/null +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v @@ -0,0 +1,272 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module axi_jesd204_rx #( + parameter ID = 0, + parameter NUM_LANES = 1 +) ( + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + input [13:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [13:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + output irq, + + input core_clk, + output core_reset, + + output [NUM_LANES-1:0] core_cfg_lanes_disable, + output [7:0] core_cfg_beats_per_multiframe, + output [7:0] core_cfg_octets_per_frame, + output core_cfg_disable_scrambler, + output core_cfg_disable_char_replacement, + output [7:0] core_cfg_lmfc_offset, + output core_cfg_sysref_oneshot, + output core_cfg_sysref_required, + output core_cfg_buffer_early_release, + output [7:0] core_cfg_buffer_delay, + + input [NUM_LANES-1:0] core_ilas_config_valid, + input [2*NUM_LANES-1:0] core_ilas_config_addr, + input [32*NUM_LANES-1:0] core_ilas_config_data, + + input core_event_sysref_alignment_error, + input core_event_sysref_edge, + + input [2:0] core_status_ctrl_state, + input [2*NUM_LANES-1:0] core_status_lane_cgs_state, + input [NUM_LANES-1:0] core_status_lane_ifs_ready, + input [14*NUM_LANES-1:0] core_status_lane_latency +); + +localparam PCORE_VERSION = 32'h00010061; // 1.00.a +localparam PCORE_MAGIC = 32'h32303452; // 204R + +/* Register interface signals */ +reg [31:0] up_rdata = 'h0; +reg up_wack = 1'b0; +reg up_rack = 1'b0; +wire up_wreq; +wire up_rreq; +wire [31:0] up_wdata; +wire [11:0] up_waddr; +wire [11:0] up_raddr; +wire [31:0] up_rdata_common; +wire [31:0] up_rdata_sysref; +wire [31:0] up_rdata_rx; + +wire [4:0] up_irq_trigger = 5'b00000; + +wire up_cfg_is_writeable; +wire up_cfg_sysref_oneshot; +wire up_cfg_sysref_required; +wire up_cfg_buffer_early_release; +wire [7:0] up_cfg_buffer_delay; +wire [7:0] up_cfg_lmfc_offset; + +wire up_reset; +wire up_reset_synchronizer; + +up_axi #( + .AXI_ADDRESS_WIDTH (14), + .ADDRESS_WIDTH (12) +) i_up_axi ( + .up_rstn(~up_reset), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack) +); + +jesd204_up_common #( + .PCORE_VERSION(PCORE_VERSION), + .PCORE_MAGIC(PCORE_MAGIC), + .ID(ID), + .NUM_LANES(NUM_LANES), + .DATA_PATH_WIDTH(2), + .NUM_IRQS(5), + .EXTRA_CFG_WIDTH(19) +) i_up_common ( + .up_clk(s_axi_aclk), + .ext_resetn(s_axi_aresetn), + + .up_reset(up_reset), + .up_reset_synchronizer(up_reset_synchronizer), + + .core_clk(core_clk), + .core_reset(core_reset), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_common), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_irq_trigger(up_irq_trigger), + .irq(irq), + + .core_cfg_beats_per_multiframe(core_cfg_beats_per_multiframe), + .core_cfg_octets_per_frame(core_cfg_octets_per_frame), + .core_cfg_lanes_disable(core_cfg_lanes_disable), + .core_cfg_disable_scrambler(core_cfg_disable_scrambler), + .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement), + + .up_extra_cfg({ + /* 18 */ up_cfg_sysref_required, + /* 17 */ up_cfg_sysref_oneshot, + /* 16 */ up_cfg_buffer_early_release, + /* 08-15 */ up_cfg_buffer_delay, + /* 00-07 */ up_cfg_lmfc_offset + }), + .core_extra_cfg({ + /* 18 */ core_cfg_sysref_required, + /* 17 */ core_cfg_sysref_oneshot, + /* 16 */ core_cfg_buffer_early_release, + /* 08-15 */ core_cfg_buffer_delay, + /* 00-07 */ core_cfg_lmfc_offset + }) +); + +jesd204_up_sysref i_up_sysref ( + .up_clk(s_axi_aclk), + .up_reset(up_reset), + + .core_clk(core_clk), + .core_event_sysref_alignment_error(), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_sysref), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_cfg_lmfc_offset(up_cfg_lmfc_offset), + .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot), + .up_cfg_sysref_required(up_cfg_sysref_required) +); + +jesd204_up_rx #( + .NUM_LANES(NUM_LANES) +) i_up_rx ( + .up_clk(s_axi_aclk), + .up_reset(up_reset), + .up_reset_synchronizer(up_reset_synchronizer), + + .core_clk(core_clk), + .core_reset(core_reset), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_rx), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_cfg_buffer_early_release(up_cfg_buffer_early_release), + .up_cfg_buffer_delay(up_cfg_buffer_delay), + + .core_status_ctrl_state(core_status_ctrl_state), + .core_status_lane_cgs_state(core_status_lane_cgs_state), + .core_status_lane_ifs_ready(core_status_lane_ifs_ready), + .core_status_lane_latency(core_status_lane_latency), + + .core_ilas_config_valid(core_ilas_config_valid), + .core_ilas_config_addr(core_ilas_config_addr), + .core_ilas_config_data(core_ilas_config_data) +); + +always @(posedge s_axi_aclk) begin + up_wack <= up_wreq; + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_rx; + end +end + +endmodule diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc new file mode 100644 index 000000000..aacb6dfce --- /dev/null +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc @@ -0,0 +1,111 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set core_clk [get_clocks -of_objects [get_ports core_clk]] + +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + +# Used for synchronizing resets with asynchronous de-assert +set_property ASYNC_REG TRUE \ + [get_cells -hier {up_reset_vector_reg*}] \ + [get_cells -hier {core_reset_vector_reg*}] \ + [get_cells -hier {up_reset_synchronizer_vector_reg*}] + +set_false_path \ + -from [get_pins {i_up_rx/i_sync_status/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_rx/i_sync_status/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_rx/i_sync_status/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_rx/i_sync_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +# Don't place them too far appart +set_max_delay -datapath_only \ + -from [get_pins {i_up_rx/i_sync_status/cdc_hold_reg[*]/C}] \ + -to [get_pins {i_up_rx/i_sync_status/out_data_reg[*]/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from $core_clk \ + -to [get_pins {i_up_rx/*i_up_rx_lane/i_sync_status_ready/cdc_sync_stage1_reg*/D}] + +set_max_delay -datapath_only \ + -from $core_clk \ + -to [get_pins {i_up_rx/*i_up_rx_lane/up_status_latency_reg[*]/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from $core_clk \ + -to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_sync_ilas_ready/cdc_sync_stage1_reg[0]/D}] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/*mem_reg*/CLK}] \ + -to [get_pins {up_rdata_reg[*]/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from [get_pins {i_up_common/up_reset_core_reg/C}] \ + -to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}] + +set_false_path \ + -from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \ + -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[1]/D}] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_cfg_*_reg*/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $core_clk] diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl new file mode 100644 index 000000000..e6ce1205b --- /dev/null +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl @@ -0,0 +1,116 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_jesd204_rx +adi_ip_files axi_jesd204_rx [list \ + "../../xilinx/common/up_clock_mon_constr.xdc" \ + "../../common/up_axi.v" \ + "../../common/up_clock_mon.v" \ + "jesd204_up_rx.v" \ + "jesd204_up_rx_lane.v" \ + "jesd204_up_ilas_mem.v" \ + "axi_jesd204_rx_constr.xdc" \ + "axi_jesd204_rx.v" \ +] + +adi_ip_properties axi_jesd204_rx + +adi_ip_add_core_dependencies { \ + analog.com:user:axi_jesd204_common:1.0 \ + analog.com:user:util_cdc:1.0 \ +} + +set_property display_name "ADI JESD204B Receive AXI Interface" [ipx::current_core] +set_property description "ADI JESD204B Receive AXI Interface" [ipx::current_core] + +adi_add_bus "rx_cfg" "master" \ + "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_rx_cfg:1.0" \ + { \ + { "core_cfg_lanes_disable" "lanes_disable" } \ + { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \ + { "core_cfg_octets_per_frame" "octets_per_frame" } \ + { "core_cfg_lmfc_offset" "lmfc_offset" } \ + { "core_cfg_sysref_oneshot" "sysref_oneshot" } \ + { "core_cfg_sysref_required" "sysref_required" } \ + { "core_cfg_buffer_early_release" "buffer_early_release" } \ + { "core_cfg_buffer_delay" "buffer_delay" } \ + { "core_cfg_disable_char_replacement" "disable_char_replacement" } \ + { "core_cfg_disable_scrambler" "disable_scrambler" } \ + } + +adi_add_bus "rx_ilas_config" "slave" \ + "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_rx_ilas_config:1.0" \ + { \ + { "core_ilas_config_valid" "valid" } \ + { "core_ilas_config_addr" "addr" } \ + { "core_ilas_config_data" "data" } \ + } + +adi_add_bus "rx_event" "slave" \ + "analog.com:interface:jesd204_rx_event_rtl:1.0" \ + "analog.com:interface:jesd204_rx_event:1.0" \ + { \ + { "core_event_sysref_alignment_error" "sysref_alignment_error" } \ + { "core_event_sysref_edge" "sysref_edge" } \ + } + +adi_add_bus "rx_status" "slave" \ + "analog.com:interface:jesd204_rx_status_rtl:1.0" \ + "analog.com:interface:jesd204_rx_status:1.0" \ + { \ + { "core_status_ctrl_state" "ctrl_state" } \ + { "core_status_lane_cgs_state" "lane_cgs_state" } \ + { "core_status_lane_ifs_ready" "lane_ifs_ready" } \ + { "core_status_lane_latency" "lane_latency" } \ + } + +adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \ + "core_reset" "master" + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v new file mode 100644 index 000000000..913e328f7 --- /dev/null +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v @@ -0,0 +1,94 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_up_ilas_mem ( + input up_clk, + + input [1:0] up_raddr, + output [31:0] up_rdata, + + input core_clk, + input core_reset, + + input core_ilas_config_valid, + input [1:0] core_ilas_config_addr, + input [31:0] core_ilas_config_data, + + output up_ilas_ready +); + +reg [3:0] mem[0:31]; +reg core_ilas_captured = 1'b0; + +sync_bits i_sync_ilas_ready ( + .in(core_ilas_captured), + .out_resetn(1'b1), + .out_clk(up_clk), + .out(up_ilas_ready) +); + +generate +genvar i; +for (i = 0; i < 32; i = i + 1) begin: ilas_mem + assign up_rdata[i] = mem[i][~up_raddr]; + + always @(posedge core_clk) begin + if (core_ilas_config_valid == 1'b1) begin + mem[i] <= {mem[i][2:0],core_ilas_config_data[i]}; + end + end +end +endgenerate + +always @(posedge core_clk) begin + if (core_reset == 1'b1) begin + core_ilas_captured = 1'b0; + end else begin + if (core_ilas_config_valid == 1'b1 && core_ilas_config_addr == 'h3) begin + core_ilas_captured <= 1'b1; + end + end +end + +endmodule diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v new file mode 100644 index 000000000..4cac308af --- /dev/null +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v @@ -0,0 +1,170 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_up_rx # ( + parameter NUM_LANES = 1 +) ( + input up_clk, + input up_reset, + input up_reset_synchronizer, + + input [11:0] up_raddr, + output reg [31:0] up_rdata, + input up_wreq, + input [11:0] up_waddr, + input [31:0] up_wdata, + + input core_clk, + input core_reset, + + input [NUM_LANES-1:0] core_ilas_config_valid, + input [2*NUM_LANES-1:0] core_ilas_config_addr, + input [32*NUM_LANES-1:0] core_ilas_config_data, + + input [2:0] core_status_ctrl_state, + input [2*NUM_LANES-1:0] core_status_lane_cgs_state, + input [NUM_LANES-1:0] core_status_lane_ifs_ready, + input [14*NUM_LANES-1:0] core_status_lane_latency, + + input up_cfg_is_writeable, + output reg up_cfg_buffer_early_release, + output reg [7:0] up_cfg_buffer_delay +); + +localparam ELASTIC_BUFFER_SIZE = 256; + +wire [2:0] up_status_ctrl_state; +wire [2*NUM_LANES-1:0] up_status_lane_cgs_state; +wire [31:0] up_lane_rdata[0:NUM_LANES-1]; + +sync_data #( + .NUM_OF_BITS(3+NUM_LANES*(2)) +) i_sync_status ( + .in_clk(core_clk), + .in_data({ + core_status_ctrl_state, + core_status_lane_cgs_state + }), + .out_clk(up_clk), + .out_data({ + up_status_ctrl_state, + up_status_lane_cgs_state + }) +); + +localparam LANE_BASE_ADDR = 'h300 / 32; + +always @(*) begin + case (up_raddr) + /* Core configuration */ + 12'h010: up_rdata <= ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */ + + /* JESD RX configuraton */ + 12'h090: up_rdata <= { + /* 17-31 */ 15'h00, /* Reserved for future additions */ + /* 16 */ up_cfg_buffer_early_release, /* Release buffer as soon as all lanes are ready. */ + /* 10-15 */ 6'b0000, /* Reserved for future extensions of buffer_delay */ + /* 02-09 */ up_cfg_buffer_delay, /* Buffer release delay */ + /* 00-01 */ 2'b00 /* Data path width alignment */ + }; + /* 0x91-0x9f reserved for future use */ + + /* JESD RX status */ + 12'ha0: up_rdata <= { + /* 04-31 */ 28'h00, /* Reserved for future additions */ + /* 03 */ 1'b0, /* Reserved for future extensions of ctrl_state */ + /* 00-02 */ up_status_ctrl_state /* State of the internal state machine */ + }; + default: begin + if (up_raddr[11:3] >= LANE_BASE_ADDR && + up_raddr[11:3] < LANE_BASE_ADDR + NUM_LANES) begin + up_rdata <= up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR]; + end else begin + up_rdata <= 'h00; + end + end + endcase +end + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_cfg_buffer_early_release <= 1'b0; + up_cfg_buffer_delay <= 'h00; + end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin + case (up_waddr) + /* JESD RX configuraton */ + 12'h090: begin + up_cfg_buffer_early_release <= up_wdata[16]; + up_cfg_buffer_delay <= up_wdata[9:2]; + end + endcase + end +end + +genvar i; +generate for (i = 0; i < NUM_LANES; i = i + 1) begin + jesd204_up_rx_lane i_up_rx_lane ( + .up_clk(up_clk), + .up_reset_synchronizer(up_reset_synchronizer), + + .up_raddr(up_raddr[2:0]), + .up_rdata(up_lane_rdata[i]), + + .up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]), + + .core_clk(core_clk), + .core_reset(core_reset), + + .core_ilas_config_valid(core_ilas_config_valid[i]), + .core_ilas_config_addr(core_ilas_config_addr[2*i+1:2*i]), + .core_ilas_config_data(core_ilas_config_data[32*i+31:32*i]), + + .core_status_ifs_ready(core_status_lane_ifs_ready[i]), + .core_status_latency(core_status_lane_latency[14*i+13:14*i]) + ); + end + +endgenerate + +endmodule diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v new file mode 100644 index 000000000..7aceb5fce --- /dev/null +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v @@ -0,0 +1,136 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_up_rx_lane ( + input up_clk, + input up_reset_synchronizer, + + input [2:0] up_raddr, + output reg [31:0] up_rdata, + + input [1:0] up_status_cgs_state, + + input core_clk, + input core_reset, + + input core_ilas_config_valid, + input [1:0] core_ilas_config_addr, + input [31:0] core_ilas_config_data, + + input core_status_ifs_ready, + input [13:0] core_status_latency +); + +wire [1:0] up_status_ctrl_state; + +wire up_status_ifs_ready; +reg [13:0] up_status_latency = 'h00; + +wire [31:0] up_ilas_rdata; +wire up_ilas_ready; + +sync_bits #( + .NUM_OF_BITS(1) +) i_sync_status_ready ( + .in({ + core_status_ifs_ready + }), + .out_clk(up_clk), + .out_resetn(1'b1), + .out({ + up_status_ifs_ready + }) +); + +always @(posedge up_clk) begin + if (up_reset_synchronizer == 1'b1) begin + up_status_latency <= 'h00; + end else begin + if (up_status_ifs_ready == 1'b1) begin + up_status_latency <= core_status_latency; + end + end +end + +always @(*) begin + if (up_raddr[2] == 1'b1) begin + if (up_ilas_ready == 1'b1) begin + up_rdata <= up_ilas_rdata; + end else begin + up_rdata <= 'h00; + end + end else begin + case (up_raddr[1:0]) + 2'b00: up_rdata <= { + /* 06-31 */ 28'h00, /* Reserved for future use */ + /* 05 */ up_ilas_ready, + /* 04 */ up_status_ifs_ready, + /* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */ + /* 00-01 */ up_status_cgs_state + }; + 2'b01: up_rdata <= { + /* 14-31 */ 18'h00, /* Reserved for future use */ + /* 00-13 */ up_status_latency + }; + default: up_rdata <= 'h00; + endcase + end +end + +jesd204_up_ilas_mem i_ilas_mem ( + .up_clk(up_clk), + + .up_raddr(up_raddr[1:0]), + .up_rdata(up_ilas_rdata), + .up_ilas_ready(up_ilas_ready), + + .core_clk(core_clk), + .core_reset(core_reset), + + .core_ilas_config_valid(core_ilas_config_valid), + .core_ilas_config_addr(core_ilas_config_addr), + .core_ilas_config_data(core_ilas_config_data) +); + +endmodule diff --git a/library/jesd204/axi_jesd204_tx/Makefile b/library/jesd204/axi_jesd204_tx/Makefile new file mode 100644 index 000000000..1615f4afe --- /dev/null +++ b/library/jesd204/axi_jesd204_tx/Makefile @@ -0,0 +1,69 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../common/up_axi.v +M_DEPS += ../../common/up_clock_mon.v +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc +M_DEPS += axi_jesd204_tx.v +M_DEPS += axi_jesd204_tx_constr.xdc +M_DEPS += axi_jesd204_tx_ip.tcl +M_DEPS += jesd204_up_tx.v + +M_DEPS += ../../jesd204/axi_jesd204_common/axi_jesd204_common.xpr +M_DEPS += ../../util_cdc/util_cdc.xpr + +M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all dep clean clean-all +all: dep axi_jesd204_tx.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_jesd204_tx.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_jesd204_tx_ip.tcl >> axi_jesd204_tx_ip.log 2>&1 + +dep: + make -C ../../jesd204/axi_jesd204_common/ + make -C ../../util_cdc/ + make -C ../../jesd204/interfaces/ +#################################################################################### +#################################################################################### diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v new file mode 100644 index 000000000..53cc63bca --- /dev/null +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v @@ -0,0 +1,297 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + + +module axi_jesd204_tx #( + parameter ID = 0, + parameter NUM_LANES = 1 +) ( + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + input [13:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [13:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + output irq, + + input core_clk, + output core_reset, + + output [NUM_LANES-1:0] core_cfg_lanes_disable, + output [7:0] core_cfg_beats_per_multiframe, + output [7:0] core_cfg_octets_per_frame, + output [7:0] core_cfg_lmfc_offset, + output core_cfg_sysref_oneshot, + output core_cfg_sysref_required, + output core_cfg_continuous_cgs, + output core_cfg_continuous_ilas, + output core_cfg_skip_ilas, + output [7:0] core_cfg_mframes_per_ilas, + output core_cfg_disable_char_replacement, + output core_cfg_disable_scrambler, + + input core_ilas_config_rd, + input [1:0] core_ilas_config_addr, + output [32*NUM_LANES-1:0] core_ilas_config_data, + + input core_event_sysref_alignment_error, + input core_event_sysref_edge, + + output core_ctrl_manual_sync_request, + + input [1:0] core_status_state, + input core_status_sync +); + +localparam PCORE_VERSION = 32'h00010061; // 1.00.a +localparam PCORE_MAGIC = 32'h32303454; // 204T + +wire up_reset; + +/* Register interface signals */ +reg [31:0] up_rdata = 'd0; +reg up_wack = 1'b0; +reg up_rack = 1'b0; +wire up_wreq; +wire up_rreq; +wire [31:0] up_wdata; +wire [11:0] up_waddr; +wire [11:0] up_raddr; +wire [31:0] up_rdata_common; +wire [31:0] up_rdata_sysref; +wire [31:0] up_rdata_tx; + +wire up_cfg_skip_ilas; +wire up_cfg_continuous_ilas; +wire up_cfg_continuous_cgs; +wire [7:0] up_cfg_mframes_per_ilas; +wire [7:0] up_cfg_lmfc_offset; +wire up_cfg_sysref_oneshot; +wire up_cfg_sysref_required; +wire up_cfg_is_writeable; + +wire [4:0] up_irq_trigger; + +sync_event #( + .NUM_OF_EVENTS(2) +) i_sync_events ( + .in_clk(core_clk), + .in_event({ + core_event_sysref_alignment_error, + core_event_sysref_edge + }), + .out_clk(s_axi_aclk), + .out_event(up_irq_trigger[1:0]) +); + +assign up_irq_trigger[4:2] = 3'b000; + +up_axi #( + .AXI_ADDRESS_WIDTH (14), + .ADDRESS_WIDTH (12) +) i_up_axi ( + .up_rstn(~up_reset), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack) +); + +jesd204_up_common #( + .PCORE_VERSION(PCORE_VERSION), + .PCORE_MAGIC(PCORE_MAGIC), + .ID(ID), + .NUM_LANES(NUM_LANES), + .DATA_PATH_WIDTH(2), + .NUM_IRQS(5), + .EXTRA_CFG_WIDTH(21), + .MAX_OCTETS_PER_FRAME(8) +) i_up_common ( + .up_clk(s_axi_aclk), + .ext_resetn(s_axi_aresetn), + + .up_reset(up_reset), + + .up_reset_synchronizer(), + + .core_clk(core_clk), + .core_reset(core_reset), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_common), + + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_irq_trigger(up_irq_trigger), + .irq(irq), + + .core_cfg_beats_per_multiframe(core_cfg_beats_per_multiframe), + .core_cfg_octets_per_frame(core_cfg_octets_per_frame), + .core_cfg_lanes_disable(core_cfg_lanes_disable), + .core_cfg_disable_scrambler(core_cfg_disable_scrambler), + .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement), + + .up_extra_cfg({ + /* 20 */ up_cfg_sysref_required, + /* 19 */ up_cfg_sysref_oneshot, + /* 18 */ up_cfg_continuous_cgs, + /* 17 */ up_cfg_continuous_ilas, + /* 16 */ up_cfg_skip_ilas, + /* 08-15 */ up_cfg_lmfc_offset, + /* 00-07 */ up_cfg_mframes_per_ilas + }), + .core_extra_cfg({ + /* 20 */ core_cfg_sysref_required, + /* 19 */ core_cfg_sysref_oneshot, + /* 18 */ core_cfg_continuous_cgs, + /* 17 */ core_cfg_continuous_ilas, + /* 16 */ core_cfg_skip_ilas, + /* 08-15 */ core_cfg_lmfc_offset, + /* 00-07 */ core_cfg_mframes_per_ilas + }) +); + +jesd204_up_sysref i_up_sysref ( + .up_clk(s_axi_aclk), + .up_reset(up_reset), + + .core_clk(core_clk), + .core_event_sysref_alignment_error(1'b0), // FIXME + + .up_cfg_lmfc_offset(up_cfg_lmfc_offset), + .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot), + .up_cfg_sysref_required(up_cfg_sysref_required), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_sysref), + + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable) +); + +jesd204_up_tx #( + .NUM_LANES(NUM_LANES) +) i_up_tx ( + .up_clk(s_axi_aclk), + .up_reset(up_reset), + + .core_clk(core_clk), + .core_ilas_config_rd(core_ilas_config_rd), + .core_ilas_config_addr(core_ilas_config_addr), + .core_ilas_config_data(core_ilas_config_data), + + .core_ctrl_manual_sync_request(core_ctrl_manual_sync_request), + + .core_status_state(core_status_state), + .core_status_sync(core_status_sync), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_tx), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_cfg_continuous_cgs(up_cfg_continuous_cgs), + .up_cfg_continuous_ilas(up_cfg_continuous_ilas), + .up_cfg_skip_ilas(up_cfg_skip_ilas), + .up_cfg_mframes_per_ilas(up_cfg_mframes_per_ilas) +); + +always @(posedge s_axi_aclk) begin + up_wack <= up_wreq; + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_tx; + end +end + +endmodule diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc new file mode 100644 index 000000000..b3e1a53c4 --- /dev/null +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc @@ -0,0 +1,128 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set core_clk [get_clocks -of_objects [get_ports core_clk]] + +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + +# Used for synchronizing resets with asynchronous de-assert +set_property ASYNC_REG TRUE \ + [get_cells -hier {up_reset_vector_reg*}] \ + [get_cells -hier {core_reset_vector_reg*}] \ + [get_cells -hier {up_reset_synchronizer_vector_reg*}] + +set_false_path \ + -from [get_pins {i_up_tx/i_sync_state/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_sync_state/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_tx/i_sync_state/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_sync_state/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +# Don't place them too far appart +set_max_delay -datapath_only \ + -from [get_pins {i_up_tx/i_sync_state/cdc_hold_reg[*]/C}] \ + -to [get_pins {i_up_tx/i_sync_state/out_data_reg[*]/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from [get_pins {i_sync_events/out_toggle_d1_reg/C}] \ + -to [get_pins {i_sync_events/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_sync_events/in_toggle_d1_reg/C}] \ + -to [get_pins {i_sync_events/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_max_delay -datapath_only \ + -from [get_pins {i_sync_events/cdc_hold_reg[*]/C}] \ + -to [get_pins {i_sync_events/out_event_reg[*]/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from $core_clk \ + -to [get_pins {i_up_tx/i_sync_sync/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_common/up_reset_core_reg/C}] \ + -to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}] + +set_false_path \ + -from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \ + -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[1]/D}] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_cfg_*_reg*/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \ + -to [get_pins {i_up_tx/*core_ilas_config_data_reg*/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \ + -to [get_pins {i_up_tx/*core_ilas_config_data_reg*/S}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $core_clk] + +set_false_path \ + -from [get_pins {i_up_tx/i_sync_manual_sync_request/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_sync_manual_sync_request/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_tx/i_sync_manual_sync_request/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_sync_manual_sync_request/i_sync_out/cdc_sync_stage1_reg[0]/D}] diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl new file mode 100644 index 000000000..e93a4c297 --- /dev/null +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl @@ -0,0 +1,121 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_jesd204_tx +adi_ip_files axi_jesd204_tx [list \ + "../../xilinx/common/up_clock_mon_constr.xdc" \ + "../../common/up_axi.v" \ + "../../common/up_clock_mon.v" \ + "axi_jesd204_tx_constr.xdc" \ + "jesd204_up_tx.v" \ + "axi_jesd204_tx.v" \ +] + +adi_ip_properties axi_jesd204_tx + +adi_ip_add_core_dependencies { \ + analog.com:user:axi_jesd204_common:1.0 \ + analog.com:user:util_cdc:1.0 \ +} + +set_property display_name "ADI JESD204B Transmit AXI Interface" [ipx::current_core] +set_property description "ADI JESD204B Transmit AXI Interface" [ipx::current_core] + +adi_add_bus "tx_cfg" "master" \ + "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_tx_cfg:1.0" \ + { \ + { "core_cfg_lanes_disable" "lanes_disable" } \ + { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \ + { "core_cfg_octets_per_frame" "octets_per_frame" } \ + { "core_cfg_lmfc_offset" "lmfc_offset" } \ + { "core_cfg_sysref_oneshot" "sysref_oneshot" } \ + { "core_cfg_sysref_required" "sysref_required" } \ + { "core_cfg_continuous_cgs" "continuous_cgs" } \ + { "core_cfg_continuous_ilas" "continuous_ilas" } \ + { "core_cfg_skip_ilas" "skip_ilas" } \ + { "core_cfg_mframes_per_ilas" "mframes_per_ilas" } \ + { "core_cfg_disable_char_replacement" "disable_char_replacement" } \ + { "core_cfg_disable_scrambler" "disable_scrambler" } \ + } + +adi_add_bus "tx_ilas_config" "slave" \ + "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ilas_config:1.0" \ + { \ + { "core_ilas_config_rd" "rd" } \ + { "core_ilas_config_addr" "addr" } \ + { "core_ilas_config_data" "data" } \ + } + +adi_add_bus "tx_event" "slave" \ + "analog.com:interface:jesd204_tx_event_rtl:1.0" \ + "analog.com:interface:jesd204_tx_event:1.0" \ + { \ + { "core_event_sysref_alignment_error" "sysref_alignment_error" } \ + { "core_event_sysref_edge" "sysref_edge" } \ + } + +adi_add_bus "tx_status" "slave" \ + "analog.com:interface:jesd204_tx_status_rtl:1.0" \ + "analog.com:interface:jesd204_tx_status:1.0" \ + { \ + { "core_status_state" "state" } \ + { "core_status_sync" "sync" } \ + } + +adi_add_bus "tx_ctrl" "master" \ + "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ctrl:1.0" \ + { \ + { "core_ctrl_manual_sync_request" "manual_sync_request" } \ + } + +adi_add_bus_clock "core_clk" "tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl" \ + "core_reset" "master" + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v new file mode 100644 index 000000000..8b348914f --- /dev/null +++ b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v @@ -0,0 +1,303 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_up_tx # ( + parameter NUM_LANES = 1 +) ( + input up_clk, + input up_reset, + + input [11:0] up_raddr, + output reg [31:0] up_rdata, + input up_wreq, + input [11:0] up_waddr, + input [31:0] up_wdata, + + input up_cfg_is_writeable, + + output reg up_cfg_skip_ilas, + output reg up_cfg_continuous_ilas, + output reg up_cfg_continuous_cgs, + output reg [7:0] up_cfg_mframes_per_ilas, + + input core_clk, + input core_ilas_config_rd, + input [1:0] core_ilas_config_addr, + output reg [32*NUM_LANES-1:0] core_ilas_config_data, + + output core_ctrl_manual_sync_request, + + input [1:0] core_status_state, + input core_status_sync +); + +reg [31:0] up_cfg_ilas_data[0:4*NUM_LANES-1]; +reg up_ctrl_manual_sync_request = 1'b0; + +wire [1:0] up_status_state; +wire up_status_sync; + +sync_bits i_sync_sync ( + .in(core_status_sync), + .out_clk(up_clk), + .out_resetn(1'b1), + .out(up_status_sync) +); + +sync_data #( + .NUM_OF_BITS(2) +) i_sync_state ( + .in_clk(core_clk), + .in_data(core_status_state), + .out_clk(up_clk), + .out_data(up_status_state) +); + +sync_event #( + .NUM_OF_EVENTS(1), + .ASYNC_CLK(1) +) i_sync_manual_sync_request ( + .in_clk(up_clk), + .in_event(up_ctrl_manual_sync_request), + .out_clk(core_clk), + .out_event(core_ctrl_manual_sync_request) +); + +integer i; + +always @(*) begin + case (up_raddr) + /* JESD TX configuration */ + 12'h090: up_rdata <= { + /* 03-31 */ 29'h00, /* Reserved for future additions */ + /* 02 */ up_cfg_skip_ilas, /* Don't send ILAS, go directly from CGS to DATA */ + /* 01 */ up_cfg_continuous_ilas, /* Continuously send ILAS sequence */ + /* 00 */ up_cfg_continuous_cgs /* Continuously send CGS characters */ + }; + 12'h091: up_rdata <= { + /* 08-31 */ 24'h00, /* Reserved for future additions */ + /* 00-07 */ up_cfg_mframes_per_ilas /* Number of multiframes send during the ILAS */ + }; + + /* JESD TX status */ + 12'ha0: up_rdata <= { + /* 05-31 */ 23'h00, /* Reserved for future additions */ + /* 04 */ up_status_sync, /* Raw value of the SYNC pin */ + /* 02-03 */ 2'b0, /* Reserved fo future extension of the status_state field */ + /* 00-01 */ up_status_state /* State of the internal state machine (0=CGS, 1=ILAS, 2=DATA) */ + }; + default: begin + if (up_raddr[10:3] >= ('h300/32) && + up_raddr[10:3] < (('h300/32) + NUM_LANES) && + up_raddr[2] == 1'b1) begin + up_rdata <= up_cfg_ilas_data[{up_raddr[5:3],up_raddr[1:0]}]; + end else begin + up_rdata <= 32'h00000000; + end + end + endcase + +end + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_cfg_skip_ilas <= 1'b0; + up_cfg_continuous_ilas <= 1'b0; + up_cfg_continuous_cgs <= 1'b0; + up_cfg_mframes_per_ilas <= 'h3; + end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin + case (up_waddr) + /* JESD TX configuraton */ + 12'h090: begin + up_cfg_skip_ilas <= up_wdata[2]; + up_cfg_continuous_ilas <= up_wdata[1]; + up_cfg_continuous_cgs <= up_wdata[0]; + end + 12'h091: begin +// We'll enable this if we ever have a usecase +// cfg_mframes_per_ilas <= up_wdata[7:0]; + end + endcase + end +end + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_ctrl_manual_sync_request <= 1'b0; + end else if (up_wreq == 1'b1 && up_waddr == 12'h092) begin + up_ctrl_manual_sync_request <= up_wdata[0]; + end else begin + up_ctrl_manual_sync_request <= 1'b0; + end +end + +/* Shared ILAS data can be access through any lane register map window */ + +/* Shared ILAS data */ +reg [7:0] up_cfg_ilas_data_did = 'h00; +reg [3:0] up_cfg_ilas_data_bid = 'h00; +reg [4:0] up_cfg_ilas_data_l = 'h00; +reg up_cfg_ilas_data_scr = 'h00; +reg [7:0] up_cfg_ilas_data_f = 'h00; +reg [4:0] up_cfg_ilas_data_k = 'h00; +reg [7:0] up_cfg_ilas_data_m = 'h00; +reg [4:0] up_cfg_ilas_data_n = 'h00; +reg [1:0] up_cfg_ilas_data_cs = 'h00; +reg [4:0] up_cfg_ilas_data_np = 'h00; +reg [2:0] up_cfg_ilas_data_subclassv = 'h00; +reg [4:0] up_cfg_ilas_data_s = 'h00; +reg [2:0] up_cfg_ilas_data_jesdv = 'h00; +reg [4:0] up_cfg_ilas_data_cf = 'h00; +reg up_cfg_ilas_data_hd = 'h00; + +/* Per lane ILAS data */ +reg [4:0] up_cfg_ilas_data_lid[0:NUM_LANES-1]; +reg [7:0] up_cfg_ilas_data_fchk[0:NUM_LANES-1]; + +always @(*) begin + for (i = 0; i < NUM_LANES; i = i + 1) begin + up_cfg_ilas_data[0+4*i] <= { + 4'b0000, + up_cfg_ilas_data_bid, + up_cfg_ilas_data_did, + 16'h00 + }; + up_cfg_ilas_data[1+4*i] <= { + 3'b000, + up_cfg_ilas_data_k, + up_cfg_ilas_data_f, + up_cfg_ilas_data_scr, + 2'b00, + up_cfg_ilas_data_l, + 3'b000, + up_cfg_ilas_data_lid[i] + }; + up_cfg_ilas_data[2+4*i] <= { + up_cfg_ilas_data_jesdv, + up_cfg_ilas_data_s, + up_cfg_ilas_data_subclassv, + up_cfg_ilas_data_np, + up_cfg_ilas_data_cs, + 1'b0, + up_cfg_ilas_data_n, + up_cfg_ilas_data_m + }; + up_cfg_ilas_data[3+4*i] <= { + up_cfg_ilas_data_fchk[i], + 16'h0000, + up_cfg_ilas_data_hd, + 2'b00, + up_cfg_ilas_data_cf + }; + end +end + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_cfg_ilas_data_did <= 'h00; + up_cfg_ilas_data_bid <= 'h00; + up_cfg_ilas_data_scr <= 'h00; + up_cfg_ilas_data_f <= 'h00; + up_cfg_ilas_data_k <= 'h00; + up_cfg_ilas_data_m <= 'h00; + up_cfg_ilas_data_n <= 'h00; + up_cfg_ilas_data_cs <= 'h00; + up_cfg_ilas_data_np <= 'h00; + up_cfg_ilas_data_subclassv <= 'h00; + up_cfg_ilas_data_s <= 'h00; + up_cfg_ilas_data_jesdv <= 'h00; + up_cfg_ilas_data_cf <= 'h00; + up_cfg_ilas_data_hd <= 'h00; + up_cfg_ilas_data_l <= 'h00; + for (i = 0; i < NUM_LANES; i = i + 1) begin + up_cfg_ilas_data_lid[i] <= 'h00; + up_cfg_ilas_data_fchk[i] <= 'h00; + end + end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin + for (i = 0; i < NUM_LANES; i = i + 1) begin + if (up_waddr[10:2] == ('h310 / 16) + i*2) begin + case (up_waddr[1:0]) + 2'h0: begin + up_cfg_ilas_data_bid <= up_wdata[27:24]; + up_cfg_ilas_data_did <= up_wdata[23:16]; + end + 2'h1: begin + up_cfg_ilas_data_k <= up_wdata[28:24]; + up_cfg_ilas_data_f <= up_wdata[23:16]; + up_cfg_ilas_data_scr <= up_wdata[15]; + up_cfg_ilas_data_l <= up_wdata[12:8]; + up_cfg_ilas_data_lid[i] <= up_wdata[4:0]; + end + 2'h2: begin + up_cfg_ilas_data_jesdv <= up_wdata[31:29]; + up_cfg_ilas_data_s <= up_wdata[28:24]; + up_cfg_ilas_data_subclassv <= up_wdata[23:21]; + up_cfg_ilas_data_np <= up_wdata[20:16]; + up_cfg_ilas_data_cs <= up_wdata[15:14]; + up_cfg_ilas_data_n <= up_wdata[12:8]; + up_cfg_ilas_data_m <= up_wdata[7:0]; + end + 2'h3: begin + up_cfg_ilas_data_fchk[i] <= up_wdata[31:24]; + up_cfg_ilas_data_hd <= up_wdata[7]; + up_cfg_ilas_data_cf <= up_wdata[4:0]; + end + endcase + end + end + end +end + +genvar j; +generate +for (j = 0; j < NUM_LANES; j = j + 1) begin + always @(posedge core_clk) begin + if (core_ilas_config_rd == 1'b1) begin + core_ilas_config_data[j*32+31:j*32] <= up_cfg_ilas_data[core_ilas_config_addr+4*j]; + end + end +end +endgenerate + +endmodule diff --git a/library/jesd204/interfaces/Makefile b/library/jesd204/interfaces/Makefile new file mode 100644 index 000000000..bb6080e4e --- /dev/null +++ b/library/jesd204/interfaces/Makefile @@ -0,0 +1,49 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS := interfaces_ip.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl + +M_VIVADO := vivado -mode batch -source + +XML_FLIST := jesd204_tx_cfg.xml +XML_FLIST += jesd204_tx_cfg_rtl.xml +XML_FLIST += jesd204_tx_ilas_config.xml +XML_FLIST += jesd204_tx_ilas_config_rtl.xml +XML_FLIST += jesd204_tx_status.xml +XML_FLIST += jesd204_tx_status_rtl.xml +XML_FLIST += jesd204_tx_event.xml +XML_FLIST += jesd204_tx_event_rtl.xml +XML_FLIST += jesd204_tx_ctrl.xml +XML_FLIST += jesd204_tx_ctrl_rtl.xml +XML_FLIST += jesd204_rx_cfg.xml +XML_FLIST += jesd204_rx_cfg_rtl.xml +XML_FLIST += jesd204_rx_status.xml +XML_FLIST += jesd204_rx_status_rtl.xml +XML_FLIST += jesd204_rx_ilas_config.xml +XML_FLIST += jesd204_rx_ilas_config_rtl.xml +XML_FLIST += jesd204_rx_event.xml +XML_FLIST += jesd204_rx_event_rtl.xml + +M_FLIST := *.log +M_FLIST += *.jou +M_FLIST += $(XML_FLIST) + +.PHONY: all clean clean-all +all: $(XML_FLIST) + +clean:clean-all + +clean-all: + rm -rf $(M_FLIST) + +%.xml: $(M_DEPS) + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/jesd204/interfaces/interfaces_ip.tcl b/library/jesd204/interfaces/interfaces_ip.tcl new file mode 100644 index 000000000..310fad913 --- /dev/null +++ b/library/jesd204/interfaces/interfaces_ip.tcl @@ -0,0 +1,105 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +# TX interfaces + +adi_if_define "jesd204_tx_cfg" +adi_if_ports output -1 lanes_disable +adi_if_ports output 8 beats_per_multiframe +adi_if_ports output 8 octets_per_frame +adi_if_ports output 8 lmfc_offset +adi_if_ports output 1 continuous_cgs +adi_if_ports output 1 continuous_ilas +adi_if_ports output 1 skip_ilas +adi_if_ports output 8 mframes_per_ilas +adi_if_ports output 1 disable_char_replacement +adi_if_ports output 1 disable_scrambler + +adi_if_define "jesd204_tx_ilas_config" +adi_if_ports output 1 rd +adi_if_ports output 2 addr +adi_if_ports input 32 data + +adi_if_define "jesd204_tx_status" +adi_if_ports output 1 state +adi_if_ports output 1 sync + +adi_if_define "jesd204_tx_event" +adi_if_ports output 1 sysref_alignment_error +adi_if_ports output 1 sysref_edge + +adi_if_define "jesd204_tx_ctrl" +adi_if_ports output 1 manual_sync_request + +# RX interfaces + +adi_if_define "jesd204_rx_cfg" +adi_if_ports output -1 lanes_disable +adi_if_ports output 8 beats_per_multiframe +adi_if_ports output 8 octets_per_frame +adi_if_ports output 8 lmfc_offset +adi_if_ports output 1 buffer_early_release +adi_if_ports output 1 buffer_delay +adi_if_ports output 1 disable_char_replacement +adi_if_ports output 1 disable_scrambler + +adi_if_define "jesd204_rx_status" +adi_if_ports output 3 ctrl_state +adi_if_ports output -1 lane_cgs_state +adi_if_ports output -1 lane_frame_align +adi_if_ports output -1 lane_ifs_ready +adi_if_ports output -1 lane_latency_ready +adi_if_ports output -1 lane_latency + +adi_if_define "jesd204_rx_ilas_config" +adi_if_ports output -1 valid +adi_if_ports output -1 addr +adi_if_ports input -1 data + +adi_if_define "jesd204_rx_event" +adi_if_ports output 1 sysref_alignment_error +adi_if_ports output 1 sysref_edge diff --git a/library/jesd204/jesd204_common/Makefile b/library/jesd204/jesd204_common/Makefile new file mode 100644 index 000000000..96ebab577 --- /dev/null +++ b/library/jesd204/jesd204_common/Makefile @@ -0,0 +1,49 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += eof.v +M_DEPS += jesd204_common_ip.tcl +M_DEPS += lmfc.v +M_DEPS += pipeline_stage.v +M_DEPS += scrambler.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: jesd204_common.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +jesd204_common.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) jesd204_common_ip.tcl >> jesd204_common_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/jesd204/jesd204_common/eof.v b/library/jesd204/jesd204_common/eof.v new file mode 100644 index 000000000..57e64b583 --- /dev/null +++ b/library/jesd204/jesd204_common/eof.v @@ -0,0 +1,152 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_eof_generator #( + parameter DATA_PATH_WIDTH = 4, + parameter MAX_OCTETS_PER_FRAME = 256 +) ( + input clk, + input reset, + + input lmfc_edge, + + input [7:0] cfg_octets_per_frame, + input cfg_generate_eomf, + + output reg [DATA_PATH_WIDTH-1:0] sof, + output reg [DATA_PATH_WIDTH-1:0] eof, + output reg eomf +); + +localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 : + MAX_OCTETS_PER_FRAME > 64 ? 7 : + MAX_OCTETS_PER_FRAME > 32 ? 6 : + MAX_OCTETS_PER_FRAME > 16 ? 5 : + MAX_OCTETS_PER_FRAME > 8 ? 4 : + MAX_OCTETS_PER_FRAME > 4 ? 3 : + MAX_OCTETS_PER_FRAME > 2 ? 2 : 1; +localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : + DATA_PATH_WIDTH == 4 ? 2 : 1; + +reg lmfc_edge_d1 = 1'b0; + +wire beat_counter_sof; +wire beat_counter_eof; +wire small_octets_per_frame; + +always @(posedge clk) begin + if (cfg_generate_eomf == 1'b1) begin + lmfc_edge_d1 <= lmfc_edge; + end else begin + lmfc_edge_d1 <= 1'b0; + end + eomf <= lmfc_edge_d1; +end + +generate +if (CW > DPW_LOG2) begin + reg [CW-DPW_LOG2-1:0] beat_counter = 'h00; + wire [CW-DPW_LOG2-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2]; + + assign beat_counter_sof = beat_counter == 'h00; + assign beat_counter_eof = beat_counter == cfg_beats_per_frame; + assign small_octets_per_frame = cfg_beats_per_frame == 'h00; + + always @(posedge clk) begin + if (reset == 1'b1) begin + beat_counter <= 'h00; + end else if (beat_counter_eof == 1'b1) begin + beat_counter <= 'h00; + end else begin + beat_counter <= beat_counter + 1'b1; + end + end + +end else begin + assign beat_counter_sof = 1'b1; + assign beat_counter_eof = 1'b1; + assign small_octets_per_frame = 1'b1; +end +endgenerate + +function [1:0] ffs; +input [2:0] x; +begin + case (x) + 1: ffs = 0; + 2: ffs = 1; + 3: ffs = 0; + 4: ffs = 2; + 5: ffs = 0; + 6: ffs = 1; + 7: ffs = 0; + default: ffs = 0; + endcase +end +endfunction + +integer i; + +/* Only 1, 2 and multiples of 4 are supported atm */ +always @(posedge clk) begin + if (reset == 1'b1) begin + sof <= {DATA_PATH_WIDTH{1'b0}}; + eof <= {DATA_PATH_WIDTH{1'b0}}; + end else begin + sof <= {{DATA_PATH_WIDTH-1{1'b0}},beat_counter_sof}; + eof <= {beat_counter_eof,{DATA_PATH_WIDTH-1{1'b0}}}; + + if (small_octets_per_frame == 1'b1) begin + for (i = 1; i < DATA_PATH_WIDTH; i = i + 1) begin + if (cfg_octets_per_frame[ffs(i)] != 1'b1) begin + sof[i] <= 1'b1; + eof[DATA_PATH_WIDTH-1-i] <= 1'b1; + end + end + end else begin + end + end +end + +endmodule diff --git a/library/jesd204/jesd204_common/jesd204_common_ip.tcl b/library/jesd204/jesd204_common/jesd204_common_ip.tcl new file mode 100644 index 000000000..f326d6907 --- /dev/null +++ b/library/jesd204/jesd204_common/jesd204_common_ip.tcl @@ -0,0 +1,62 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create jesd204_common +adi_ip_files jesd204_common [list \ + "lmfc.v" \ + "scrambler.v" \ + "eof.v" \ + "pipeline_stage.v" \ +] + +adi_ip_properties_lite jesd204_common + +set_property display_name "ADI JESD204B Common Library" [ipx::current_core] +set_property description "ADI JESD204B Common Library" [ipx::current_core] +set_property hide_in_gui {1} [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/jesd204_common/lmfc.v b/library/jesd204/jesd204_common/lmfc.v new file mode 100644 index 000000000..104aeaf68 --- /dev/null +++ b/library/jesd204/jesd204_common/lmfc.v @@ -0,0 +1,187 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_lmfc ( + input clk, + input reset, + + input sysref, + + input [7:0] cfg_beats_per_multiframe, + input [7:0] cfg_lmfc_offset, + input cfg_sysref_oneshot, + input cfg_sysref_required, + + input clear_sysref_captured, + + output reg lmfc_edge, + output reg lmfc_clk, + output reg [7:0] lmfc_counter, + + output reg sysref_captured, + output reg sysref_edge, + output reg sysref_alignment_error +); + +reg sysref_r = 1'b0; +reg sysref_d1 = 1'b0; +reg sysref_d2 = 1'b0; +reg sysref_d3 = 1'b0; + +/* lmfc_octet_counter = lmfc_counter * (char_clock_rate / device_clock_rate) */ +reg [7:0] lmfc_counter_next = 'h00; + +reg lmfc_clk_p1 = 1'b1; + +reg lmfc_active = 1'b0; + +always @(posedge clk) begin + sysref_r <= sysref; +end + +/* + * Unfortunately setup and hold are often ignored on the sysref signal relative + * to the device clock. The device will often still work fine, just not + * deterministic. Reduce the probability that the meta-stability creeps into the + * reset of the system and causes non-reproducible issues. + */ +always @(posedge clk) begin + sysref_d1 <= sysref_r; + sysref_d2 <= sysref_d1; + sysref_d3 <= sysref_d2; +end + +always @(posedge clk) begin + if (sysref_d3 == 1'b0 && sysref_d2 == 1'b1) begin + sysref_edge <= 1'b1; + end else begin + sysref_edge <= 1'b0; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + sysref_captured <= 1'b0; + end else if (sysref_edge == 1'b1) begin + sysref_captured <= 1'b1; + end else if (clear_sysref_captured == 1'b1) begin + sysref_captured <= 1'b0; + end +end + +/* + * The configuration must be static when the core is out of reset. Otherwise + * undefined behaviour might occur. + * E.g. lmfc_counter > beats_per_multiframe + * + * To change the configuration first assert reset, then update the configuration + * setting, finally deassert reset. + */ + +always @(*) begin + if (lmfc_counter == cfg_beats_per_multiframe) begin + lmfc_counter_next <= 'h00; + end else begin + lmfc_counter_next <= lmfc_counter + 1'b1; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + lmfc_counter <= 'h00; + lmfc_active <= ~cfg_sysref_required; + end else begin + /* + * In oneshot mode only the first occurence of the + * SYSREF signal is used for alignment. + */ + if (sysref_edge == 1'b1 && + (cfg_sysref_oneshot == 1'b0 || sysref_captured == 1'b0)) begin + lmfc_counter <= cfg_lmfc_offset; + lmfc_active <= 1'b1; + end else begin + lmfc_counter <= lmfc_counter_next; + end + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + sysref_alignment_error <= 1'b0; + end else begin + /* + * Alignement error is reported regardless of oneshot mode + * setting. + */ + sysref_alignment_error <= 1'b0; + if (sysref_edge == 1'b1 && + lmfc_counter_next != cfg_lmfc_offset) begin + sysref_alignment_error <= 1'b1; + end + end +end + +always @(posedge clk) begin + if (lmfc_counter == 'h00 && lmfc_active == 1'b1) begin + lmfc_edge <= 1'b1; + end else begin + lmfc_edge <= 1'b0; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + lmfc_clk_p1 <= 1'b0; + end else if (lmfc_active == 1'b1) begin + if (lmfc_counter == cfg_beats_per_multiframe) begin + lmfc_clk_p1 <= 1'b1; + end else if (lmfc_counter == cfg_beats_per_multiframe[7:1]) begin + lmfc_clk_p1 <= 1'b0; + end + end + + lmfc_clk <= lmfc_clk_p1; +end + +endmodule diff --git a/library/jesd204/jesd204_common/pipeline_stage.v b/library/jesd204/jesd204_common/pipeline_stage.v new file mode 100644 index 000000000..3a76872b6 --- /dev/null +++ b/library/jesd204/jesd204_common/pipeline_stage.v @@ -0,0 +1,60 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module pipeline_stage #( + parameter REGISTERED = 1, + parameter WIDTH = 1 +) ( + input clk, + input [WIDTH-1:0] in, + output reg [WIDTH-1:0] out +); + +generate if (REGISTERED == 1) begin + always @(posedge clk) out <= in; +end else begin + always @(*) out <= in; +end endgenerate + +endmodule diff --git a/library/jesd204/jesd204_common/scrambler.v b/library/jesd204/jesd204_common/scrambler.v new file mode 100644 index 000000000..83b6dae63 --- /dev/null +++ b/library/jesd204/jesd204_common/scrambler.v @@ -0,0 +1,91 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_scrambler #( + parameter WIDTH = 32, + parameter DESCRAMBLE = 0 +) ( + input clk, + input reset, + + input enable, + + input [WIDTH-1:0] data_in, + output [WIDTH-1:0] data_out +); + +reg [14:0] state = 'h7f80; +reg [WIDTH-1:0] swizzle_out; +wire [WIDTH-1:0] swizzle_in; +wire [WIDTH-1:0] feedback; +wire [WIDTH-1+15:0] full_state; + +generate +genvar i; +for (i = 0; i < WIDTH / 8; i = i + 1) begin + assign swizzle_in[WIDTH-1-i*8:WIDTH-i*8-8] = data_in[i*8+7:i*8]; + assign data_out[WIDTH-1-i*8:WIDTH-i*8-8] = swizzle_out[i*8+7:i*8]; +end +endgenerate + +assign full_state = {state,DESCRAMBLE ? swizzle_in : feedback}; +assign feedback = full_state[WIDTH-1+15:15] ^ full_state[WIDTH-1+14:14] ^ swizzle_in; + +always @(*) begin + if (enable == 1'b0) begin + swizzle_out <= swizzle_in; + end else begin + swizzle_out <= feedback; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + state <= 'h7f80; + end else begin + state <= full_state[14:0]; + end +end + +endmodule diff --git a/library/jesd204/jesd204_rx/Makefile b/library/jesd204/jesd204_rx/Makefile new file mode 100644 index 000000000..6b209d822 --- /dev/null +++ b/library/jesd204/jesd204_rx/Makefile @@ -0,0 +1,67 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += align_mux.v +M_DEPS += elastic_buffer.v +M_DEPS += ilas_monitor.v +M_DEPS += jesd204_rx_constr.xdc +M_DEPS += jesd204_rx_ip.tcl +M_DEPS += lane_latency_monitor.v +M_DEPS += rx.v +M_DEPS += rx_cgs.v +M_DEPS += rx_ctrl.v +M_DEPS += rx_lane.v + +M_DEPS += ../../jesd204/jesd204_common/jesd204_common.xpr + +M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all dep clean clean-all +all: dep jesd204_rx.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +jesd204_rx.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) jesd204_rx_ip.tcl >> jesd204_rx_ip.log 2>&1 + +dep: + make -C ../../jesd204/jesd204_common/ +#################################################################################### +#################################################################################### diff --git a/library/jesd204/jesd204_rx/align_mux.v b/library/jesd204/jesd204_rx/align_mux.v new file mode 100644 index 000000000..44aa00364 --- /dev/null +++ b/library/jesd204/jesd204_rx/align_mux.v @@ -0,0 +1,80 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module align_mux #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input [1:0] align, + input [DATA_PATH_WIDTH*8-1:0] in_data, + input [DATA_PATH_WIDTH-1:0] in_charisk, + output reg [DATA_PATH_WIDTH*8-1:0] out_data, + output reg [DATA_PATH_WIDTH-1:0] out_charisk +); + +reg [DATA_PATH_WIDTH*8-1:0] in_data_d1; +reg [DATA_PATH_WIDTH-1:0] in_charisk_d1; + +always @(posedge clk) begin + in_data_d1 <= in_data; + in_charisk_d1 <= in_charisk; +end + +always @(*) begin + case (align) + 'h0: out_data <= in_data_d1; + 'h1: out_data <= {in_data[7:0],in_data_d1[31:8]}; + 'h2: out_data <= {in_data[15:0],in_data_d1[31:16]}; + 'h3: out_data <= {in_data[23:0],in_data_d1[31:24]}; + endcase + + case (align) + 'h0: out_charisk <= in_charisk_d1; + 'h1: out_charisk <= {in_charisk[0:0],in_charisk_d1[3:1]}; + 'h2: out_charisk <= {in_charisk[1:0],in_charisk_d1[3:2]}; + 'h3: out_charisk <= {in_charisk[2:0],in_charisk_d1[3:3]}; + endcase +end + +endmodule diff --git a/library/jesd204/jesd204_rx/elastic_buffer.v b/library/jesd204/jesd204_rx/elastic_buffer.v new file mode 100644 index 000000000..928b5651c --- /dev/null +++ b/library/jesd204/jesd204_rx/elastic_buffer.v @@ -0,0 +1,90 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module elastic_buffer #( + parameter WIDTH = 32, + parameter SIZE = 256 +) ( + input clk, + input reset, + + input [WIDTH-1:0] wr_data, + + output reg [WIDTH-1:0] rd_data, + + input ready_n, + input do_release_n +); + +localparam ADDR_WIDTH = SIZE > 128 ? 7 : + SIZE > 64 ? 6 : + SIZE > 32 ? 5 : + SIZE > 16 ? 4 : + SIZE > 8 ? 3 : + SIZE > 4 ? 2 : + SIZE > 2 ? 1 : 0; + +reg [ADDR_WIDTH:0] wr_addr = 'h00; +reg [ADDR_WIDTH:0] rd_addr = 'h00; +reg [WIDTH-1:0] mem[0:SIZE - 1]; + +always @(posedge clk) begin + if (ready_n == 1'b1) begin + wr_addr <= 'h00; + end else begin + mem[wr_addr] <= wr_data; + wr_addr <= wr_addr + 1'b1; + end +end + +always @(posedge clk) begin + if (do_release_n == 1'b1) begin + rd_addr <= 'h00; + end else begin + rd_addr <= rd_addr + 1'b1; + rd_data <= mem[rd_addr]; + end +end + +endmodule diff --git a/library/jesd204/jesd204_rx/ilas_monitor.v b/library/jesd204/jesd204_rx/ilas_monitor.v new file mode 100644 index 000000000..f3db40b14 --- /dev/null +++ b/library/jesd204/jesd204_rx/ilas_monitor.v @@ -0,0 +1,159 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_ilas_monitor #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input [DATA_PATH_WIDTH*8-1:0] data, + input [DATA_PATH_WIDTH-1:0] charisk28, + + output reg ilas_config_valid, + output reg [1:0] ilas_config_addr, + output reg [DATA_PATH_WIDTH*8-1:0] ilas_config_data, + + output data_ready_n +); + +reg [3:0] multi_frame_counter = 'h00; +reg [7:0] frame_counter = 'h00; +reg [7:0] length = 'h00; + +localparam STATE_ILAS = 1'b1; +localparam STATE_DATA = 1'b0; + +reg state = STATE_ILAS; +reg next_state; +reg prev_was_last = 1'b0; +reg frame_length_error = 1'b0; + +assign data_ready_n = next_state; + +always @(*) begin + next_state <= state; + if (reset == 1'b0 && prev_was_last == 1'b1) begin + if (charisk28[0] != 1'b1 || data[7:5] != 3'h0) begin + next_state <= STATE_DATA; + end + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + state <= STATE_ILAS; + end else begin + state <= next_state; + end +end + +always @(posedge clk) begin + if (reset == 1'b1 || (charisk28[3] == 1'b1 && data[31:29] == 3'h3)) begin + prev_was_last <= 1'b1; + end else begin + prev_was_last <= 1'b0; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + multi_frame_counter <= 'h00; + end else if (charisk28[0] == 1'b1 && data[7:5] == 3'h0 && state == STATE_ILAS) begin + multi_frame_counter <= multi_frame_counter + 1'b1; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + length <= 'h00; + end else if (prev_was_last == 1'b1) begin + if (length == 'h00) begin + length <= frame_counter; + end + end +end + +always @(posedge clk) begin + frame_length_error <= 1'b0; + if (prev_was_last == 1'b1) begin + if (length != 'h00 && length != frame_counter) begin + frame_length_error <= 1'b1; + end + end +end + +always @(posedge clk) begin + if (prev_was_last == 1'b1) begin + frame_counter <= 'h00; + end else begin + frame_counter <= frame_counter + 1'b1; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + ilas_config_valid <= 1'b0; + end else if (state == STATE_ILAS) begin + if (charisk28[1] == 1'b1 && data[15:13] == 3'h4) begin + ilas_config_valid <= 1'b1; + end else if (ilas_config_addr == 'h3) begin + ilas_config_valid <= 1'b0; + end + end +end + +always @(posedge clk) begin + if (ilas_config_valid == 1'b0) begin + ilas_config_addr <= 1'b0; + end else if (ilas_config_valid == 1'b1) begin + ilas_config_addr <= ilas_config_addr + 1'b1; + end +end + +always @(posedge clk) begin + ilas_config_data <= data; +end + +endmodule diff --git a/library/jesd204/jesd204_rx/jesd204_rx_constr.xdc b/library/jesd204/jesd204_rx/jesd204_rx_constr.xdc new file mode 100644 index 000000000..a753b66c3 --- /dev/null +++ b/library/jesd204/jesd204_rx/jesd204_rx_constr.xdc @@ -0,0 +1,52 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +set_property ASYNC_REG TRUE \ + [get_cells {i_lmfc/sysref_d1_reg}] \ + [get_cells {i_lmfc/sysref_d2_reg}] + +# Make sure that the device clock to sysref skew is at least somewhat +# predictable +set_property IOB TRUE \ + [get_cells {i_lmfc/sysref_r_reg}] diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl b/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl new file mode 100644 index 000000000..9a9ac8bef --- /dev/null +++ b/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl @@ -0,0 +1,134 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create jesd204_rx +adi_ip_files jesd204_rx [list \ + "rx_lane.v" \ + "rx_cgs.v" \ + "rx_ctrl.v" \ + "elastic_buffer.v" \ + "ilas_monitor.v" \ + "align_mux.v" \ + "lane_latency_monitor.v" \ + "jesd204_rx_constr.xdc" \ + "rx.v" \ +] + +adi_ip_properties_lite jesd204_rx + +adi_ip_add_core_dependencies { \ + analog.com:user:jesd204_common:1.0 \ +} + +set_property display_name "ADI JESD204 Receive" [ipx::current_core] +set_property description "ADI JESD204 Receive" [ipx::current_core] + +#adi_add_bus "rx_data" "master" \ +# "xilinx.com:interface:axis_rtl:1.0" \ +# "xilinx.com:interface:axis:1.0" \ +# { \ +# { "rx_valid" "TVALID" } \ +# { "rx_data" "TDATA" } \ +# } + +adi_add_multi_bus 8 "rx_phy" "slave" \ + "xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \ + "xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \ + [list \ + {"phy_data" "rxdata" 32} \ + { "phy_charisk" "rxcharisk" 4} \ + { "phy_disperr" "rxdisperr" 4} \ + { "phy_notintable" "rxnotintable" 4} \ + ] \ + "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})" + +adi_add_bus "rx_cfg" "slave" \ + "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_rx_cfg:1.0" \ + { \ + { "cfg_lanes_disable" "lanes_disable" } \ + { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ + { "cfg_octets_per_frame" "octets_per_frame" } \ + { "cfg_lmfc_offset" "lmfc_offset" } \ + { "cfg_sysref_oneshot" "sysref_oneshot" } \ + { "cfg_sysref_required" "sysref_required" } \ + { "cfg_buffer_delay" "buffer_delay" } \ + { "cfg_buffer_early_release" "buffer_early_release" } \ + { "cfg_disable_char_replacement" "disable_char_replacement" } \ + { "cfg_disable_scrambler" "disable_scrambler" } \ + } + +adi_add_bus "rx_status" "master" \ + "analog.com:interface:jesd204_rx_status_rtl:1.0" \ + "analog.com:interface:jesd204_rx_status:1.0" \ + { \ + { "status_ctrl_state" "ctrl_state" } \ + { "status_lane_cgs_state" "lane_cgs_state" } \ + { "status_lane_ifs_ready" "lane_ifs_ready" } \ + { "status_lane_latency" "lane_latency" } \ + } + +adi_add_bus "rx_ilas_config" "master" \ + "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_rx_ilas_config:1.0" \ + { \ + { "ilas_config_valid" "valid" } \ + { "ilas_config_addr" "addr" } \ + { "ilas_config_data" "data" } \ + } + +adi_add_bus "rx_event" "master" \ + "analog.com:interface:jesd204_rx_event_rtl:1.0" \ + "analog.com:interface:jesd204_rx_event:1.0" \ + { \ + { "event_sysref_alignment_error" "sysref_alignment_error" } \ + { "event_sysref_edge" "sysref_edge" } \ + } + +adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset" + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/jesd204_rx/lane_latency_monitor.v b/library/jesd204/jesd204_rx/lane_latency_monitor.v new file mode 100644 index 000000000..cb32868ac --- /dev/null +++ b/library/jesd204/jesd204_rx/lane_latency_monitor.v @@ -0,0 +1,101 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_lane_latency_monitor #( + parameter NUM_LANES = 1 +) ( + input clk, + input reset, + + input [NUM_LANES-1:0] lane_ready, + input [NUM_LANES*2-1:0] lane_frame_align, + + input lmfc_edge, + input [7:0] lmfc_counter, + + output [14*NUM_LANES-1:0] lane_latency, + output [NUM_LANES-1:0] lane_latency_ready +); + +reg [2:0] mframe_counter; + +reg [11:0] lane_latency_mem[0:NUM_LANES-1]; +reg [NUM_LANES-1:0] lane_captured = 'h00; + +always @(posedge clk) begin + if (reset == 1'b1) begin + mframe_counter <= 'h0; + end else if (lmfc_edge == 1'b1 && mframe_counter != 'h7) begin + mframe_counter <= mframe_counter + 1'b1; + end +end + +generate +genvar i; + +reg [7:0] lmfc_counter_d1; +reg [7:0] lmfc_counter_d2; + +always @(posedge clk) begin + lmfc_counter_d1 <= lmfc_counter; + lmfc_counter_d2 <= lmfc_counter_d1; +end + +for (i = 0; i < NUM_LANES; i = i + 1) begin + always @(posedge clk) begin + if (reset == 1'b1) begin + lane_latency_mem[i] <= 'h00; + lane_captured[i] <= 1'b0; + end else if (lane_ready[i] == 1'b1 && lane_captured[i] == 1'b0) begin + lane_latency_mem[i] <= {mframe_counter,lmfc_counter_d2}; + lane_captured[i] <= 1'b1; + end + end + + assign lane_latency[i*14+13:i*14] = {lane_latency_mem[i],lane_frame_align[i*2+1:i*2]}; + assign lane_latency_ready[i] = lane_captured[i]; +end +endgenerate + +endmodule diff --git a/library/jesd204/jesd204_rx/rx.v b/library/jesd204/jesd204_rx/rx.v new file mode 100644 index 000000000..3b6d155b7 --- /dev/null +++ b/library/jesd204/jesd204_rx/rx.v @@ -0,0 +1,351 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_rx #( + parameter NUM_LANES = 1 +) ( + input clk, + input reset, + + input [32*NUM_LANES-1:0] phy_data, + input [4*NUM_LANES-1:0] phy_charisk, + input [4*NUM_LANES-1:0] phy_notintable, + input [4*NUM_LANES-1:0] phy_disperr, + + input sysref, + output lmfc_edge, + output lmfc_clk, + + output event_sysref_alignment_error, + output event_sysref_edge, + + output sync, + + output phy_en_char_align, + + output [32*NUM_LANES-1:0] rx_data, + output rx_valid, + output [3:0] rx_eof, + output [3:0] rx_sof, + + input [NUM_LANES-1:0] cfg_lanes_disable, + input [7:0] cfg_beats_per_multiframe, + input [7:0] cfg_octets_per_frame, + input [7:0] cfg_lmfc_offset, + input cfg_sysref_required, + input cfg_sysref_oneshot, + input cfg_buffer_early_release, + input [7:0] cfg_buffer_delay, + input cfg_disable_char_replacement, + input cfg_disable_scrambler, + + output [NUM_LANES-1:0] ilas_config_valid, + output [NUM_LANES*2-1:0] ilas_config_addr, + output [NUM_LANES*32-1:0] ilas_config_data, + + output [2:0] status_ctrl_state, + output [2*NUM_LANES-1:0] status_lane_cgs_state, + output [NUM_LANES-1:0] status_lane_ifs_ready, + output [14*NUM_LANES-1:0] status_lane_latency +); + +/* + * Can be used to enable additional pipeline stages to ease timing. Usually not + * necessary. + */ +localparam CHAR_INFO_REGISTERED = 0; +localparam ALIGN_MUX_REGISTERED = 0; +localparam SCRAMBLER_REGISTERED = 0; + +/* Only 4 is supported at the moment */ +localparam DATA_PATH_WIDTH = 4; + +/* + * Maximum number of octets per multiframe for ADI JESD204 DACs is 256 (Adjust + * as necessary). Divide by data path width. + */ +localparam MAX_OCTETS_PER_FRAME = 16; +localparam MAX_OCTETS_PER_MULTIFRAME = + (MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32); +localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH; +localparam ELASTIC_BUFFER_SIZE = MAX_BEATS_PER_MULTIFRAME; + +localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 : + MAX_BEATS_PER_MULTIFRAME > 128 ? 8 : + MAX_BEATS_PER_MULTIFRAME > 64 ? 7 : + MAX_BEATS_PER_MULTIFRAME > 32 ? 6 : + MAX_BEATS_PER_MULTIFRAME > 16 ? 5 : + MAX_BEATS_PER_MULTIFRAME > 8 ? 4 : + MAX_BEATS_PER_MULTIFRAME > 4 ? 3 : + MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1; + +/* Helper for common expressions */ +localparam DW = 8*DATA_PATH_WIDTH*NUM_LANES; +localparam CW = DATA_PATH_WIDTH*NUM_LANES; + +wire [NUM_LANES-1:0] cgs_reset; +wire [NUM_LANES-1:0] cgs_ready; +wire [NUM_LANES-1:0] ifs_reset; + +reg buffer_release_n = 1'b1; +reg buffer_release_d1 = 1'b0; +wire [NUM_LANES-1:0] buffer_ready_n; + +reg eof_reset = 1'b1; + +wire [DW-1:0] phy_data_r; +wire [CW-1:0] phy_charisk_r; +wire [CW-1:0] phy_notintable_r; +wire [CW-1:0] phy_disperr_r; + +wire [DW-1:0] rx_data_s; + +wire rx_valid_s = buffer_release_d1; + +wire [7:0] lmfc_counter; +wire latency_monitor_reset; + +wire [2*NUM_LANES-1:0] frame_align; +wire [NUM_LANES-1:0] ifs_ready; + +reg buffer_release_opportunity = 1'b0; + +always @(posedge clk) begin + if (lmfc_counter == cfg_buffer_delay || + cfg_buffer_early_release == 1'b1) begin + buffer_release_opportunity <= 1'b1; + end else begin + buffer_release_opportunity <= 1'b0; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + buffer_release_n <= 1'b1; + end else begin + if (buffer_release_opportunity == 1'b1) begin + buffer_release_n <= |(buffer_ready_n & ~cfg_lanes_disable); + end + end + buffer_release_d1 <= ~buffer_release_n; + eof_reset <= buffer_release_n; +end + +pipeline_stage #( + .WIDTH(3 * CW + DW), + .REGISTERED(1) +) i_input_pipeline_stage ( + .clk(clk), + .in({ + phy_data, + phy_charisk, + phy_notintable, + phy_disperr + }), + .out({ + phy_data_r, + phy_charisk_r, + phy_notintable_r, + phy_disperr_r + }) +); + +pipeline_stage #( + .WIDTH(DW+1), + .REGISTERED(1) +) i_output_pipeline_stage ( + .clk(clk), + .in({ + rx_data_s, + rx_valid_s + }), + .out({ + rx_data, + rx_valid + }) +); + +jesd204_lmfc i_lmfc ( + .clk(clk), + .reset(reset), + + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + .cfg_lmfc_offset(cfg_lmfc_offset), + .cfg_sysref_oneshot(cfg_sysref_oneshot), + .cfg_sysref_required(cfg_sysref_required), + + .sysref(sysref), + .lmfc_edge(lmfc_edge), + .lmfc_clk(lmfc_clk), + .lmfc_counter(lmfc_counter), + + .sysref_edge(event_sysref_edge), + .sysref_alignment_error(event_sysref_alignment_error), + + .sysref_captured(), + .clear_sysref_captured(1'b0) +); + +jesd204_rx_ctrl #( + .NUM_LANES(NUM_LANES) +) i_rx_ctrl ( + .clk(clk), + .reset(reset), + + .cfg_lanes_disable(cfg_lanes_disable), + + .phy_ready(1'b1), + .phy_en_char_align(phy_en_char_align), + + .lmfc_edge(lmfc_edge), + .sync(sync), + + .latency_monitor_reset(latency_monitor_reset), + + .cgs_reset(cgs_reset), + .cgs_ready(cgs_ready), + + .ifs_reset(ifs_reset), + + .status_state(status_ctrl_state) +); + +jesd204_eof_generator #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .MAX_OCTETS_PER_FRAME(MAX_OCTETS_PER_FRAME) +) i_eof_gen ( + .clk(clk), + .reset(eof_reset), + + .lmfc_edge(lmfc_edge), + + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_generate_eomf(1'b0), + + .sof(rx_sof), + .eof(rx_eof), + .eomf() +); + +genvar i; +generate +for (i = 0; i < NUM_LANES; i = i + 1) begin + + localparam D_START = i * DATA_PATH_WIDTH*8; + localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1; + localparam C_START = i * DATA_PATH_WIDTH; + localparam C_STOP = C_START + DATA_PATH_WIDTH-1; + + jesd204_rx_lane #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .CHAR_INFO_REGISTERED(CHAR_INFO_REGISTERED), + .ALIGN_MUX_REGISTERED(ALIGN_MUX_REGISTERED), + .SCRAMBLER_REGISTERED(SCRAMBLER_REGISTERED), + .ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE) + ) i_lane ( + .clk(clk), + .reset(reset), + + .phy_data(phy_data_r[D_STOP:D_START]), + .phy_charisk(phy_charisk_r[C_STOP:C_START]), + .phy_notintable(phy_notintable_r[C_STOP:C_START]), + .phy_disperr(phy_disperr_r[C_STOP:C_START]), + + .cgs_reset(cgs_reset[i]), + .cgs_ready(cgs_ready[i]), + + .ifs_reset(ifs_reset[i]), + + .cfg_disable_scrambler(cfg_disable_scrambler), + + .rx_data(rx_data_s[D_STOP:D_START]), + + .buffer_release_n(buffer_release_n), + .buffer_ready_n(buffer_ready_n[i]), + + .ilas_config_valid(ilas_config_valid[i]), + .ilas_config_addr(ilas_config_addr[2*i+1:2*i]), + .ilas_config_data(ilas_config_data[D_STOP:D_START]), + + .status_cgs_state(status_lane_cgs_state[2*i+1:2*i]), + .status_ifs_ready(ifs_ready[i]), + .status_frame_align(frame_align[2*i+1:2*i]) + ); +end +endgenerate + +/* Delay matching based on the number of pipeline stages */ +reg [NUM_LANES-1:0] ifs_ready_d1 = 1'b0; +reg [NUM_LANES-1:0] ifs_ready_d2 = 1'b0; +reg [NUM_LANES-1:0] ifs_ready_mux; + +always @(posedge clk) begin + ifs_ready_d1 <= ifs_ready; + ifs_ready_d2 <= ifs_ready_d1; +end + +always @(*) begin + case (SCRAMBLER_REGISTERED + ALIGN_MUX_REGISTERED) + 1: ifs_ready_mux <= ifs_ready_d1; + 2: ifs_ready_mux <= ifs_ready_d2; + default: ifs_ready_mux <= ifs_ready; + endcase +end + +jesd204_lane_latency_monitor #( + .NUM_LANES(NUM_LANES) +) i_lane_latency_monitor ( + .clk(clk), + .reset(latency_monitor_reset), + + .lmfc_edge(lmfc_edge), + .lmfc_counter(lmfc_counter), + + .lane_ready(ifs_ready_mux), + .lane_frame_align(frame_align), + .lane_latency_ready(status_lane_ifs_ready), + .lane_latency(status_lane_latency) +); + +endmodule diff --git a/library/jesd204/jesd204_rx/rx_cgs.v b/library/jesd204/jesd204_rx/rx_cgs.v new file mode 100644 index 000000000..8c7def4a5 --- /dev/null +++ b/library/jesd204/jesd204_rx/rx_cgs.v @@ -0,0 +1,123 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_rx_cgs #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input [DATA_PATH_WIDTH-1:0] char_is_cgs, + input [DATA_PATH_WIDTH-1:0] char_is_error, + + output ready, + + output [1:0] status_state +); + +localparam CGS_STATE_INIT = 2'b00; +localparam CGS_STATE_CHECK = 2'b01; +localparam CGS_STATE_DATA = 2'b10; + +reg [1:0] state = CGS_STATE_INIT; +reg rdy = 1'b0; +reg [1:0] beat_error_count = 'h00; + +wire beat_is_cgs = &char_is_cgs; +wire beat_has_error = |char_is_error; +wire beat_is_all_error = &char_is_error; + +assign ready = rdy; +assign status_state = state; + +always @(posedge clk) begin + if (state == CGS_STATE_INIT) begin + beat_error_count <= 'h00; + end else begin + if (beat_has_error == 1'b1) begin + beat_error_count <= beat_error_count + 1'b1; + end else begin + beat_error_count <= 'h00; + end + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + state <= CGS_STATE_INIT; + end else begin + case (state) + CGS_STATE_INIT: begin + if (beat_is_cgs == 1'b1) begin + state <= CGS_STATE_CHECK; + end + end + CGS_STATE_CHECK: begin + if (beat_has_error == 1'b1) begin + if (beat_error_count == 'h3 || + beat_is_all_error == 1'b1) begin + state <= CGS_STATE_INIT; + end + end else begin + state <= CGS_STATE_DATA; + end + end + CGS_STATE_DATA: begin + if (beat_has_error == 1'b1) begin + state <= CGS_STATE_CHECK; + end + end + endcase + end +end + +always @(posedge clk) begin + case (state) + CGS_STATE_INIT: rdy <= 1'b0; + CGS_STATE_DATA: rdy <= 1'b1; + default: rdy <= rdy; + endcase +end + +endmodule diff --git a/library/jesd204/jesd204_rx/rx_ctrl.v b/library/jesd204/jesd204_rx/rx_ctrl.v new file mode 100644 index 000000000..f2712d026 --- /dev/null +++ b/library/jesd204/jesd204_rx/rx_ctrl.v @@ -0,0 +1,176 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_rx_ctrl #( + parameter NUM_LANES = 1 +) ( + input clk, + input reset, + + input [NUM_LANES-1:0] cfg_lanes_disable, + + input phy_ready, + + output phy_en_char_align, + + output [NUM_LANES-1:0] cgs_reset, + input [NUM_LANES-1:0] cgs_ready, + + output [NUM_LANES-1:0] ifs_reset, + + input lmfc_edge, + + output sync, + output reg latency_monitor_reset, + + output [2:0] status_state +); + +localparam STATE_RESET = 0; +localparam STATE_WAIT_FOR_PHY = 1; +localparam STATE_CGS = 2; +localparam STATE_DEGLITCH = 3; +localparam STATE_SYNCHRONIZED = 4; + +reg [2:0] state = STATE_RESET; +reg [2:0] next_state = STATE_RESET; + +reg [NUM_LANES-1:0] cgs_rst = {NUM_LANES{1'b1}}; +reg [NUM_LANES-1:0] ifs_rst = {NUM_LANES{1'b1}}; +reg sync_n = 1'b1; +reg en_align = 1'b0; +reg state_good = 1'b0; + +reg [2:0] good_counter = 'h00; +reg [9:0] deglitch_counter = 'h3ff; + +assign cgs_reset = cgs_rst; +assign ifs_reset = ifs_rst; +assign sync = sync_n; +assign phy_en_char_align = en_align; + +assign status_state = state; + +always @(posedge clk) begin + case (state) + STATE_RESET: begin + cgs_rst <= {NUM_LANES{1'b1}}; + ifs_rst <= {NUM_LANES{1'b1}}; + sync_n <= 1'b1; + latency_monitor_reset <= 1'b1; + end + STATE_CGS: begin + sync_n <= 1'b0; + cgs_rst <= cfg_lanes_disable; + end + STATE_SYNCHRONIZED: begin + if (lmfc_edge == 1'b1) begin + sync_n <= 1'b1; + ifs_rst <= cfg_lanes_disable; + latency_monitor_reset <= 1'b0; + end + end + endcase +end + +always @(posedge clk) begin + case (state) + STATE_DEGLITCH: begin + if (deglitch_counter != 'h00) begin + deglitch_counter <= deglitch_counter - 1'b1; + end + end + default: begin + deglitch_counter <= 'h3f; + end + endcase +end + +always @(*) begin + case (state) + STATE_RESET: state_good <= 1'b1; + STATE_WAIT_FOR_PHY: state_good <= phy_ready; + STATE_CGS: state_good <= &(cgs_ready | cfg_lanes_disable); + STATE_DEGLITCH: state_good <= deglitch_counter == 'h00; + STATE_SYNCHRONIZED: state_good <= 1'b1; + default: state_good <= 1'b0; + endcase +end + +always @(posedge clk) begin + if (state_good == 1'b1) begin + good_counter <= good_counter + 1'b1; + end else begin + good_counter <= 'h00; + end +end + +always @(posedge clk) begin + case (state) + STATE_CGS: en_align <= 1'b1; + default: en_align <= 1'b0; + endcase +end + +always @(*) begin + case (state) + STATE_RESET: next_state <= STATE_WAIT_FOR_PHY; + STATE_WAIT_FOR_PHY: next_state <= STATE_CGS; + STATE_CGS: next_state <= STATE_DEGLITCH; + STATE_DEGLITCH: next_state <= STATE_SYNCHRONIZED; + default: next_state <= state_good ? state : STATE_RESET; + endcase +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + state <= STATE_RESET; + end else begin + if (good_counter == 'h7) begin + state <= next_state; + end + end +end + +endmodule diff --git a/library/jesd204/jesd204_rx/rx_lane.v b/library/jesd204/jesd204_rx/rx_lane.v new file mode 100644 index 000000000..320c2c445 --- /dev/null +++ b/library/jesd204/jesd204_rx/rx_lane.v @@ -0,0 +1,261 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_rx_lane #( + parameter DATA_PATH_WIDTH = 4, + parameter CHAR_INFO_REGISTERED = 0, + parameter ALIGN_MUX_REGISTERED = 0, + parameter SCRAMBLER_REGISTERED = 0, + parameter ELASTIC_BUFFER_SIZE = 256 +) ( + input clk, + input reset, + + input [DATA_PATH_WIDTH*8-1:0] phy_data, + input [DATA_PATH_WIDTH-1:0] phy_charisk, + input [DATA_PATH_WIDTH-1:0] phy_notintable, + input [DATA_PATH_WIDTH-1:0] phy_disperr, + + input cgs_reset, + output cgs_ready, + + input ifs_reset, + + output [DATA_PATH_WIDTH*8-1:0] rx_data, + + output buffer_ready_n, + input buffer_release_n, + + input cfg_disable_scrambler, + + output ilas_config_valid, + output [1:0] ilas_config_addr, + output [DATA_PATH_WIDTH*8-1:0] ilas_config_data, + + output [1:0] status_cgs_state, + output status_ifs_ready, + output [1:0] status_frame_align +); + +wire [7:0] char[0:DATA_PATH_WIDTH-1]; +wire [DATA_PATH_WIDTH-1:0] char_is_valid; +reg [DATA_PATH_WIDTH-1:0] char_is_cgs = 1'b0; // K28.5 /K/ + +reg [DATA_PATH_WIDTH-1:0] char_is_error = 1'b0; +reg [DATA_PATH_WIDTH-1:0] charisk28 = 4'b0000; + +wire cgs_beat_is_cgs = &char_is_cgs; +wire cgs_beat_has_error = |char_is_error; + +reg ifs_ready = 1'b0; +reg [1:0] frame_align = 'h00; + +wire [DATA_PATH_WIDTH*8-1:0] phy_data_s; +wire [DATA_PATH_WIDTH-1:0] charisk28_aligned_s; +wire [DATA_PATH_WIDTH*8-1:0] data_aligned_s; +wire [DATA_PATH_WIDTH-1:0] charisk28_aligned; +wire [DATA_PATH_WIDTH*8-1:0] data_aligned; +wire [DATA_PATH_WIDTH*8-1:0] data_scrambled_s; +wire [DATA_PATH_WIDTH*8-1:0] data_scrambled; + +wire ilas_monitor_reset_s; +wire ilas_monitor_reset; +wire buffer_ready_n_s; + +assign status_ifs_ready = ifs_ready; +assign status_frame_align = frame_align; + +genvar i; +generate + +for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin + assign char[i] = phy_data[i*8+7:i*8]; + assign char_is_valid[i] = ~(phy_notintable[i] | phy_disperr[i]); + + always @(*) begin + char_is_error[i] <= ~char_is_valid[i]; + + char_is_cgs[i] <= 1'b0; + charisk28[i] <= 1'b0; + + if (char[i][4:0] == 'd28 && phy_charisk[i] && char_is_valid[i]) begin + charisk28[i] <= 1'b1; + if (char[i][7:5] == 'd5) begin + char_is_cgs[i] <= 1'b1; + end + end + end +end + +endgenerate + +always @(posedge clk) begin + if (ifs_reset == 1'b1) begin + ifs_ready <= 1'b0; + end else if (cgs_beat_is_cgs == 1'b0 && cgs_beat_has_error == 1'b0) begin + ifs_ready <= 1'b1; + end +end + +always @(posedge clk) begin + if (ifs_ready == 1'b0) begin + if (char_is_cgs[0] == 1'b0) begin + frame_align <= 'h0; + end else if (char_is_cgs[1] == 1'b0) begin + frame_align <= 'h1; + end else if (char_is_cgs[2] == 1'b0) begin + frame_align <= 'h2; + end else begin + frame_align <= 'h3; + end + end +end + +pipeline_stage #( + .WIDTH(DATA_PATH_WIDTH*8), + .REGISTERED(CHAR_INFO_REGISTERED) +) i_pipeline_stage0 ( + .clk(clk), + .in(phy_data), + .out(phy_data_s) +); + +align_mux i_align_mux ( + .clk(clk), + .align(frame_align), + .in_data(phy_data_s), + .out_data(data_aligned_s), + .in_charisk(charisk28), + .out_charisk(charisk28_aligned_s) +); + +assign ilas_monitor_reset_s = ~ifs_ready; + +pipeline_stage #( + .WIDTH(1 + DATA_PATH_WIDTH * (8 + 1)), + .REGISTERED(ALIGN_MUX_REGISTERED) +) i_pipeline_stage1 ( + .clk(clk), + .in({ + ilas_monitor_reset_s, + data_aligned_s, + charisk28_aligned_s + }), + .out({ + ilas_monitor_reset, + data_aligned, + charisk28_aligned + }) +); + +jesd204_scrambler #( + .WIDTH(DATA_PATH_WIDTH*8), + .DESCRAMBLE(1) +) i_descrambler ( + .clk(clk), + .reset(buffer_ready_n_s), + .enable(~cfg_disable_scrambler), + .data_in(data_aligned), + .data_out(data_scrambled_s) +); + +pipeline_stage #( + .WIDTH(1 + DATA_PATH_WIDTH * 8), + .REGISTERED(SCRAMBLER_REGISTERED) +) i_pipeline_stage2 ( + .clk(clk), + .in({ + buffer_ready_n_s, + data_scrambled_s + }), + .out({ + buffer_ready_n, + data_scrambled + }) +); + +elastic_buffer #( + .WIDTH(DATA_PATH_WIDTH*8), + .SIZE(ELASTIC_BUFFER_SIZE) +) i_elastic_buffer ( + .clk(clk), + .reset(reset), + + .wr_data(data_scrambled), + .rd_data(rx_data), + + .ready_n(buffer_ready_n), + .do_release_n(buffer_release_n) +); + +jesd204_ilas_monitor #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) +) i_ilas_monitor ( + .clk(clk), + .reset(ilas_monitor_reset), + .data(data_aligned), + .charisk28(charisk28_aligned), + + .data_ready_n(buffer_ready_n_s), + + .ilas_config_valid(ilas_config_valid), + .ilas_config_addr(ilas_config_addr), + .ilas_config_data(ilas_config_data) +); + +jesd204_rx_cgs #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) +) i_cgs ( + .clk(clk), + .reset(cgs_reset), + + .char_is_cgs(char_is_cgs), + .char_is_error(char_is_error), + + .ready(cgs_ready), + + .status_state(status_cgs_state) +); + +endmodule diff --git a/library/jesd204/jesd204_rx_static_config/Makefile b/library/jesd204/jesd204_rx_static_config/Makefile new file mode 100644 index 000000000..007d281f0 --- /dev/null +++ b/library/jesd204/jesd204_rx_static_config/Makefile @@ -0,0 +1,51 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += jesd204_rx_static_config_ip.tcl +M_DEPS += rx_static_config.v + +M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml +M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all dep clean clean-all +all: dep jesd204_rx_static_config.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +jesd204_rx_static_config.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) jesd204_rx_static_config_ip.tcl >> jesd204_rx_static_config_ip.log 2>&1 + +dep: + make -C ../../jesd204/interfaces/ +#################################################################################### +#################################################################################### diff --git a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl new file mode 100644 index 000000000..cc3dd40c9 --- /dev/null +++ b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl @@ -0,0 +1,69 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create jesd204_rx_static_config +adi_ip_files jesd204_rx_static_config [list \ + "rx_static_config.v" \ +] + +adi_ip_properties_lite jesd204_rx_static_config + +adi_add_bus "rx_cfg" "master" \ + "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_rx_cfg:1.0" \ + { \ + { "cfg_lanes_disable" "lanes_disable" } \ + { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ + { "cfg_octets_per_frame" "octets_per_frame" } \ + { "cfg_lmfc_offset" "lmfc_offset" } \ + { "cfg_sysref_oneshot" "sysref_oneshot" } \ + { "cfg_sysref_required" "sysref_required" } \ + { "cfg_buffer_early_release" "buffer_early_release" } \ + } +adi_add_bus_clock "clk" "rx_cfg" + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/jesd204_rx_static_config/rx_static_config.v b/library/jesd204/jesd204_rx_static_config/rx_static_config.v new file mode 100644 index 000000000..aa5cfb3f2 --- /dev/null +++ b/library/jesd204/jesd204_rx_static_config/rx_static_config.v @@ -0,0 +1,78 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_rx_static_config #( + parameter NUM_LANES = 1, + parameter OCTETS_PER_FRAME = 1, + parameter FRAMES_PER_MULTIFRAME = 32, + parameter SCR = 1, + parameter BUFFER_EARLY_RELEASE = 0 +) ( + input clk, + + output [NUM_LANES-1:0] cfg_lanes_disable, + output [7:0] cfg_beats_per_multiframe, + output [7:0] cfg_octets_per_frame, + output [7:0] cfg_lmfc_offset, + output cfg_sysref_oneshot, + output cfg_sysref_required, + + output [7:0] cfg_buffer_delay, + output cfg_buffer_early_release, + output cfg_disable_scrambler, + output cfg_disable_char_replacement +); + +assign cfg_beats_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME / 4) - 1; +assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1; +assign cfg_lmfc_offset = 3; +assign cfg_sysref_oneshot = 1'b0; +assign cfg_sysref_required = 1'b1; +assign cfg_buffer_delay = 'hb; +assign cfg_buffer_early_release = BUFFER_EARLY_RELEASE; +assign cfg_lanes_disable = {NUM_LANES{1'b0}}; +assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1; +assign cfg_disable_char_replacement = cfg_disable_scrambler; + +endmodule diff --git a/library/jesd204/jesd204_tx/Makefile b/library/jesd204/jesd204_tx/Makefile new file mode 100644 index 000000000..c134d47f9 --- /dev/null +++ b/library/jesd204/jesd204_tx/Makefile @@ -0,0 +1,65 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += jesd204_tx_constr.xdc +M_DEPS += jesd204_tx_ip.tcl +M_DEPS += tx.v +M_DEPS += tx_ctrl.v +M_DEPS += tx_lane.v + +M_DEPS += ../../jesd204/jesd204_common/jesd204_common.xpr + +M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all dep clean clean-all +all: dep jesd204_tx.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +jesd204_tx.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) jesd204_tx_ip.tcl >> jesd204_tx_ip.log 2>&1 + +dep: + make -C ../../jesd204/jesd204_common/ + make -C ../../jesd204/interfaces/ +#################################################################################### +#################################################################################### diff --git a/library/jesd204/jesd204_tx/ilas_cfg_static.v b/library/jesd204/jesd204_tx/ilas_cfg_static.v new file mode 100644 index 000000000..d5976fbf5 --- /dev/null +++ b/library/jesd204/jesd204_tx/ilas_cfg_static.v @@ -0,0 +1,98 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. Confidential and proprietary. +// +// Do not redistribute without explicit permission. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +module jesd204_ilas_config_static #( + parameter DID = 8'h00, + parameter BID = 4'h0, + parameter L = 5'h3, + parameter SCR = 1'b1, + parameter F = 8'h01, + parameter K = 5'h1f, + parameter M = 8'h3, + parameter N = 5'h0f, + parameter CS = 2'h0, + parameter NP = 5'h0f, + parameter SUBCLASSV = 3'h1, + parameter S = 5'h00, + parameter JESDV = 3'h1, + parameter CF = 5'h00, + parameter HD = 1'b1, + parameter NUM_LANES = 1 +) ( + input clk, + + input [1:0] ilas_config_addr, + input ilas_config_rd, + output reg [32*NUM_LANES-1:0] ilas_config_data +); + +wire [31:0] ilas_mem[0:3]; + +assign ilas_mem[0][15:0] = 8'h00; +assign ilas_mem[0][23:16] = DID; // DID +assign ilas_mem[0][27:24] = BID; // BID +assign ilas_mem[0][31:28] = 4'h0; // ADJCNT +assign ilas_mem[1][4:0] = 5'h00; // LID +assign ilas_mem[1][5] = 1'b0; // PHADJ +assign ilas_mem[1][6] = 1'b0; // ADJDIR +assign ilas_mem[1][7] = 1'b0; // X +assign ilas_mem[1][12:8] = L; // L +assign ilas_mem[1][14:13] = 2'b00; // X +assign ilas_mem[1][15] = SCR; // SCR +assign ilas_mem[1][23:16] = F; // F +assign ilas_mem[1][28:24] = K; // K +assign ilas_mem[1][31:29] = 3'b000; // X +assign ilas_mem[2][7:0] = M; // M +assign ilas_mem[2][12:8] = N; // N +assign ilas_mem[2][13] = 1'b0; // X +assign ilas_mem[2][15:14] = CS; // CS +assign ilas_mem[2][20:16] = NP; // N' +assign ilas_mem[2][23:21] = SUBCLASSV; // SUBCLASSV +assign ilas_mem[2][28:24] = S; // S +assign ilas_mem[2][31:29] = JESDV; // JESDV +assign ilas_mem[3][4:0] = CF; // CF +assign ilas_mem[3][6:5] = 2'b00; // X +assign ilas_mem[3][7] = HD; // HD +assign ilas_mem[3][23:8] = 16'h0000; // X +assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] + + ilas_mem[1][4:0] + ilas_mem[1][5] + ilas_mem[1][6] + ilas_mem[1][12:8] + + ilas_mem[1][15] + ilas_mem[1][23:16] + ilas_mem[1][28:24] + + ilas_mem[2][7:0] + ilas_mem[2][12:8] + ilas_mem[2][15:14] + + ilas_mem[2][20:16] + ilas_mem[2][23:21] + ilas_mem[2][28:24] + + ilas_mem[2][31:29] + ilas_mem[3][4:0] + ilas_mem[3][7]; + +generate +genvar i; + +for (i = 0; i < NUM_LANES; i = i + 1) begin + always @(posedge clk) begin + if (ilas_config_rd == 1'b1) begin + ilas_config_data[i*32+31:i*32] <= ilas_mem[ilas_config_addr]; + + /* Overwrite special cases */ + case (ilas_config_addr) + 'h1: ilas_config_data[i*32+4:i*32] <= i; + 'h3: ilas_config_data[i*32+31:i*32+24] <= ilas_mem[ilas_config_addr][31:24] + i; + endcase + end + end +end +endgenerate + +endmodule diff --git a/library/jesd204/jesd204_tx/jesd204_tx_constr.xdc b/library/jesd204/jesd204_tx/jesd204_tx_constr.xdc new file mode 100644 index 000000000..a753b66c3 --- /dev/null +++ b/library/jesd204/jesd204_tx/jesd204_tx_constr.xdc @@ -0,0 +1,52 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +set_property ASYNC_REG TRUE \ + [get_cells {i_lmfc/sysref_d1_reg}] \ + [get_cells {i_lmfc/sysref_d2_reg}] + +# Make sure that the device clock to sysref skew is at least somewhat +# predictable +set_property IOB TRUE \ + [get_cells {i_lmfc/sysref_r_reg}] diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl b/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl new file mode 100644 index 000000000..a831a6b56 --- /dev/null +++ b/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl @@ -0,0 +1,135 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create jesd204_tx +adi_ip_files jesd204_tx [list \ + "tx_lane.v" \ + "tx_ctrl.v" \ + "jesd204_tx_constr.xdc" \ + "tx.v" +] + +adi_ip_properties_lite jesd204_tx + +adi_ip_add_core_dependencies { \ + analog.com:user:jesd204_common:1.0 \ +} + +set_property display_name "ADI JESD204 Transmit" [ipx::current_core] +set_property description "ADI JESD204 Transmit" [ipx::current_core] + +adi_add_bus "tx_data" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { \ + { "tx_ready" "TREADY" } \ + { "tx_data" "TDATA" } \ + } + +adi_add_multi_bus 8 "tx_phy" "master" \ + "xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \ + "xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \ + [list \ + {"phy_data" "txdata" 32} \ + { "phy_charisk" "txcharisk" 4} \ + ] \ + "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})" + +adi_add_bus "tx_cfg" "slave" \ + "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_tx_cfg:1.0" \ + { \ + { "cfg_lanes_disable" "lanes_disable" } \ + { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ + { "cfg_octets_per_frame" "octets_per_frame" } \ + { "cfg_lmfc_offset" "lmfc_offset" } \ + { "cfg_sysref_oneshot" "sysref_oneshot" } \ + { "cfg_sysref_required" "sysref_required" } \ + { "cfg_continuous_cgs" "continuous_cgs" } \ + { "cfg_continuous_ilas" "continuous_ilas" } \ + { "cfg_skip_ilas" "skip_ilas" } \ + { "cfg_mframes_per_ilas" "mframes_per_ilas" } \ + { "cfg_disable_char_replacement" "disable_char_replacement" } \ + { "cfg_disable_scrambler" "disable_scrambler" } \ + } + +adi_add_bus "tx_ilas_config" "master" \ + "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ilas_config:1.0" \ + { \ + { "ilas_config_rd" "rd" } \ + { "ilas_config_addr" "addr" } \ + { "ilas_config_data" "data" } \ + } + +adi_add_bus "tx_event" "master" \ + "analog.com:interface:jesd204_tx_event_rtl:1.0" \ + "analog.com:interface:jesd204_tx_event:1.0" \ + { \ + { "event_sysref_alignment_error" "sysref_alignment_error" } \ + { "event_sysref_edge" "sysref_edge" } \ + } + +adi_add_bus "tx_status" "master" \ + "analog.com:interface:jesd204_tx_status_rtl:1.0" \ + "analog.com:interface:jesd204_tx_status:1.0" \ + { \ + { "status_state" "state" } \ + { "status_sync" "sync" } \ + } + +adi_add_bus "tx_ctrl" "slave" \ + "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ctrl:1.0" \ + { \ + { "ctrl_manual_sync_request" "manual_sync_request" } \ + } + +adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \ + "reset" + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/jesd204_tx/tx.v b/library/jesd204/jesd204_tx/tx.v new file mode 100644 index 000000000..dd214f95f --- /dev/null +++ b/library/jesd204/jesd204_tx/tx.v @@ -0,0 +1,224 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_tx #( + parameter NUM_LANES = 1 +) ( + input clk, + input reset, + + output [32*NUM_LANES-1:0] phy_data, + output [4*NUM_LANES-1:0] phy_charisk, + + input sysref, + output lmfc_edge, + output lmfc_clk, + + input sync, + + input [32*NUM_LANES-1:0] tx_data, + output tx_ready, + + input [NUM_LANES-1:0] cfg_lanes_disable, + input [7:0] cfg_beats_per_multiframe, + input [7:0] cfg_octets_per_frame, + input [7:0] cfg_lmfc_offset, + input cfg_sysref_oneshot, + input cfg_sysref_required, + input cfg_continuous_cgs, + input cfg_continuous_ilas, + input cfg_skip_ilas, + input [7:0] cfg_mframes_per_ilas, + input cfg_disable_char_replacement, + input cfg_disable_scrambler, + + output ilas_config_rd, + output [1:0] ilas_config_addr, + input [32*NUM_LANES-1:0] ilas_config_data, + + input ctrl_manual_sync_request, + + output event_sysref_edge, + output event_sysref_alignment_error, + + output status_sync, + output [1:0] status_state +); + +/* Only 4 is supported at the moment */ +localparam DATA_PATH_WIDTH = 4; + +localparam MAX_OCTETS_PER_FRAME = 8; +localparam MAX_OCTETS_PER_MULTIFRAME = + (MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32); +localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH; + +localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 : + MAX_BEATS_PER_MULTIFRAME > 128 ? 8 : + MAX_BEATS_PER_MULTIFRAME > 64 ? 7 : + MAX_BEATS_PER_MULTIFRAME > 32 ? 6 : + MAX_BEATS_PER_MULTIFRAME > 16 ? 5 : + MAX_BEATS_PER_MULTIFRAME > 8 ? 4 : + MAX_BEATS_PER_MULTIFRAME > 4 ? 3 : + MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1; + +localparam DW = DATA_PATH_WIDTH * 8 * NUM_LANES; + +wire eof_gen_reset; +wire [DATA_PATH_WIDTH-1:0] eof; +wire eomf; + +wire [NUM_LANES-1:0] lane_cgs_enable; + +wire [DW-1:0] ilas_data; +wire [DATA_PATH_WIDTH-1:0] ilas_charisk; + +wire cfg_generate_eomf = 1'b1; + +jesd204_lmfc i_lmfc ( + .clk(clk), + .reset(reset), + + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + .cfg_lmfc_offset(cfg_lmfc_offset), + .cfg_sysref_oneshot(cfg_sysref_oneshot), + .cfg_sysref_required(cfg_sysref_required), + + .sysref(sysref), + + .clear_sysref_captured(1'b0), + .sysref_captured(), + .sysref_edge(event_sysref_edge), + .sysref_alignment_error(event_sysref_alignment_error), + + .lmfc_edge(lmfc_edge), + .lmfc_clk(lmfc_clk), + .lmfc_counter() +); + +jesd204_tx_ctrl #( + .NUM_LANES(NUM_LANES), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) +) i_tx_ctrl ( + .clk(clk), + .reset(reset), + + .sync(sync), + .lmfc_edge(lmfc_edge), + + .lane_cgs_enable(lane_cgs_enable), + .eof_reset(eof_gen_reset), + + .tx_ready(tx_ready), + + .ilas_data(ilas_data), + .ilas_charisk(ilas_charisk), + + .ilas_config_addr(ilas_config_addr), + .ilas_config_rd(ilas_config_rd), + .ilas_config_data(ilas_config_data), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_continuous_cgs(cfg_continuous_cgs), + .cfg_continuous_ilas(cfg_continuous_ilas), + .cfg_skip_ilas(cfg_skip_ilas), + .cfg_mframes_per_ilas(cfg_mframes_per_ilas), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + + .ctrl_manual_sync_request(ctrl_manual_sync_request), + + .status_sync(status_sync), + .status_state(status_state) +); + +jesd204_eof_generator #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .MAX_OCTETS_PER_FRAME(MAX_OCTETS_PER_FRAME) +) i_eof_gen ( + .clk(clk), + .reset(eof_gen_reset), + + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_generate_eomf(cfg_generate_eomf), + + .lmfc_edge(lmfc_edge), + .sof(), + .eof(eof), + .eomf(eomf) +); + +generate +genvar i; +for (i = 0; i < NUM_LANES; i = i + 1) begin + + localparam D_START = i * DATA_PATH_WIDTH*8; + localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1; + localparam C_START = i * DATA_PATH_WIDTH; + localparam C_STOP = C_START + DATA_PATH_WIDTH-1; + + jesd204_tx_lane #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_lane ( + .clk(clk), + + .eof(eof), + .eomf(eomf), + + .cgs_enable(lane_cgs_enable[i]), + + .ilas_data(ilas_data[D_STOP:D_START]), + .ilas_charisk(ilas_charisk), + + .tx_data(tx_data[D_STOP:D_START]), + .tx_ready(tx_ready), + + .phy_data(phy_data[D_STOP:D_START]), + .phy_charisk(phy_charisk[C_STOP:C_START]), + + .cfg_disable_scrambler(cfg_disable_scrambler) + ); +end +endgenerate + +endmodule diff --git a/library/jesd204/jesd204_tx/tx_ctrl.v b/library/jesd204/jesd204_tx/tx_ctrl.v new file mode 100644 index 000000000..b0478e4f4 --- /dev/null +++ b/library/jesd204/jesd204_tx/tx_ctrl.v @@ -0,0 +1,270 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_tx_ctrl #( + parameter NUM_LANES = 1, + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input sync, + input lmfc_edge, + + output reg [NUM_LANES-1:0] lane_cgs_enable, + output reg eof_reset, + + output reg tx_ready, + + output reg [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_data, + output reg [DATA_PATH_WIDTH-1:0] ilas_charisk, + + output reg [1:0] ilas_config_addr, + output reg ilas_config_rd, + input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_config_data, + + input [NUM_LANES-1:0] cfg_lanes_disable, + input cfg_continuous_cgs, + input cfg_continuous_ilas, + input cfg_skip_ilas, + input [7:0] cfg_mframes_per_ilas, + input cfg_disable_char_replacement, + + input ctrl_manual_sync_request, + + output status_sync, + output reg [1:0] status_state +); + +reg lmfc_edge_d1 = 1'b0; +reg lmfc_edge_d2 = 1'b0; +reg ilas_reset = 1'b1; +reg ilas_data_reset = 1'b1; +reg sync_request = 1'b0; +reg sync_request_received = 1'b0; +reg [1:0] sync_sync = 2'b11; +reg [7:0] mframe_counter = 'h00; +reg [5:0] ilas_counter = 'h00; +reg ilas_config_rd_d1 = 1'b1; +reg last_ilas_mframe = 1'b0; +reg cgs_enable = 1'b1; + +always @(posedge clk) begin + sync_sync <= {sync_sync[0],sync}; +end + +assign status_sync = sync_sync; + +always @(posedge clk) begin + if (reset == 1'b1) begin + sync_request <= 1'b0; + end else begin + /* TODO: SYNC must be asserted at least 4 frames before interpreted as a + * sync request and the /K28.5/ symbol generation has lasted for at + * least 1 frame + 9 octets */ + if (cfg_continuous_cgs == 1'b1) begin + sync_request <= 1'b1; + end else begin + sync_request <= ~sync_sync[1] | ctrl_manual_sync_request; + end + end +end + +always @(posedge clk) begin + if (sync_request == 1'b0 && sync_request_received == 1'b1) begin + lmfc_edge_d1 <= lmfc_edge; + lmfc_edge_d2 <= lmfc_edge_d1; + end else begin + lmfc_edge_d1 <= 1'b0; + lmfc_edge_d2 <= 1'b0; + end +end + +always @(posedge clk) begin + if (reset == 1'b1) begin + sync_request_received <= 1'b0; + end else if (sync_request == 1'b1) begin + sync_request_received <= 1'b1; + end +end + +always @(posedge clk) begin + if (cfg_skip_ilas == 1'b1 || + mframe_counter == cfg_mframes_per_ilas) begin + last_ilas_mframe <= 1'b1; + end else begin + last_ilas_mframe <= 1'b0; + end +end + +localparam STATE_WAIT = 2'b00; +localparam STATE_CGS = 2'b01; +localparam STATE_ILAS = 2'b10; +localparam STATE_DATA = 2'b11; + +/* Timeline + * + * #1 lmfc_edge == 1, ilas_reset update + * #2 eof_reset update + * #3 {lane_,}cgs_enable, tx_ready update + * + * One multi-frame should at least be 3 clock cycles (TBD 64-bit data path) + */ + +always @(posedge clk) begin + if (sync_request == 1'b1 || reset == 1'b1) begin + cgs_enable <= 1'b1; + lane_cgs_enable <= {NUM_LANES{1'b1}}; + tx_ready <= 1'b0; + eof_reset <= 1'b1; + ilas_reset <= 1'b1; + ilas_data_reset <= 1'b1; + + if (sync_request_received == 1'b0) begin + status_state <= STATE_WAIT; + end else begin + status_state <= STATE_CGS; + end + end else if (sync_request_received == 1'b1) begin + if (lmfc_edge == 1'b1 && last_ilas_mframe == 1'b1) begin + ilas_reset <= 1'b1; + status_state <= STATE_DATA; + end else if (lmfc_edge_d1 == 1'b1 && (cfg_continuous_ilas == 1'b1 || + cgs_enable == 1'b1)) begin + ilas_reset <= 1'b0; + status_state <= STATE_ILAS; + end + + if (lmfc_edge_d1 == 1'b1) begin + if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin + eof_reset <= cfg_disable_char_replacement; + ilas_data_reset <= 1'b1; + end else if (cgs_enable == 1'b1) begin + ilas_data_reset <= 1'b0; + end + end + + if (lmfc_edge_d2 == 1'b1) begin + lane_cgs_enable <= cfg_lanes_disable; + cgs_enable <= 1'b0; + if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin + tx_ready <= 1'b1; + end + end + end +end + +always @(posedge clk) begin + if (ilas_reset == 1'b1) begin + mframe_counter <= 'h00; + end else if (lmfc_edge_d1 == 1'b1) begin + mframe_counter <= mframe_counter + 1'b1; + end +end + +always @(posedge clk) begin + if (ilas_reset == 1'b1) begin + ilas_config_rd <= 1'b0; + end else if (mframe_counter == 'h00 && lmfc_edge == 1'b1) begin + ilas_config_rd <= 1'b1; + end else if (ilas_config_addr == 'h3) begin + ilas_config_rd <= 1'b0; + end + ilas_config_rd_d1 <= ilas_config_rd; +end + +always @(posedge clk) begin + if (ilas_config_rd == 1'b0) begin + ilas_config_addr <= 'h00; + end else begin + ilas_config_addr <= ilas_config_addr + 1'b1; + end +end + +always @(posedge clk) begin + if (ilas_reset == 1'b1) begin + ilas_counter <= 'h00; + end else begin + ilas_counter <= ilas_counter + 1'b1; + end +end + +wire [31:0] ilas_default_data = { + ilas_counter,2'h3, + ilas_counter,2'h2, + ilas_counter,2'h1, + ilas_counter,2'h0 +}; + +always @(posedge clk) begin + if (ilas_data_reset == 1'b1) begin + ilas_data <= {NUM_LANES{32'h00}}; + ilas_charisk <= 4'b0000; + end else begin + if (ilas_config_rd_d1 == 1'b1) begin + case (ilas_config_addr) + 2'h1: begin + ilas_data <= (ilas_config_data & {NUM_LANES{32'hffff0000}}) | + {NUM_LANES{16'h00,8'h9c,8'h1c}}; // /Q/ /R/ + ilas_charisk <= 4'b0011; + end + default: begin + ilas_data <= ilas_config_data; + ilas_charisk <= 4'b0000; + end + endcase + end else if (lmfc_edge_d2 == 1'b1) begin + ilas_data <= {NUM_LANES{ilas_default_data[31:8],8'h1c}}; // /R/ + ilas_charisk <= 4'b0001; + end else if (lmfc_edge_d1 == 1'b1) begin + ilas_data <= {NUM_LANES{8'h7c,ilas_default_data[23:0]}}; // /A/ + ilas_charisk <= 4'b1000; + end else begin + ilas_data <= {NUM_LANES{ilas_default_data}}; + ilas_charisk <= 4'b0000; + end + end +end + +endmodule diff --git a/library/jesd204/jesd204_tx/tx_lane.v b/library/jesd204/jesd204_tx/tx_lane.v new file mode 100644 index 000000000..454c7bfde --- /dev/null +++ b/library/jesd204/jesd204_tx/tx_lane.v @@ -0,0 +1,120 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_tx_lane #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + + input [DATA_PATH_WIDTH-1:0] eof, + input eomf, + + input cgs_enable, + + input [DATA_PATH_WIDTH*8-1:0] ilas_data, + input [DATA_PATH_WIDTH-1:0] ilas_charisk, + + input [DATA_PATH_WIDTH*8-1:0] tx_data, + input tx_ready, + + output reg [DATA_PATH_WIDTH*8-1:0] phy_data, + output reg [DATA_PATH_WIDTH-1:0] phy_charisk, + + input cfg_disable_scrambler +); + +wire [DATA_PATH_WIDTH*8-1:0] scrambled_data; +wire [7:0] scrambled_char[0:DATA_PATH_WIDTH-1]; +reg [7:0] char_align[0:DATA_PATH_WIDTH-1]; + +jesd204_scrambler #( + .WIDTH(DATA_PATH_WIDTH*8), + .DESCRAMBLE(0) +) i_scrambler ( + .clk(clk), + .reset(~tx_ready), + .enable(~cfg_disable_scrambler), + .data_in(tx_data), + .data_out(scrambled_data) +); + +generate +genvar i; + +for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin + assign scrambled_char[i] = scrambled_data[i*8+7:i*8]; + + always @(*) begin + if (i == DATA_PATH_WIDTH-1 && eomf == 1'b1) begin + char_align[i] <= 8'h7c; // /A/ + end else begin + char_align[i] <= 8'hfc; // /F/ + end + end + + always @(posedge clk) begin + if (cgs_enable == 1'b1) begin + phy_charisk[i] <= 1'b1; + end else if (eof[i] == 1'b1 && scrambled_char[i] == char_align[i]) begin + phy_charisk[i] <= 1'b1; + end else begin + phy_charisk[i] <= ilas_charisk[i]; + end + end +end + +endgenerate + +always @(posedge clk) begin + if (cgs_enable == 1'b1) begin + phy_data <= {DATA_PATH_WIDTH{8'hbc}}; + end else begin + case (tx_ready) + 1'b0: phy_data <= ilas_data; + default: phy_data <= scrambled_data; + endcase + end +end + +endmodule diff --git a/library/jesd204/jesd204_tx_static_config/Makefile b/library/jesd204/jesd204_tx_static_config/Makefile new file mode 100644 index 000000000..7a21e41bb --- /dev/null +++ b/library/jesd204/jesd204_tx_static_config/Makefile @@ -0,0 +1,54 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += ilas_cfg_static.v +M_DEPS += jesd204_tx_static_config_ip.tcl +M_DEPS += tx_static_config.v + +M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml +M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all dep clean clean-all +all: dep jesd204_tx_static_config.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +jesd204_tx_static_config.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) jesd204_tx_static_config_ip.tcl >> jesd204_tx_static_config_ip.log 2>&1 + +dep: + make -C ../../jesd204/interfaces/ +#################################################################################### +#################################################################################### diff --git a/library/jesd204/jesd204_tx_static_config/ilas_cfg_static.v b/library/jesd204/jesd204_tx_static_config/ilas_cfg_static.v new file mode 100644 index 000000000..fe7159281 --- /dev/null +++ b/library/jesd204/jesd204_tx_static_config/ilas_cfg_static.v @@ -0,0 +1,123 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_ilas_config_static #( + parameter DID = 8'h00, + parameter BID = 4'h0, + parameter L = 5'h3, + parameter SCR = 1'b1, + parameter F = 8'h01, + parameter K = 5'h1f, + parameter M = 8'h3, + parameter N = 5'h0f, + parameter CS = 2'h0, + parameter NP = 5'h0f, + parameter SUBCLASSV = 3'h1, + parameter S = 5'h00, + parameter JESDV = 3'h1, + parameter CF = 5'h00, + parameter HD = 1'b1, + parameter NUM_LANES = 1 +) ( + input clk, + + input [1:0] ilas_config_addr, + input ilas_config_rd, + output reg [32*NUM_LANES-1:0] ilas_config_data +); + +wire [31:0] ilas_mem[0:3]; + +assign ilas_mem[0][15:0] = 8'h00; +assign ilas_mem[0][23:16] = DID; // DID +assign ilas_mem[0][27:24] = BID; // BID +assign ilas_mem[0][31:28] = 4'h0; // ADJCNT +assign ilas_mem[1][4:0] = 5'h00; // LID +assign ilas_mem[1][5] = 1'b0; // PHADJ +assign ilas_mem[1][6] = 1'b0; // ADJDIR +assign ilas_mem[1][7] = 1'b0; // X +assign ilas_mem[1][12:8] = L; // L +assign ilas_mem[1][14:13] = 2'b00; // X +assign ilas_mem[1][15] = SCR; // SCR +assign ilas_mem[1][23:16] = F; // F +assign ilas_mem[1][28:24] = K; // K +assign ilas_mem[1][31:29] = 3'b000; // X +assign ilas_mem[2][7:0] = M; // M +assign ilas_mem[2][12:8] = N; // N +assign ilas_mem[2][13] = 1'b0; // X +assign ilas_mem[2][15:14] = CS; // CS +assign ilas_mem[2][20:16] = NP; // N' +assign ilas_mem[2][23:21] = SUBCLASSV; // SUBCLASSV +assign ilas_mem[2][28:24] = S; // S +assign ilas_mem[2][31:29] = JESDV; // JESDV +assign ilas_mem[3][4:0] = CF; // CF +assign ilas_mem[3][6:5] = 2'b00; // X +assign ilas_mem[3][7] = HD; // HD +assign ilas_mem[3][23:8] = 16'h0000; // X +assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] + + ilas_mem[1][4:0] + ilas_mem[1][5] + ilas_mem[1][6] + ilas_mem[1][12:8] + + ilas_mem[1][15] + ilas_mem[1][23:16] + ilas_mem[1][28:24] + + ilas_mem[2][7:0] + ilas_mem[2][12:8] + ilas_mem[2][15:14] + + ilas_mem[2][20:16] + ilas_mem[2][23:21] + ilas_mem[2][28:24] + + ilas_mem[2][31:29] + ilas_mem[3][4:0] + ilas_mem[3][7]; + +generate +genvar i; + +for (i = 0; i < NUM_LANES; i = i + 1) begin + always @(posedge clk) begin + if (ilas_config_rd == 1'b1) begin + ilas_config_data[i*32+31:i*32] <= ilas_mem[ilas_config_addr]; + + /* Overwrite special cases */ + case (ilas_config_addr) + 'h1: ilas_config_data[i*32+4:i*32] <= i; + 'h3: ilas_config_data[i*32+31:i*32+24] <= ilas_mem[ilas_config_addr][31:24] + i; + endcase + end + end +end +endgenerate + +endmodule diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl new file mode 100644 index 000000000..bbdc966c6 --- /dev/null +++ b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl @@ -0,0 +1,85 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create jesd204_tx_static_config +adi_ip_files jesd204_tx_static_config [list \ + "tx_static_config.v" \ + "ilas_cfg_static.v" \ +] + +adi_ip_properties_lite jesd204_tx_static_config + +adi_add_bus "tx_cfg" "master" \ + "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_tx_cfg:1.0" \ + { \ + { "cfg_lanes_disable" "lanes_disable" } \ + { "cfg_beats_per_multiframe" "beats_per_multiframe" } \ + { "cfg_octets_per_frame" "octets_per_frame" } \ + { "cfg_lmfc_offset" "lmfc_offset" } \ + { "cfg_sysref_oneshot" "sysref_oneshot" } \ + { "cfg_sysref_required" "sysref_required" } \ + { "cfg_continuous_cgs" "continuous_cgs" } \ + { "cfg_continuous_ilas" "continuous_ilas" } \ + { "cfg_skip_ilas" "skip_ilas" } \ + { "cfg_mframes_per_ilas" "mframes_per_ilas" } \ + { "cfg_disable_char_replacement" "disable_char_replacement" } \ + { "cfg_disable_scrambler" "disable_scrambler" } \ + } + +adi_add_bus "tx_ilas_config" "slave" \ + "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ilas_config:1.0" \ + { \ + { "ilas_config_rd" "rd" } \ + { "ilas_config_addr" "addr" } \ + { "ilas_config_data" "data" } \ + } + +adi_add_bus_clock "core_clk" "tx_cfg:tx_ilas_config" + +ipx::save_core [ipx::current_core] diff --git a/library/jesd204/jesd204_tx_static_config/tx_static_config.v b/library/jesd204/jesd204_tx_static_config/tx_static_config.v new file mode 100644 index 000000000..ec5f5aa2e --- /dev/null +++ b/library/jesd204/jesd204_tx_static_config/tx_static_config.v @@ -0,0 +1,111 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module jesd204_tx_static_config #( + parameter NUM_LANES = 1, + parameter OCTETS_PER_FRAME = 1, + parameter FRAMES_PER_MULTIFRAME = 32, + parameter NUM_CONVERTERS = 1, + parameter N = 16, + parameter NP = 16, + parameter HIGH_DENSITY = 1, + parameter SCR = 1 +) ( + input clk, + + output [NUM_LANES-1:0] cfg_lanes_disable, + output [7:0] cfg_beats_per_multiframe, + output [7:0] cfg_octets_per_frame, + output [7:0] cfg_lmfc_offset, + output cfg_sysref_oneshot, + output cfg_sysref_required, + output cfg_continuous_cgs, + output cfg_continuous_ilas, + output cfg_skip_ilas, + output [7:0] cfg_mframes_per_ilas, + output cfg_disable_char_replacement, + output cfg_disable_scrambler, + + input ilas_config_rd, + input [1:0] ilas_config_addr, + output [32*NUM_LANES-1:0] ilas_config_data +); + +assign cfg_beats_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME / 4) - 1; +assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1; +assign cfg_lmfc_offset = 3; +assign cfg_sysref_oneshot = 1'b0; +assign cfg_sysref_required = 1'b1; +assign cfg_continuous_cgs = 1'b0; +assign cfg_continuous_ilas = 1'b0; +assign cfg_skip_ilas = 1'b0; +assign cfg_mframes_per_ilas = 3; +assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1; +assign cfg_disable_char_replacement = cfg_disable_scrambler; +assign cfg_lanes_disable = {NUM_LANES{1'b0}}; + +jesd204_ilas_config_static #( + .DID(8'h00), + .BID(5'h00), + .L(NUM_LANES - 1), + .SCR(SCR), + .F(OCTETS_PER_FRAME - 1), + .K(FRAMES_PER_MULTIFRAME - 1), + .M(NUM_CONVERTERS - 1), + .N(N), + .NP(NP), + .SUBCLASSV(3'h1), + .S(5'h00), + .JESDV(3'h1), + .CF(5'h00), + .HD(HIGH_DENSITY), + .NUM_LANES(NUM_LANES) +) i_ilas_config ( + .clk(clk), + .ilas_config_addr(ilas_config_addr), + .ilas_config_rd(ilas_config_rd), + .ilas_config_data(ilas_config_data) +); + +endmodule diff --git a/library/jesd204/scripts/jesd204.tcl b/library/jesd204/scripts/jesd204.tcl new file mode 100644 index 000000000..1ea95a1b7 --- /dev/null +++ b/library/jesd204/scripts/jesd204.tcl @@ -0,0 +1,185 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +proc adi_axi_jesd204_tx_create {ip_name num_lanes} { + + if {$num_lanes < 1 || $num_lanes > 8} { + return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-8)" + } + + startgroup + + set result [catch { + + create_bd_cell -type hier $ip_name + + ad_ip_instance axi_jesd204_tx "${ip_name}/tx_axi" + ad_ip_instance jesd204_tx "${ip_name}/tx" + + ad_ip_parameter "${ip_name}/tx_axi" CONFIG.NUM_LANES $num_lanes + ad_ip_parameter "${ip_name}/tx" CONFIG.NUM_LANES $num_lanes + + ad_connect "${ip_name}/tx_axi/core_reset" "${ip_name}/tx/reset" + ad_connect "${ip_name}/tx_axi/tx_ctrl" "${ip_name}/tx/tx_ctrl" + ad_connect "${ip_name}/tx_axi/tx_cfg" "${ip_name}/tx/tx_cfg" + ad_connect "${ip_name}/tx/tx_event" "${ip_name}/tx_axi/tx_event" + ad_connect "${ip_name}/tx/tx_status" "${ip_name}/tx_axi/tx_status" + ad_connect "${ip_name}/tx/tx_ilas_config" "${ip_name}/tx_axi/tx_ilas_config" + + # Control interface + create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk" + create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn" + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi" + create_bd_pin -dir O -type intr "${ip_name}/irq" + + ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tx_axi/s_axi_aclk" + ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tx_axi/s_axi_aresetn" + ad_connect "${ip_name}/s_axi" "${ip_name}/tx_axi/s_axi" + ad_connect "${ip_name}/tx_axi/irq" "${ip_name}/irq" + + # JESD204 processing + create_bd_pin -dir I -type clk "${ip_name}/device_clk" + create_bd_pin -dir I "${ip_name}/sync" + create_bd_pin -dir I "${ip_name}/sysref" + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/tx_data" + + ad_connect "${ip_name}/device_clk" "${ip_name}/tx_axi/core_clk" + ad_connect "${ip_name}/device_clk" "${ip_name}/tx/clk" + ad_connect "${ip_name}/sync" "${ip_name}/tx/sync" + ad_connect "${ip_name}/sysref" "${ip_name}/tx/sysref" + ad_connect "${ip_name}/tx_data" "${ip_name}/tx/tx_data" + + for {set i 0} {$i < $num_lanes} {incr i} { + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 "${ip_name}/tx_phy${i}" + ad_connect "${ip_name}/tx/tx_phy${i}" "${ip_name}/tx_phy${i}" + } + } resulttext resultoptions] + + dict unset resultoptions -level + + endgroup + + if {$result != 0} { + undo -quiet + } + + return -options $resultoptions $resulttext +} + +proc adi_axi_jesd204_rx_create {ip_name num_lanes} { + + if {$num_lanes < 1 || $num_lanes > 8} { + return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-8)" + } + + startgroup + + set result [catch { + + create_bd_cell -type hier $ip_name + + ad_ip_instance axi_jesd204_rx "${ip_name}/rx_axi" + ad_ip_instance jesd204_rx "${ip_name}/rx" + + ad_ip_parameter "${ip_name}/rx_axi" CONFIG.NUM_LANES $num_lanes + ad_ip_parameter "${ip_name}/rx" CONFIG.NUM_LANES $num_lanes + + ad_connect "${ip_name}/rx_axi/core_reset" "${ip_name}/rx/reset" + ad_connect "${ip_name}/rx_axi/rx_cfg" "${ip_name}/rx/rx_cfg" + ad_connect "${ip_name}/rx/rx_event" "${ip_name}/rx_axi/rx_event" + ad_connect "${ip_name}/rx/rx_status" "${ip_name}/rx_axi/rx_status" + ad_connect "${ip_name}/rx/rx_ilas_config" "${ip_name}/rx_axi/rx_ilas_config" + + # Control interface + create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk" + create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn" + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi" + create_bd_pin -dir O -type intr "${ip_name}/irq" + + ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/rx_axi/s_axi_aclk" + ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/rx_axi/s_axi_aresetn" + ad_connect "${ip_name}/s_axi" "${ip_name}/rx_axi/s_axi" + ad_connect "${ip_name}/rx_axi/irq" "${ip_name}/irq" + + # JESD204 processing + create_bd_pin -dir I -type clk "${ip_name}/device_clk" + create_bd_pin -dir O "${ip_name}/sync" + create_bd_pin -dir I "${ip_name}/sysref" + create_bd_pin -dir O "${ip_name}/phy_en_char_align" +# create_bd_pin -dir I "${ip_name}/phy_ready" + create_bd_pin -dir O -from 3 -to 0 "${ip_name}/rx_eof" + create_bd_pin -dir O -from 3 -to 0 "${ip_name}/rx_sof" + +# create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/rx_data" + create_bd_pin -dir O "${ip_name}/rx_data_tvalid" + create_bd_pin -dir O -from [expr $num_lanes * 32 - 1] -to 0 "${ip_name}/rx_data_tdata" + + ad_connect "${ip_name}/device_clk" "${ip_name}/rx_axi/core_clk" + ad_connect "${ip_name}/device_clk" "${ip_name}/rx/clk" + ad_connect "${ip_name}/rx/sync" "${ip_name}/sync" + ad_connect "${ip_name}/sysref" "${ip_name}/rx/sysref" +# ad_connect "${ip_name}/phy_ready" "${ip_name}/rx/phy_ready" + ad_connect "${ip_name}/rx/phy_en_char_align" "${ip_name}/phy_en_char_align" + ad_connect "${ip_name}/rx/rx_data" "${ip_name}/rx_data_tdata" + ad_connect "${ip_name}/rx/rx_valid" "${ip_name}/rx_data_tvalid" + ad_connect "${ip_name}/rx/rx_eof" "${ip_name}/rx_eof" + ad_connect "${ip_name}/rx/rx_sof" "${ip_name}/rx_sof" + + for {set i 0} {$i < $num_lanes} {incr i} { + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 "${ip_name}/rx_phy${i}" + ad_connect "${ip_name}/rx/rx_phy${i}" "${ip_name}/rx_phy${i}" + } + } resulttext resultoptions] + + dict unset resultoptions -level + + endgroup + + if {$result != 0} { + undo -quiet + } + + return -options $resultoptions $resulttext +} diff --git a/library/jesd204/tb/.gitignore b/library/jesd204/tb/.gitignore new file mode 100644 index 000000000..804d96e77 --- /dev/null +++ b/library/jesd204/tb/.gitignore @@ -0,0 +1,2 @@ +run/ +vcd/ diff --git a/library/jesd204/tb/axi_jesd204_rx_regmap_tb b/library/jesd204/tb/axi_jesd204_rx_regmap_tb new file mode 100755 index 000000000..7ca030b90 --- /dev/null +++ b/library/jesd204/tb/axi_jesd204_rx_regmap_tb @@ -0,0 +1,16 @@ +#!/bin/bash + +SOURCE="axi_jesd204_rx_regmap_tb.v" +SOURCE+=" ../axi_jesd204_rx/axi_jesd204_rx.v" +SOURCE+=" ../axi_jesd204_rx/jesd204_up_rx.v" +SOURCE+=" ../axi_jesd204_rx/jesd204_up_rx_lane.v" +SOURCE+=" ../axi_jesd204_rx/jesd204_up_ilas_mem.v" +SOURCE+=" ../axi_jesd204_common/jesd204_up_common.v" +SOURCE+=" ../axi_jesd204_common/jesd204_up_sysref.v" +SOURCE+=" ../../common/up_clock_mon.v" +SOURCE+=" ../../common/up_axi.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_data.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v new file mode 100644 index 000000000..0e8051cca --- /dev/null +++ b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v @@ -0,0 +1,301 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module axi_jesd204_rx_tb; + parameter VCD_FILE = "axi_jesd204_rx_regmap_tb.vcd"; + parameter NUM_LANES = 2; + + `define TIMEOUT 1000000 + `include "tb_base.v" + + wire s_axi_aclk = clk; + wire s_axi_aresetn = ~reset; + + reg s_axi_awvalid = 1'b0; + reg s_axi_wvalid = 1'b0; + reg [13:0] s_axi_awaddr = 'h00; + reg [31:0] s_axi_wdata = 'h00; + wire [1:0] s_axi_bresp; + wire s_axi_awready; + wire s_axi_wready; + wire s_axi_bready = 1'b1; + wire [3:0] s_axi_wstrb = 4'b1111; + wire [2:0] s_axi_awprot = 3'b000; + wire [2:0] s_axi_arprot = 3'b000; + wire [1:0] s_axi_rresp; + wire [31:0] s_axi_rdata; + + task write_reg; + input [31:0] addr; + input [31:0] value; + begin + @(posedge s_axi_aclk) + s_axi_awvalid <= 1'b1; + s_axi_wvalid <= 1'b1; + s_axi_awaddr <= addr; + s_axi_wdata <= value; + @(posedge s_axi_aclk) + while (s_axi_awvalid || s_axi_wvalid) begin + @(posedge s_axi_aclk) + if (s_axi_awready) + s_axi_awvalid <= 1'b0; + if (s_axi_wready) + s_axi_wvalid <= 1'b0; + end + end + endtask + + reg [13:0] s_axi_araddr = 'h0; + reg s_axi_arvalid = 'h0; + reg s_axi_rready = 'h0; + wire s_axi_arready; + wire s_axi_rvalid; + + task read_reg; + input [31:0] addr; + output [31:0] value; + begin + s_axi_arvalid <= 1'b1; + s_axi_araddr <= addr; + s_axi_rready <= 1'b1; + @(posedge s_axi_aclk) #0; + while (s_axi_arvalid) begin + if (s_axi_arready == 1'b1) begin + s_axi_arvalid <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + + while (s_axi_rready) begin + if (s_axi_rvalid == 1'b1) begin + value <= s_axi_rdata; + s_axi_rready <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + end + endtask + + task read_reg_check; + input [31:0] addr; + output match; + reg [31:0] value; + reg [31:0] expected; + begin + read_reg(addr, value); + expected = expected_reg_mem[addr[13:2]]; + match <= value === expected; + end + endtask + + reg read_match = 1'b1; + + always @(posedge clk) begin + if (read_match == 1'b0) begin + failed <= 1'b1; + end + end + + reg [31:0] expected_reg_mem[0:1023]; + + task set_reset_reg_value; + input [31:0] addr; + input [31:0] value; + begin + expected_reg_mem[addr[13:2]] <= value; + end + endtask + + task initialize_expected_reg_mem; + integer i; + begin + for (i = 0; i < 1024; i = i + 1) + expected_reg_mem[i] <= 'h00; + /* Non zero power-on-reset values */ + set_reset_reg_value('h00, 32'h00010061); /* PCORE version register */ + set_reset_reg_value('h0c, 32'h32303452); /* PCORE magic register */ + set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */ + set_reset_reg_value('h40, 32'h00000100); /* Elastic buffer size */ + set_reset_reg_value('h14, 'h2); /* Datapath width */ + set_reset_reg_value('hc0, 'h1); /* Core reset */ + set_reset_reg_value('hc4, 'h1); /* Core state */ +// set_reset_reg_value('hc8, 'h28000); /* clock monitor */ + set_reset_reg_value('h210, 'h3); /* OCTETS_PER_MULTIFRAME */ + end + endtask + + task check_all_registers; + integer i; + begin + for (i = 0; i < 'h400; i = i + 4) begin + read_reg_check(i, read_match); + end + end + endtask + + task write_reg_and_update; + input [31:0] addr; + input [31:0] value; + integer i; + begin + write_reg(addr, value); + expected_reg_mem[addr[13:2]] <= value; + + if (addr == 'hc0) begin + expected_reg_mem['hc4/4][0] <= value[0]; + end + end + endtask + + task invert_register; + input [31:0] addr; + reg [31:0] value; + begin + read_reg(addr, value); + write_reg(addr, ~value); + end + endtask + + task invert_all_registers; + integer i; + begin + for (i = 0; i < 'h400; i = i + 4) begin + invert_register(i); + end + end + endtask + + integer i; + initial begin + initialize_expected_reg_mem(); + @(posedge s_axi_aresetn) + check_all_registers(); + + /* Check scratch */ + write_reg_and_update('h08, 32'h12345678); + check_all_registers(); + + /* Check IRQ mask */ + write_reg_and_update('h80, 32'h0); + check_all_registers(); + + /* Check lanes enable */ + write_reg_and_update('h200, {NUM_LANES{1'b1}}); + check_all_registers(); + + /* Check JESD common config */ + write_reg_and_update('h210, 32'hff03ff); + check_all_registers(); + write_reg_and_update('h214, 32'h03); + check_all_registers(); + + /* Check JESD RX configuration */ + write_reg_and_update('h240, 32'h103fc); + check_all_registers(); + + /* Reset core */ + write_reg_and_update('hc0, 32'h0); + check_all_registers(); + + /* Should be read-only when core is out of reset */ + invert_register('h200); + invert_register('h204); + invert_register('h210); + invert_register('h240); + + check_all_registers(); + + /* Check that reset works for all registers */ + do_trigger_reset(); + initialize_expected_reg_mem(); + check_all_registers(); + invert_all_registers(); + do_trigger_reset(); + check_all_registers(); + end + + reg core_clk = 1'b0; + always @(*) #4 core_clk <= ~core_clk; + + axi_jesd204_rx #( + .NUM_LANES(NUM_LANES) + ) i_axi ( + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awprot(s_axi_awprot), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wready(s_axi_wready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bresp(s_axi_bresp), + .s_axi_bready(s_axi_bready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arprot(s_axi_arprot), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rdata(s_axi_rdata), + + .core_clk(core_clk), + + .core_ilas_config_valid(1'b0), + .core_ilas_config_addr(2'b00), + .core_ilas_config_data(2'b00), + + .core_event_sysref_alignment_error(1'b0), + .core_event_sysref_edge(1'b0), + + .core_status_ctrl_state('h00), + .core_status_lane_cgs_state('h00), + .core_status_lane_ifs_ready({NUM_LANES{1'b0}}), + .core_status_lane_latency('h00) + ); + +endmodule diff --git a/library/jesd204/tb/axi_jesd204_tx_regmap_tb b/library/jesd204/tb/axi_jesd204_tx_regmap_tb new file mode 100755 index 000000000..5d951bff0 --- /dev/null +++ b/library/jesd204/tb/axi_jesd204_tx_regmap_tb @@ -0,0 +1,15 @@ +#!/bin/bash + +SOURCE="axi_jesd204_tx_regmap_tb.v" +SOURCE+=" ../axi_jesd204_tx/axi_jesd204_tx.v" +SOURCE+=" ../axi_jesd204_tx/jesd204_up_tx.v" +SOURCE+=" ../axi_jesd204_common/jesd204_up_common.v" +SOURCE+=" ../axi_jesd204_common/jesd204_up_sysref.v" +SOURCE+=" ../../common/up_axi.v" +SOURCE+=" ../../common/up_clock_mon.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_data.v" +SOURCE+=" ../../util_cdc/sync_event.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v new file mode 100644 index 000000000..7dcbed8a6 --- /dev/null +++ b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v @@ -0,0 +1,354 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module axi_jesd204_tx_tb; + parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd"; + parameter NUM_LANES = 2; + + `define TIMEOUT 1000000 + `include "tb_base.v" + + reg [1:0] core_status_state = 2'b00; + reg core_status_sync = 1'b0; + + wire s_axi_aclk = clk; + wire s_axi_aresetn = ~reset; + + reg s_axi_awvalid = 1'b0; + reg s_axi_wvalid = 1'b0; + reg [13:0] s_axi_awaddr = 'h00; + reg [31:0] s_axi_wdata = 'h00; + wire [1:0] s_axi_bresp; + wire s_axi_awready; + wire s_axi_wready; + wire s_axi_bready = 1'b1; + wire [3:0] s_axi_wstrb = 4'b1111; + wire [2:0] s_axi_awprot = 3'b000; + wire [2:0] s_axi_arprot = 3'b000; + wire [1:0] s_axi_rresp; + wire [31:0] s_axi_rdata; + + task write_reg; + input [31:0] addr; + input [31:0] value; + begin + @(posedge s_axi_aclk) + s_axi_awvalid <= 1'b1; + s_axi_wvalid <= 1'b1; + s_axi_awaddr <= addr; + s_axi_wdata <= value; + @(posedge s_axi_aclk) + while (s_axi_awvalid || s_axi_wvalid) begin + @(posedge s_axi_aclk) + if (s_axi_awready) + s_axi_awvalid <= 1'b0; + if (s_axi_wready) + s_axi_wvalid <= 1'b0; + end + end + endtask + + reg [13:0] s_axi_araddr = 'h0; + reg s_axi_arvalid = 'h0; + reg s_axi_rready = 'h0; + wire s_axi_arready; + wire s_axi_rvalid; + + task read_reg; + input [31:0] addr; + output [31:0] value; + begin + s_axi_arvalid <= 1'b1; + s_axi_araddr <= addr; + s_axi_rready <= 1'b1; + @(posedge s_axi_aclk) #0; + while (s_axi_arvalid) begin + if (s_axi_arready == 1'b1) begin + s_axi_arvalid <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + + while (s_axi_rready) begin + if (s_axi_rvalid == 1'b1) begin + value <= s_axi_rdata; + s_axi_rready <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + end + endtask + + task read_reg_check; + input [31:0] addr; + output match; + reg [31:0] value; + reg [31:0] expected; + begin + read_reg(addr, value); + expected = expected_reg_mem[addr[13:2]]; + match <= value === expected; + end + endtask + + reg read_match = 1'b1; + + always @(posedge clk) begin + if (read_match == 1'b0) begin + failed <= 1'b1; + end + end + + reg [31:0] expected_reg_mem[0:1023]; + + task set_reset_reg_value; + input [31:0] addr; + input [31:0] value; + begin + expected_reg_mem[addr[13:2]] <= value; + end + endtask + + task initialize_expected_reg_mem; + integer i; + begin + for (i = 0; i < 1024; i = i + 1) + expected_reg_mem[i] <= 'h00; + /* Non zero power-on-reset values */ + set_reset_reg_value('h00, 32'h00010061); /* PCORE version register */ + set_reset_reg_value('h0c, 32'h32303454); /* PCORE magic register */ + set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */ + set_reset_reg_value('h14, 'h2); /* Datapath width */ + set_reset_reg_value('hc0, 'h1); /* Link disable */ + set_reset_reg_value('hc4, 'h1); /* Core state */ +// set_reset_reg_value('hc8, 'h80000); /* clock monitor */ + set_reset_reg_value('h210, 'h3); /* OCTETS_PER_MULTIFRAME */ + + set_reset_reg_value('h244, 'h3); /* MFRAMES_PER_ILAS */ + end + endtask + + task check_all_registers; + integer i; + begin + for (i = 0; i < 'h400; i = i + 4) begin + read_reg_check(i, read_match); + end + end + endtask + + task write_reg_and_update; + input [31:0] addr; + input [31:0] value; + integer i; + begin + write_reg(addr, value); + expected_reg_mem[addr[13:2]] <= value; + + /* Special case for ILAS */ + if (addr >= 'h310 && addr < 'h310 + 32 * NUM_LANES) begin + for (i = 0; i < NUM_LANES; i = i + 1) begin + case (addr[3:2]) + 2'b01: expected_reg_mem['h310/4 + i * 8 + 1][31:5] <= value[31:5]; + 2'b11: expected_reg_mem['h310/4 + i * 8 + 3][23:0] <= value[23:0]; + default: expected_reg_mem['h310/4 + i * 8 + addr[3:2]] <= value; + endcase + end + end + + if (addr == 'hc0) begin + expected_reg_mem['hc4/4][0] <= value[0]; + end + end + endtask + + task invert_register; + input [31:0] addr; + reg [31:0] value; + begin + read_reg(addr, value); + write_reg(addr, ~value); + end + endtask + + task invert_all_registers; + integer i; + begin + for (i = 0; i < 'h400; i = i + 4) begin + invert_register(i); + end + end + endtask + + integer i; + initial begin + initialize_expected_reg_mem(); + @(posedge s_axi_aresetn) + check_all_registers(); + + /* Check scratch */ + write_reg_and_update('h08, 32'h12345678); + check_all_registers(); + + /* Check IRQ mask */ + write_reg_and_update('h80, 32'h0); + check_all_registers(); + + /* Check lanes disable */ + write_reg_and_update('h200, {NUM_LANES{1'b1}}); + check_all_registers(); + + /* Check JESD common config */ + write_reg_and_update('h210, 32'hff03ff); + check_all_registers(); + write_reg_and_update('h214, 32'h03); + check_all_registers(); + + /* Check JESD TX configuration */ + write_reg_and_update('h240, 32'h07); + check_all_registers(); + + /* Check mframes per ILAS - RO at the moment */ + write_reg('h244, 32'hff); + check_all_registers(); + + /* Check status register */ + core_status_state = 2'b01; + set_reset_reg_value('h280, 32'h00000001); + check_all_registers(); + core_status_state = 2'b10; + set_reset_reg_value('h280, 32'h00000002); + check_all_registers(); + core_status_state = 2'b11; + set_reset_reg_value('h280, 32'h00000003); + check_all_registers(); + core_status_state = 2'b00; + set_reset_reg_value('h280, 32'h00000000); + check_all_registers(); + + core_status_sync = 1'b1; + set_reset_reg_value('h280, 32'h00000010); + check_all_registers(); + core_status_sync = 1'b0; + set_reset_reg_value('h280, 32'h00000000); + check_all_registers(); + + /* ILAS register */ + for (i = 0; i < NUM_LANES; i = i + 1) begin + write_reg_and_update('h310 + i * 32, 32'h0fff0000); + write_reg_and_update('h314 + i * 32, 32'h1fff9f1f ^ i); + write_reg_and_update('h318 + i * 32, 32'hffffdfff ^ i); + write_reg_and_update('h31c + i * 32, 32'h0f00009f ^ (2 << 24)); + end + check_all_registers(); + + /* Reset core */ + write_reg_and_update('hc0, 32'h0); + check_all_registers(); + + /* Should be read-only when core is out of reset */ + invert_register('h200); + invert_register('h210); + invert_register('h214); + invert_register('h240); + invert_register('h244); + for (i = 0; i < NUM_LANES; i = i + 1) begin + invert_register('h310 + i * 32); + invert_register('h314 + i * 32); + invert_register('h318 + i * 32); + invert_register('h31c + i * 32); + end + + check_all_registers(); + + /* Check that reset works for all registers */ + do_trigger_reset(); + initialize_expected_reg_mem(); + check_all_registers(); + invert_all_registers(); + do_trigger_reset(); + check_all_registers(); + end + + reg core_clk = 1'b0; + always @(*) #4 core_clk <= ~core_clk; + + axi_jesd204_tx #( + .NUM_LANES(NUM_LANES) + ) i_axi ( + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awprot(s_axi_awprot), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wready(s_axi_wready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bresp(s_axi_bresp), + .s_axi_bready(s_axi_bready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arprot(s_axi_arprot), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rdata(s_axi_rdata), + + .core_clk(core_clk), + + .core_ilas_config_rd(1'b1), + .core_ilas_config_addr(2'b00), + + .core_event_sysref_alignment_error(1'b0), + .core_event_sysref_edge(1'b0), + + .core_status_state(core_status_state), + .core_status_sync(core_status_sync) + ); + +endmodule diff --git a/library/jesd204/tb/loopback_tb b/library/jesd204/tb/loopback_tb new file mode 100755 index 000000000..2303f3d7e --- /dev/null +++ b/library/jesd204/tb/loopback_tb @@ -0,0 +1,15 @@ +#!/bin/bash + +SOURCE="loopback_tb.v" +SOURCE+=" ../jesd204_common/lmfc.v ../jesd204_common/scrambler.v ../jesd204_common/eof.v" +SOURCE+=" ../jesd204_common/pipeline_stage.v" +SOURCE+=" ../jesd204_rx/rx.v ../jesd204_rx/rx_lane.v" +SOURCE+=" ../jesd204_rx/ilas_monitor.v ../jesd204_rx/align_mux.v ../jesd204_rx/rx_cgs.v" +SOURCE+=" ../jesd204_rx/rx_ctrl.v ../jesd204_rx/elastic_buffer.v ../jesd204_rx/lane_latency_monitor.v" +SOURCE+=" ../jesd204_rx_static_config/rx_static_config.v" +SOURCE+=" ../jesd204_tx/tx.v ../jesd204_tx/tx_ctrl.v ../jesd204_tx/tx_lane.v" +SOURCE+=" ../jesd204_tx_static_config/tx_static_config.v" +SOURCE+=" ../jesd204_tx_static_config/ilas_cfg_static.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/loopback_tb.v b/library/jesd204/tb/loopback_tb.v new file mode 100644 index 000000000..cb4b1b5a5 --- /dev/null +++ b/library/jesd204/tb/loopback_tb.v @@ -0,0 +1,311 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module loopback_tb; + parameter VCD_FILE = "loopback_tb.vcd"; + parameter NUM_LANES = 4; + parameter OCTETS_PER_FRAME = 4; + parameter FRAMES_PER_MULTIFRAME = 16; + parameter ENABLE_SCRAMBLER = 1; + parameter BUFFER_EARLY_RELEASE = 1; + parameter LANE_DELAY = 1; + + localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 4; + localparam TX_LATENCY = 3; + localparam RX_LATENCY = 3; + localparam BASE_LATENCY = TX_LATENCY + RX_LATENCY; + + `include "tb_base.v" + + reg [5:0] tx_counter = 'h00; + reg [5:0] rx_counter = 'h00; + reg [NUM_LANES*32-1:0] rx_mask = 'hffff0000; + wire tx_ready; + wire rx_valid; + wire [NUM_LANES*32-1:0] rx_data; + reg data_mismatch = 1'b1; + + always @(posedge clk) begin + if (sync == 1'b0) begin + tx_counter <= 'h00000000; + end else if (tx_ready == 1'b1) begin + tx_counter <= tx_counter + 1'b1; + end + end + + always @(posedge clk) begin + if (sync == 1'b0) begin + rx_counter <= 'h00000000; + if (ENABLE_SCRAMBLER == 1'b1) begin + rx_mask <= {NUM_LANES{32'hffff0000}}; // First two octets are invalid due to scrambling + end else begin + rx_mask <= {NUM_LANES{32'hffffffff}}; + end + end else if (rx_valid == 1'b1) begin + rx_counter <= rx_counter + 1'b1; + rx_mask <= {NUM_LANES{32'hffffffff}}; + end + end + + wire [31:0] tx_data = {tx_counter,2'h3,tx_counter,2'h2,tx_counter,2'h1,tx_counter,2'h0}; + wire [31:0] rx_ref_data = {rx_counter,2'h3,rx_counter,2'h2,rx_counter,2'h1,rx_counter,2'h0}; + + wire [NUM_LANES*32-1:0] phy_data_out; + wire [NUM_LANES*4-1:0] phy_charisk_out; + wire [NUM_LANES*32-1:0] phy_data_in; + wire [NUM_LANES*4-1:0] phy_charisk_in; + wire sync; + + reg [5:0] sysref_counter = 'h00; + reg sysref_rx = 1'b0; + reg sysref_tx = 1'b0; + + always @(posedge clk) begin + if (sysref_counter == 'h2f) + sysref_rx <= ~sysref_rx; + sysref_counter <= sysref_counter + 1'b1; + sysref_tx <= sysref_rx; + end + + localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES; + + reg [10:0] phy_delay_fifo_wr; + reg [36*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1]; + + always @(posedge clk) begin + phy_delay_fifo[phy_delay_fifo_wr] <= {phy_charisk_out,phy_data_out}; + + if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin + phy_delay_fifo_wr <= 'h00; + end else begin + phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1; + end + end + + genvar i; + generate for (i = 0; i < NUM_LANES; i = i + 1) begin + localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY); + assign phy_data_in[32*i+31:32*i] = + phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][32*i+31:32*i]; + assign phy_charisk_in[4*i+3:4*i] = + phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][4*i+3+NUM_LANES*32:4*i+32*NUM_LANES]; + end endgenerate + + wire [NUM_LANES-1:0] tx_cfg_lanes_disable; + wire [7:0] tx_cfg_beats_per_multiframe; + wire [7:0] tx_cfg_octets_per_frame; + wire [7:0] tx_cfg_lmfc_offset; + wire tx_cfg_sysref_required; + wire tx_cfg_continuous_cgs; + wire tx_cfg_continuous_ilas; + wire tx_cfg_skip_ilas; + wire [7:0] tx_cfg_mframes_per_ilas; + wire tx_cfg_disable_char_replacement; + wire tx_cfg_disable_scrambler; + + wire tx_ilas_config_rd; + wire [1:0] tx_ilas_config_addr; + wire [32*NUM_LANES-1:0] tx_ilas_config_data; + + jesd204_tx_static_config #( + .NUM_LANES(NUM_LANES), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME), + .SCR(ENABLE_SCRAMBLER) + ) i_tx_cfg ( + .clk(clk), + + .cfg_lanes_disable(tx_cfg_lanes_disable), + .cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe), + .cfg_octets_per_frame(tx_cfg_octets_per_frame), + .cfg_lmfc_offset(tx_cfg_lmfc_offset), + .cfg_sysref_required(tx_cfg_sysref_required), + .cfg_continuous_cgs(tx_cfg_continuous_cgs), + .cfg_continuous_ilas(tx_cfg_continuous_ilas), + .cfg_skip_ilas(tx_cfg_skip_ilas), + .cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas), + .cfg_disable_char_replacement(tx_cfg_disable_char_replacement), + .cfg_disable_scrambler(tx_cfg_disable_scrambler), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data) + ); + + jesd204_tx #( + .NUM_LANES(NUM_LANES) + ) i_tx ( + .clk(clk), + .reset(reset), + + .cfg_lanes_disable(tx_cfg_lanes_disable), + .cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe), + .cfg_octets_per_frame(tx_cfg_octets_per_frame), + .cfg_lmfc_offset(tx_cfg_lmfc_offset), + .cfg_sysref_required(tx_cfg_sysref_required), + .cfg_continuous_cgs(tx_cfg_continuous_cgs), + .cfg_continuous_ilas(tx_cfg_continuous_ilas), + .cfg_skip_ilas(tx_cfg_skip_ilas), + .cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas), + .cfg_disable_char_replacement(tx_cfg_disable_char_replacement), + .cfg_disable_scrambler(tx_cfg_disable_scrambler), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data), + + .ctrl_manual_sync_request(1'b0), + + .tx_ready(tx_ready), + .tx_data({NUM_LANES{tx_data}}), + + .sync(sync), + .sysref(sysref_tx), + + .phy_data(phy_data_out), + .phy_charisk(phy_charisk_out) + ); + + wire [NUM_LANES-1:0] rx_cfg_lanes_disable; + wire [7:0] rx_cfg_beats_per_multiframe; + wire [7:0] rx_cfg_octets_per_frame; + wire [7:0] rx_cfg_lmfc_offset; + wire rx_sysref_required; + wire rx_cfg_disable_scrambler; + wire rx_cfg_disable_char_replacement; + wire rx_cfg_buffer_early_release; + wire [7:0] rx_cfg_buffer_delay; + wire [NUM_LANES-1:0] rx_status_lane_ifs_ready; + wire [NUM_LANES*14-1:0] rx_status_lane_latency; + + jesd204_rx_static_config #( + .NUM_LANES(NUM_LANES), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME), + .SCR(ENABLE_SCRAMBLER), + .BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE) + ) i_rx_cfg ( + .clk(clk), + + .cfg_lanes_disable(rx_cfg_lanes_disable), + .cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe), + .cfg_octets_per_frame(rx_cfg_octets_per_frame), + .cfg_lmfc_offset(rx_cfg_lmfc_offset), + .cfg_sysref_required(rx_cfg_sysref_required), + .cfg_disable_scrambler(rx_cfg_disable_scrambler), + .cfg_disable_char_replacement(rx_cfg_disable_char_replacement), + .cfg_buffer_delay(rx_cfg_buffer_delay), + .cfg_buffer_early_release(rx_cfg_buffer_early_release) + ); + + jesd204_rx #( + .NUM_LANES(NUM_LANES) + ) i_rx ( + .clk(clk), + .reset(reset), + + .cfg_lanes_disable(rx_cfg_lanes_disable), + .cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe), + .cfg_octets_per_frame(rx_cfg_octets_per_frame), + .cfg_lmfc_offset(rx_cfg_lmfc_offset), + .cfg_sysref_required(rx_cfg_sysref_required), + .cfg_disable_scrambler(rx_cfg_disable_scrambler), + .cfg_disable_char_replacement(rx_cfg_disable_char_replacement), + .cfg_buffer_delay(rx_cfg_buffer_delay), + .cfg_buffer_early_release(rx_cfg_buffer_early_release), + + .sync(sync), + .sysref(sysref_rx), + + .rx_data(rx_data), + .rx_valid(rx_valid), + + .phy_ready(1'b1), + + .phy_data(phy_data_in), + .phy_charisk(phy_charisk_in), + .phy_notintable({NUM_LANES{4'b0000}}), + .phy_disperr({NUM_LANES{4'b0000}}), + + .status_lane_ifs_ready(rx_status_lane_ifs_ready), + .status_lane_latency(rx_status_lane_latency) + ); + + always @(posedge clk) begin + if (reset == 1'b1) begin + data_mismatch <= 1'b0; + end else if (rx_valid == 1'b1) begin + if ((rx_data & rx_mask) !== ({NUM_LANES{rx_ref_data}} & rx_mask)) begin + data_mismatch <= 1'b1; + end + end + end + + reg [NUM_LANES-1:0] lane_latency_match; + + generate for (i = 0; i < NUM_LANES; i = i + 1) begin + localparam LANE_OFFSET = BASE_LATENCY + LANE_DELAY + i; + localparam LANE_OFFSET_MFRAMES = LANE_OFFSET / BEATS_PER_MULTIFRAME + 1; + localparam LANE_OFFSET_BEATS = LANE_OFFSET % BEATS_PER_MULTIFRAME; + + always @(posedge clk) begin + if (rx_status_lane_ifs_ready[i] == 1'b1 && + rx_status_lane_latency[i*14+13:i*14+10] == LANE_OFFSET_MFRAMES && + rx_status_lane_latency[i*14+9:i*14+2] == LANE_OFFSET_BEATS) begin + lane_latency_match[i] <= 1'b1; + end else begin + lane_latency_match[i] <= 1'b0; + end + end + end endgenerate + + always @(*) begin + if (rx_valid !== 1'b1 || tx_ready !== 1'b1 || data_mismatch == 1'b1 || + &lane_latency_match != 1'b1) begin + failed <= 1'b1; + end else begin + failed <= 1'b0; + end + end +endmodule diff --git a/library/jesd204/tb/run_tb.sh b/library/jesd204/tb/run_tb.sh new file mode 100644 index 000000000..d4685c3a3 --- /dev/null +++ b/library/jesd204/tb/run_tb.sh @@ -0,0 +1,8 @@ +NAME=`basename $0` + +mkdir -p run +mkdir -p vcd +iverilog ${SOURCE} -o run/run_${NAME} $1 || exit 1 + +cd vcd +../run/run_${NAME} diff --git a/library/jesd204/tb/rx_cgs_tb b/library/jesd204/tb/rx_cgs_tb new file mode 100755 index 000000000..f471fdd67 --- /dev/null +++ b/library/jesd204/tb/rx_cgs_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="rx_cgs_tb.v" +SOURCE+=" ../jesd204_rx/rx_cgs.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/rx_cgs_tb.v b/library/jesd204/tb/rx_cgs_tb.v new file mode 100644 index 000000000..506101323 --- /dev/null +++ b/library/jesd204/tb/rx_cgs_tb.v @@ -0,0 +1,93 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module rx_cgs_tb; + parameter VCD_FILE = "rx_cgs_tb.vcd"; + + `define TIMEOUT 1000 + `include "tb_base.v" + + reg [3:0] char_is_error = 4'b0000; + reg [3:0] char_is_cgs = 4'b1111; + + integer counter = 'h00; + wire ready; + reg ready_prev = 1'b0; +/* + always @(posedge clk) begin + if ($random % 2 == 0) + char_is_error <= 4'b1111; + else + char_is_error <= 4'b0000; + end +*/ + always @(posedge clk) begin + counter <= counter + 1; + if (counter == 'h20) begin + char_is_cgs <= 4'b0001; + end else if (counter > 'h20) begin + char_is_cgs <= 4'b0000; + end + end + + jesd204_rx_cgs i_rx_cgs ( + .clk(clk), + .reset(reset), + .char_is_cgs(char_is_cgs), + .char_is_error(char_is_error), + + .ready(ready) + ); + + reg lost_sync = 1'b0; + + always @(posedge clk) begin + ready_prev <= ready; + if (ready_prev == 1'b1 && ready == 1'b0) begin + lost_sync <= 1'b1; + end + failed <= lost_sync | ~ready; + end + +endmodule diff --git a/library/jesd204/tb/rx_ctrl_tb b/library/jesd204/tb/rx_ctrl_tb new file mode 100755 index 000000000..8d5627140 --- /dev/null +++ b/library/jesd204/tb/rx_ctrl_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="rx_ctrl_tb.v" +SOURCE+=" ../jesd204_rx/rx_ctrl.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/rx_ctrl_tb.v b/library/jesd204/tb/rx_ctrl_tb.v new file mode 100644 index 000000000..9fd132dc7 --- /dev/null +++ b/library/jesd204/tb/rx_ctrl_tb.v @@ -0,0 +1,112 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module rx_ctrl_tb; + parameter VCD_FILE = "rx_ctrl_tb.vcd"; + + `include "tb_base.v" + + integer phy_reset_counter = 'h00; + integer align_counter = 'h00; + integer cgs_counter = 'h00; + + reg phy_ready = 1'b0; + reg aligned = 1'b0; + reg cgs_ready = 1'b0; + + wire en_align; + wire cgs_reset; + + always @(posedge clk) begin + if (reset == 1'b1) begin + phy_reset_counter <= 'h00; + phy_ready <= 1'b0; + end else begin + if (phy_reset_counter == 'h7) begin + phy_ready <= 1'b1; + end else begin + phy_reset_counter <= phy_reset_counter + 1'b1; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + aligned <= 1'b0; + align_counter <= 'h00; + end else if (phy_ready == 1'b1) begin + if (en_align == 1'b1) begin + if (align_counter == 'h20) begin + aligned <= 1'b1; + end else begin + align_counter <= align_counter + 1; + end + end + end + end + + + always @(posedge clk or posedge cgs_reset) begin + if (cgs_reset == 1'b1) begin + cgs_counter <= 'h00; + cgs_ready <= 1'b0; + end else begin + if (cgs_counter == 'h20) begin + cgs_ready <= 1'b1; + end else begin + cgs_counter <= cgs_counter + 1; + end + end + end + + jesd204_rx_ctrl i_rx_ctrl ( + .clk(clk), + .reset(reset), + .phy_ready(phy_ready), + .phy_en_char_align(en_align), + .cgs_reset(cgs_reset), + .cgs_ready(cgs_ready) + ); + +endmodule diff --git a/library/jesd204/tb/rx_lane_tb b/library/jesd204/tb/rx_lane_tb new file mode 100755 index 000000000..3c3c3b906 --- /dev/null +++ b/library/jesd204/tb/rx_lane_tb @@ -0,0 +1,10 @@ +#!/bin/bash + +SOURCE="rx_lane_tb.v " +SOURCE+=" ../jesd204_rx/rx_lane.v ../jesd204_rx/rx_cgs.v ../jesd204_rx/elastic_buffer.v" +SOURCE+=" ../jesd204_rx/align_mux.v ../jesd204_rx/ilas_monitor.v" +SOURCE+=" ../jesd204_common/scrambler.v" +SOURCE+=" ../jesd204_common/pipeline_stage.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/rx_lane_tb.v b/library/jesd204/tb/rx_lane_tb.v new file mode 100644 index 000000000..2b2616e73 --- /dev/null +++ b/library/jesd204/tb/rx_lane_tb.v @@ -0,0 +1,104 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module rx_lane_tb; + parameter VCD_FILE = "rx_lane_tb.vcd"; + + `include "tb_base.v" + + reg [31:0] data = {4{{3'd5,5'd28}}}; + reg [3:0] disperr = 4'b0000; + reg [3:0] charisk = 4'b1111; + + integer counter = 'h00; + wire [31:0] counter2 = (counter - 'h20) * 4; + +/* always @(posedge clk) begin + if ($random % 10 == 0) + disperr <= 4'b1111; + else + disperr <= 4'b0000; + end*/ + + always @(posedge clk) begin + counter <= counter + 1; + if (counter == 'h20) begin + charisk <= 'h0001; + data[31:8] <= {{24'h020100}}; + end else if (counter == 'h21) begin + charisk <= 'h0000; + data[31:0] <= {{32'h06050403}}; + end else if (counter > 'h21) begin + data <= (counter2 + 'h2) << 24 | + (counter2 + 'h1) << 16 | + (counter2 + 'h0) << 8 | + (counter2 - 'h1); + charisk <= 4'b0000; + end + end + + reg buffer_release_n = 1'b0; + wire buffer_ready_n; + + always @(posedge clk) begin + buffer_release_n <= buffer_ready_n; + end + + jesd204_rx_lane i_rx_lane ( + .clk(clk), + + .phy_data(data), + .phy_charisk(charisk), + .phy_disperr(disperr), + .phy_notintable(4'b0000), + + .cgs_reset(reset), + + .buffer_release_n(buffer_release_n), + .buffer_ready_n(buffer_ready_n), + + .cfg_disable_scrambler(1'b0) + ); + +endmodule diff --git a/library/jesd204/tb/rx_tb b/library/jesd204/tb/rx_tb new file mode 100755 index 000000000..50cc3303f --- /dev/null +++ b/library/jesd204/tb/rx_tb @@ -0,0 +1,12 @@ +#!/bin/bash + +SOURCE="rx_tb.v" +SOURCE+=" ../jesd204_common/lmfc.v ../jesd204_common/scrambler.v ../jesd204_common/eof.v" +SOURCE+=" ../jesd204_common/pipeline_stage.v" +SOURCE+=" ../jesd204_rx_static_config/rx_static_config.v " +SOURCE+=" ../jesd204_rx/rx.v ../jesd204_rx/rx_lane.v ../jesd204_rx/lane_latency_monitor.v" +SOURCE+=" ../jesd204_rx/ilas_monitor.v ../jesd204_rx/align_mux.v ../jesd204_rx/rx_cgs.v" +SOURCE+=" ../jesd204_rx/rx_ctrl.v ../jesd204_rx/elastic_buffer.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/rx_tb.v b/library/jesd204/tb/rx_tb.v new file mode 100644 index 000000000..ac7af3c33 --- /dev/null +++ b/library/jesd204/tb/rx_tb.v @@ -0,0 +1,189 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module rx_tb; + parameter VCD_FILE = "rx_tb.vcd"; + parameter NUM_LANES = 1; + parameter OCTETS_PER_FRAME = 8; + parameter FRAMES_PER_MULTIFRAME = 32; + + `include "tb_base.v" + + integer phy_reset_counter = 'h00; + integer align_counter = 'h00; + + reg phy_ready = 1'b0; + reg aligned = 1'b0; + + wire en_align; + + always @(posedge clk) begin + if (reset == 1'b1) begin + phy_reset_counter <= 'h00; + phy_ready <= 1'b0; + end else begin + if (phy_reset_counter == 'h40) begin + phy_ready <= 1'b1; + end else begin + phy_reset_counter <= phy_reset_counter + 1'b1; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + aligned <= 1'b0; + align_counter <= 'h00; + end else if (phy_ready == 1'b1) begin + if (en_align == 1'b1) begin + if (align_counter == 'h20) begin + aligned <= 1'b1; + end else begin + align_counter <= align_counter + 1; + end + end + end + end + + localparam KCHAR_ILAS_START = {3'd0,5'd28}; + localparam KCHAR_LANE_ALIGN = {3'd3,5'd28}; + localparam KCHAR_ILAS_CONFIG = {3'd4,5'd28}; + localparam KCHAR_CGS = {3'd5,5'd28}; + localparam KCHAR_FRAME_ALIGN = {3'd7,5'd28}; + + reg [31:0] data = KCHAR_CGS; + reg [3:0] charisk = 4'b1111; + reg [3:0] disperr = 4'b0000; + reg [3:0] notintable = 4'b0000; + + integer counter = 'h00; + wire [31:0] counter2 = (counter - 'h10) * 4; + + always @(posedge clk) begin + if (sync == 1'b0) begin + counter <= 'h00; + charisk <= 4'b1111; + data <= {KCHAR_CGS,KCHAR_CGS,KCHAR_CGS,KCHAR_CGS}; + end else begin + counter <= counter + 1; + if (counter >= 'h8 && counter < 'h28) begin + if (counter % 'h8 == 'h0) begin + if (counter != 'h10) begin + data <= {24'h00,KCHAR_ILAS_START}; + charisk <= 4'b0001; + end else begin + data <= {16'hffaa,KCHAR_ILAS_CONFIG,KCHAR_ILAS_START}; + charisk <= 4'b0011; + end + end else if (counter % 'h8 == 'h7) begin + data <= {KCHAR_LANE_ALIGN,24'h00}; + charisk <= 4'b1000; + end else begin + data <= {32'h00}; + charisk <= 4'b0000; + end + end else if (counter > 'h10) begin + data <= (counter2 + 'h2) << 24 | + (counter2 + 'h1) << 16 | + (counter2 + 'h0) << 8 | + (counter2 - 'h1); + charisk <= 4'b0000; + end + end + end + + wire [NUM_LANES-1:0] cfg_lanes_disable; + wire [7:0] cfg_beats_per_multiframe; + wire [7:0] cfg_octets_per_frame; + wire [7:0] cfg_lmfc_offset; + wire cfg_sysref_oneshot; + wire cfg_sysref_required; + wire cfg_buffer_early_release; + wire cfg_disable_scrambler; + + jesd204_rx_static_config #( + .NUM_LANES(NUM_LANES), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME) + ) i_cfg ( + .clk(clk), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_lmfc_offset(cfg_lmfc_offset), + .cfg_sysref_oneshot(cfg_sysref_oneshot), + .cfg_sysref_required(cfg_sysref_required), + .cfg_disable_scrambler(tx_cfg_disable_scrambler), + .cfg_buffer_early_release(rx_buffer_early_release) + ); + + jesd204_rx #( + .NUM_LANES(NUM_LANES) + ) i_rx ( + .clk(clk), + .reset(reset), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_lmfc_offset(cfg_lmfc_offset), + .cfg_sysref_oneshot(cfg_sysref_oneshot), + .cfg_sysref_required(cfg_sysref_required), + .cfg_disable_scrambler(tx_cfg_disable_scrambler), + .cfg_buffer_early_release(rx_buffer_early_release), + + .phy_ready(1'b1), + .phy_en_char_align(en_align), + + .phy_data({NUM_LANES{data}}), + .phy_charisk({NUM_LANES{charisk}}), + .phy_notintable({NUM_LANES{notintable}}), + .phy_disperr({NUM_LANES{disperr}}), + + .sync(sync), + .sysref(sysref) + ); + +endmodule diff --git a/library/jesd204/tb/scrambler_tb b/library/jesd204/tb/scrambler_tb new file mode 100755 index 000000000..63193edd3 --- /dev/null +++ b/library/jesd204/tb/scrambler_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="scrambler_tb.v" +SOURCE+=" ../jesd204_common/scrambler.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/scrambler_tb.v b/library/jesd204/tb/scrambler_tb.v new file mode 100644 index 000000000..4f1f0a45e --- /dev/null +++ b/library/jesd204/tb/scrambler_tb.v @@ -0,0 +1,89 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module scrambler_tb; + parameter VCD_FILE = "scrambler_tb.vcd"; + + `include "tb_base.v" + + reg [31:0] data_in; + reg [31:0] data_out_expected; + wire [31:0] data_scrambled; + wire [31:0] data_out; + + always @(posedge clk) begin + if (reset == 1'b1) begin + data_in <= 'h03020100; + end else begin + data_in <= data_in + {4{8'h04}}; + end + end + + jesd204_scrambler #( + .DESCRAMBLE(0) + ) i_scrambler ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .data_in(data_in), + .data_out(data_scrambled) + ); + + jesd204_scrambler #( + .DESCRAMBLE(1) + ) i_descrambler ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .data_in(data_scrambled), + .data_out(data_out) + ); + + always @(posedge clk) begin + if (data_in != data_out && failed == 1'b0) begin + failed <= 1'b1; + end + end + +endmodule diff --git a/library/jesd204/tb/tb_base.v b/library/jesd204/tb/tb_base.v new file mode 100644 index 000000000..274749b36 --- /dev/null +++ b/library/jesd204/tb/tb_base.v @@ -0,0 +1,94 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + + + reg clk = 1'b1; + reg [3:0] reset_shift = 4'b1111; + reg trigger_reset = 1'b0; + wire reset; + + reg failed = 1'b0; + + reg sysref = 1'b0; + + initial + begin + $dumpfile (VCD_FILE); + $dumpvars; +`ifdef TIMEOUT + #`TIMEOUT +`else + #100000 +`endif + if (failed == 1'b0) + $display("SUCCESS"); + else + $display("FAILED"); + $finish; + end + + always @(*) #10 clk <= ~clk; + always @(posedge clk) begin + if (trigger_reset == 1'b1) begin + reset_shift <= 3'b111; + end else begin + reset_shift <= {reset_shift[2:0],1'b0}; + end + end + + assign reset = reset_shift[3]; + + + initial begin + #1000; + @(posedge clk) sysref <= 1'b1; + @(posedge clk) sysref <= 1'b0; + end + + task do_trigger_reset; + begin + @(posedge clk) trigger_reset <= 1'b1; + @(posedge clk) trigger_reset <= 1'b0; + end + endtask diff --git a/library/jesd204/tb/tx_ctrl_phase_tb b/library/jesd204/tb/tx_ctrl_phase_tb new file mode 100755 index 000000000..abd657b4a --- /dev/null +++ b/library/jesd204/tb/tx_ctrl_phase_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="tx_ctrl_phase_tb.v" +SOURCE+=" ../jesd204_tx/tx_ctrl.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/tx_ctrl_phase_tb.v b/library/jesd204/tb/tx_ctrl_phase_tb.v new file mode 100644 index 000000000..cceaeaff3 --- /dev/null +++ b/library/jesd204/tb/tx_ctrl_phase_tb.v @@ -0,0 +1,210 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +/* + * Regardless of the phase relationship between LMFC and sync the output of the + * ctrl core should be the same as long as the sync signal is in the same lmfc + * cycle. + */ + +module tx_ctrl_phase_tb; + parameter VCD_FILE = "tx_ctrl_phase.vcd"; + parameter NUM_LANES = 1; + parameter BEATS_PER_LMFC = 20; + + `include "tb_base.v" + + reg lmfc_edge = 1'b0; + reg a_sync = 1'b0; + reg b_sync = 1'b0; + + wire [31:0] a_ilas_data; + wire [3:0] a_ilas_charisk; + wire [1:0] a_ilas_config_addr; + wire a_ilas_config_rd; + wire a_tx_ready; + wire a_lane_cgs_enable; + + wire [31:0] b_ilas_data; + wire [3:0] b_ilas_charisk; + wire [1:0] b_ilas_config_addr; + wire b_ilas_config_rd; + wire b_tx_ready; + wire b_lane_cgs_enable; + + reg reset2 = 1'b1; + + integer reset_counter = 0; + integer beat_counter = 0; + integer lmfc_counter = 0; + integer b_offset = 0; + + always @(posedge clk) begin + if (reset2 == 1'b1) begin + if (reset_counter == 7) begin + reset2 <= 1'b0; + reset_counter <= 0; + end else begin + reset_counter <= reset_counter + 1; + end + end + + if (reset2 == 1'b1) begin + beat_counter <= 0; + a_sync <= 1'b0; + b_sync <= 1'b0; + end else begin + beat_counter <= beat_counter + 1'b1; + if (beat_counter == BEATS_PER_LMFC*2) begin + a_sync <= 1'b1; + end + + if (beat_counter == BEATS_PER_LMFC*2 + b_offset) begin + b_sync <= 1'b1; + end + + if (beat_counter == BEATS_PER_LMFC*9) begin + b_offset <= b_offset + 1; + reset2 <= 1'b1; + end + end + + if (reset2 == 1'b1) begin + lmfc_counter <= BEATS_PER_LMFC-3; + end else begin + lmfc_counter <= lmfc_counter + 1; + if (lmfc_counter == BEATS_PER_LMFC-1) begin + lmfc_counter <= 0; + lmfc_edge <= 1'b1; + end else begin + lmfc_edge <= 1'b0; + end + end + end + + jesd204_tx_ctrl i_tx_ctrl_a ( + .clk(clk), + .reset(reset2), + + .sync(a_sync), + .lmfc_edge(lmfc_edge), + + .lane_cgs_enable(a_lane_cgs_enable), + + .tx_ready(a_tx_ready), + + .ilas_data(a_ilas_data), + .ilas_charisk(a_ilas_charisk), + + .ilas_config_addr(a_ilas_config_addr), + .ilas_config_rd(a_ilas_config_rd), + .ilas_config_data('h00), + + .ctrl_manual_sync_request(1'b0), + + .cfg_continuous_cgs(1'b0), + .cfg_continuous_ilas(1'b0), + .cfg_skip_ilas(1'b0), + .cfg_mframes_per_ilas(3) + ); + + jesd204_tx_ctrl i_tx_ctrl_b ( + .clk(clk), + .reset(reset2), + + .sync(b_sync), + .lmfc_edge(lmfc_edge), + + .lane_cgs_enable(b_lane_cgs_enable), + + .tx_ready(b_tx_ready), + + .ilas_data(b_ilas_data), + .ilas_charisk(b_ilas_charisk), + + .ilas_config_addr(b_ilas_config_addr), + .ilas_config_rd(b_ilas_config_rd), + .ilas_config_data('h00), + + .ctrl_manual_sync_request(1'b0), + + .cfg_continuous_cgs(1'b0), + .cfg_continuous_ilas(1'b0), + .cfg_skip_ilas(1'b0), + .cfg_mframes_per_ilas(3) + ); + + reg status = 1'b1; + + always @(*) begin + if (reset2 == 1'b1) begin + status <= 1'b1; + end else if (a_ilas_data != b_ilas_data || + a_ilas_charisk != b_ilas_charisk || + a_ilas_config_addr != b_ilas_config_addr || + a_ilas_config_rd != b_ilas_config_rd || + a_lane_cgs_enable != b_lane_cgs_enable || + a_tx_ready != b_tx_ready) begin + status <= 1'b0; + end + end + + reg message_shown = 1'b0; + + always @(posedge clk) begin + if (status == 1'b0 && message_shown == 1'b0 && b_offset < BEATS_PER_LMFC) begin + $display("FAILED at offset %0d", b_offset); + message_shown <= 1'b1; + end + end + + always @(posedge clk) begin + if (b_offset == BEATS_PER_LMFC+1) begin + if (message_shown == 1'b0) + $display("SUCCESS"); + $finish; + end + end + +endmodule diff --git a/library/jesd204/tb/tx_tb b/library/jesd204/tb/tx_tb new file mode 100755 index 000000000..3f2872ea3 --- /dev/null +++ b/library/jesd204/tb/tx_tb @@ -0,0 +1,9 @@ +#!/bin/bash + +SOURCE="tx_tb.v" +SOURCE+=" ../jesd204_common/lmfc.v ../jesd204_common/scrambler.v ../jesd204_common/eof.v" +SOURCE+=" ../jesd204_tx/tx.v ../jesd204_tx/tx_ctrl.v ../jesd204_tx/tx_lane.v" +SOURCE+=" ../jesd204_tx_static_config/tx_static_config.v ../jesd204_tx_static_config/ilas_cfg_static.v" + +cd `dirname $0` +source run_tb.sh diff --git a/library/jesd204/tb/tx_tb.v b/library/jesd204/tb/tx_tb.v new file mode 100644 index 000000000..b8c8b0b20 --- /dev/null +++ b/library/jesd204/tb/tx_tb.v @@ -0,0 +1,147 @@ +// +// The ADI JESD204 Core is released under the following license, which is +// different than all other HDL cores in this repository. +// +// Please read this, and understand the freedoms and responsibilities you have +// by using this source code/core. +// +// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +// +// This core is free software, you can use run, copy, study, change, ask +// questions about and improve this core. Distribution of source, or resulting +// binaries (including those inside an FPGA or ASIC) require you to release the +// source of the entire project (excluding the system libraries provide by the +// tools/compiler/FPGA vendor). These are the terms of the GNU General Public +// License version 2 as published by the Free Software Foundation. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License version 2 +// along with this source code, and binary. If not, see +// . +// +// Commercial licenses (with commercial support) of this JESD204 core are also +// available under terms different than the General Public License. (e.g. they +// do not require you to accompany any image (FPGA or ASIC) using the JESD204 +// core with any corresponding source code.) For these alternate terms you must +// purchase a license from Analog Devices Technology Licensing Office. Users +// interested in such a license should contact jesd204-licensing@analog.com for +// more information. This commercial license is sub-licensable (if you purchase +// chips from Analog Devices, incorporate them into your PCB level product, and +// purchase a JESD204 license, end users of your product will also have a +// license to use this core in a commercial setting without releasing their +// source code). +// +// In addition, we kindly ask you to acknowledge ADI in any program, application +// or publication in which you use this JESD204 HDL core. (You are not required +// to do so; it is up to your common sense to decide whether you want to comply +// with this request or not.) For general publications, we suggest referencing : +// “The design and implementation of the JESD204 HDL Core used in this project +// is copyright © 2016-2017, Analog Devices, Inc.” +// + +module tx_tb; + parameter VCD_FILE = "tx_tb.vcd"; + parameter NUM_LANES = 1; + parameter OCTETS_PER_FRAME = 4; + parameter FRAMES_PER_MULTIFRAME = 32; + + `include "tb_base.v" + + reg [31:0] tx_data = 'h00000000; + wire tx_ready; + + always @(posedge clk) begin + if (reset == 1'b1) begin + tx_data <= 'h00000000; + end else if (tx_ready == 1'b1) begin + tx_data <= tx_data + 1'b1; + end + end + + reg sync = 1'b1; + reg [31:0] counter = 'h00; + + always @(posedge clk) begin + counter <= counter + 1'b1; + if (counter >= 'h10 && counter <= 'h30) begin + sync <= 1'b0; + end else begin + sync <= 1'b1; + end + end + + wire [NUM_LANES-1:0] cfg_lanes_disable; + wire [7:0] cfg_beats_per_multiframe; + wire [7:0] cfg_octets_per_frame; + wire [7:0] cfg_lmfc_offset; + wire cfg_sysref_oneshot; + wire cfg_sysref_required; + wire cfg_continuous_cgs; + wire cfg_continuous_ilas; + wire cfg_skip_ilas; + wire [7:0] cfg_mframes_per_ilas; + wire cfg_disable_char_replacement; + wire cfg_disable_scrambler; + + wire tx_ilas_config_rd; + wire [1:0] tx_ilas_config_addr; + wire [32*NUM_LANES-1:0] tx_ilas_config_data; + + jesd204_tx_static_config #( + .NUM_LANES(NUM_LANES), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME) + ) i_cfg ( + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_lmfc_offset(cfg_lmfc_offset), + .cfg_continuous_cgs(cfg_continuous_cgs), + .cfg_continuous_ilas(cfg_continuous_ilas), + .cfg_skip_ilas(cfg_skip_ilas), + .cfg_mframes_per_ilas(cfg_mframes_per_ilas), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler), + .cfg_sysref_oneshot(cfg_sysref_oneshot), + .cfg_sysref_required(cfg_sysref_required), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data) + ); + + jesd204_tx #( + .NUM_LANES(NUM_LANES) + ) i_tx ( + .clk(clk), + .reset(reset), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_lmfc_offset(cfg_lmfc_offset), + .cfg_continuous_cgs(cfg_continuous_cgs), + .cfg_continuous_ilas(cfg_continuous_ilas), + .cfg_skip_ilas(cfg_skip_ilas), + .cfg_mframes_per_ilas(cfg_mframes_per_ilas), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler), + .cfg_sysref_oneshot(cfg_sysref_oneshot), + .cfg_sysref_required(cfg_sysref_required), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data), + + .tx_ready(tx_ready), + .tx_data({NUM_LANES{tx_data}}), + + .sync(sync), + .sysref(sysref) + ); + + +endmodule