fmcadc5- replaced with axi_adxcvr
Rejeesh Kutty
parent
22e230618c
commit
11b57290f1
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@ -1,23 +1,36 @@
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# ad9625
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create_bd_port -dir I rx_ref_clk_0
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create_bd_port -dir I -from 7 -to 0 rx_data_0_p
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create_bd_port -dir I -from 7 -to 0 rx_data_0_n
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create_bd_port -dir O rx_sync_0
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create_bd_port -dir I rx_ref_clk_1
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create_bd_port -dir I -from 7 -to 0 rx_data_1_p
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create_bd_port -dir I -from 7 -to 0 rx_data_1_n
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create_bd_port -dir O rx_sync_1
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create_bd_port -dir O rx_sysref
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create_bd_port -dir O rx_clk
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# adc peripherals
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set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
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set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
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set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
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set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
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set util_fmcadc5_0_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc5_0_xcvr]
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set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc5_0_xcvr
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set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc5_0_xcvr
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set util_fmcadc5_1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc5_1_xcvr]
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set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc5_1_xcvr
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set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc5_1_xcvr
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set axi_ad9625_0_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_0_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_0_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_0_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_0_xcvr
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set axi_ad9625_1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_1_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_1_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_1_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_1_xcvr
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set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_0_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
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@ -26,6 +39,15 @@ set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 a
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
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set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
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set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
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set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
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set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
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set util_ad9625_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9625_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {256}] $util_ad9625_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9625_cpack
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set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma
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@ -41,221 +63,58 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
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p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 512 18
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# adc common gt
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# reference clocks & resets
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set axi_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_0_gt]
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set_property -dict [list CONFIG.ID {0}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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create_bd_port -dir I rx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_1
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set axi_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_1_gt]
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set_property -dict [list CONFIG.ID {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set util_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_0_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_0_gt
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set util_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_1_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_1_gt
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set axi_fmcadc5_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_fmcadc5_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {256}] $axi_fmcadc5_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_fmcadc5_cpack
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# connections (gt)
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ad_connect util_fmcadc5_0_gt/cpll_ref_clk rx_ref_clk_0
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ad_connect util_fmcadc5_1_gt/cpll_ref_clk rx_ref_clk_1
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ad_connect axi_fmcadc5_0_gt/gt_qpll_0 util_fmcadc5_0_gt/gt_qpll_0
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ad_connect axi_fmcadc5_0_gt/gt_qpll_1 util_fmcadc5_0_gt/gt_qpll_1
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ad_connect axi_fmcadc5_0_gt/gt_pll_0 util_fmcadc5_0_gt/gt_pll_0
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ad_connect axi_fmcadc5_0_gt/gt_pll_1 util_fmcadc5_0_gt/gt_pll_1
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ad_connect axi_fmcadc5_0_gt/gt_pll_2 util_fmcadc5_0_gt/gt_pll_2
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ad_connect axi_fmcadc5_0_gt/gt_pll_3 util_fmcadc5_0_gt/gt_pll_3
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ad_connect axi_fmcadc5_0_gt/gt_pll_4 util_fmcadc5_0_gt/gt_pll_4
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ad_connect axi_fmcadc5_0_gt/gt_pll_5 util_fmcadc5_0_gt/gt_pll_5
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ad_connect axi_fmcadc5_0_gt/gt_pll_6 util_fmcadc5_0_gt/gt_pll_6
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ad_connect axi_fmcadc5_0_gt/gt_pll_7 util_fmcadc5_0_gt/gt_pll_7
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ad_connect axi_fmcadc5_1_gt/gt_qpll_0 util_fmcadc5_1_gt/gt_qpll_0
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ad_connect axi_fmcadc5_1_gt/gt_qpll_1 util_fmcadc5_1_gt/gt_qpll_1
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ad_connect axi_fmcadc5_1_gt/gt_pll_0 util_fmcadc5_1_gt/gt_pll_0
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ad_connect axi_fmcadc5_1_gt/gt_pll_1 util_fmcadc5_1_gt/gt_pll_1
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ad_connect axi_fmcadc5_1_gt/gt_pll_2 util_fmcadc5_1_gt/gt_pll_2
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ad_connect axi_fmcadc5_1_gt/gt_pll_3 util_fmcadc5_1_gt/gt_pll_3
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ad_connect axi_fmcadc5_1_gt/gt_pll_4 util_fmcadc5_1_gt/gt_pll_4
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ad_connect axi_fmcadc5_1_gt/gt_pll_5 util_fmcadc5_1_gt/gt_pll_5
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ad_connect axi_fmcadc5_1_gt/gt_pll_6 util_fmcadc5_1_gt/gt_pll_6
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ad_connect axi_fmcadc5_1_gt/gt_pll_7 util_fmcadc5_1_gt/gt_pll_7
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ad_connect axi_fmcadc5_0_gt/gt_rx_0 util_fmcadc5_0_gt/gt_rx_0
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ad_connect axi_fmcadc5_0_gt/gt_rx_1 util_fmcadc5_0_gt/gt_rx_1
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ad_connect axi_fmcadc5_0_gt/gt_rx_2 util_fmcadc5_0_gt/gt_rx_2
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ad_connect axi_fmcadc5_0_gt/gt_rx_3 util_fmcadc5_0_gt/gt_rx_3
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ad_connect axi_fmcadc5_0_gt/gt_rx_4 util_fmcadc5_0_gt/gt_rx_4
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ad_connect axi_fmcadc5_0_gt/gt_rx_5 util_fmcadc5_0_gt/gt_rx_5
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ad_connect axi_fmcadc5_0_gt/gt_rx_6 util_fmcadc5_0_gt/gt_rx_6
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ad_connect axi_fmcadc5_0_gt/gt_rx_7 util_fmcadc5_0_gt/gt_rx_7
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ad_connect axi_fmcadc5_1_gt/gt_rx_0 util_fmcadc5_1_gt/gt_rx_0
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ad_connect axi_fmcadc5_1_gt/gt_rx_1 util_fmcadc5_1_gt/gt_rx_1
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_2 util_fmcadc5_1_gt/gt_rx_2
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_3 util_fmcadc5_1_gt/gt_rx_3
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_4 util_fmcadc5_1_gt/gt_rx_4
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_5 util_fmcadc5_1_gt/gt_rx_5
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_6 util_fmcadc5_1_gt/gt_rx_6
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_7 util_fmcadc5_1_gt/gt_rx_7
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_0 axi_ad9625_0_jesd/gt0_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_1 axi_ad9625_0_jesd/gt1_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_2 axi_ad9625_0_jesd/gt2_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_3 axi_ad9625_0_jesd/gt3_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_4 axi_ad9625_0_jesd/gt4_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_5 axi_ad9625_0_jesd/gt5_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_6 axi_ad9625_0_jesd/gt6_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_7 axi_ad9625_0_jesd/gt7_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_0 axi_ad9625_1_jesd/gt0_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_1 axi_ad9625_1_jesd/gt1_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_2 axi_ad9625_1_jesd/gt2_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_3 axi_ad9625_1_jesd/gt3_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_4 axi_ad9625_1_jesd/gt4_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_5 axi_ad9625_1_jesd/gt5_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_6 axi_ad9625_1_jesd/gt6_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_7 axi_ad9625_1_jesd/gt7_rx
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_0 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_1 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_2 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_3 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_4 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_5 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_6 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_7 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_0 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_1 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_2 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_3 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_4 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_5 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_6 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_7 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_xcvrpll rx_ref_clk_0 util_fmcadc5_0_xcvr/qpll_ref_clk_*
|
||||
ad_xcvrpll rx_ref_clk_0 util_fmcadc5_0_xcvr/cpll_ref_clk_*
|
||||
ad_xcvrpll axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_qpll_rst_*
|
||||
ad_xcvrpll axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_cpll_rst_*
|
||||
ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/qpll_ref_clk_*
|
||||
ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/cpll_ref_clk_*
|
||||
ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_qpll_rst_*
|
||||
ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_cpll_rst_*
|
||||
ad_connect sys_cpu_resetn util_fmcadc5_0_xcvr/up_rstn
|
||||
ad_connect sys_cpu_resetn util_fmcadc5_1_xcvr/up_rstn
|
||||
ad_connect sys_cpu_clk util_fmcadc5_0_xcvr/up_clk
|
||||
ad_connect sys_cpu_clk util_fmcadc5_1_xcvr/up_clk
|
||||
|
||||
# connections (adc)
|
||||
|
||||
ad_connect util_fmcadc5_0_gt/rx_p rx_data_0_p
|
||||
ad_connect util_fmcadc5_0_gt/rx_n rx_data_0_n
|
||||
ad_connect util_fmcadc5_0_gt/rx_sysref GND
|
||||
ad_connect util_fmcadc5_0_gt/rx_sync rx_sync_0
|
||||
ad_connect util_fmcadc5_1_gt/rx_p rx_data_1_p
|
||||
ad_connect util_fmcadc5_1_gt/rx_n rx_data_1_n
|
||||
ad_connect util_fmcadc5_1_gt/rx_sysref GND
|
||||
ad_connect util_fmcadc5_1_gt/rx_sync rx_sync_1
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_sysref rx_sysref
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk rx_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_0_gt/rx_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_jesd/rx_core_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_rst axi_ad9625_0_jesd/rx_reset
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_rst_done axi_ad9625_0_jesd/rx_reset_done
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_0_jesd/rx_sysref
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_sync axi_ad9625_0_jesd/rx_sync
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_sof axi_ad9625_0_jesd/rx_start_of_frame
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_data axi_ad9625_0_jesd/rx_tdata
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_core/rx_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_data axi_ad9625_0_core/rx_data
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_1_gt/rx_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_1_jesd/rx_core_clk
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_rst axi_ad9625_1_jesd/rx_reset
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_rst_done axi_ad9625_1_jesd/rx_reset_done
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_1_jesd/rx_sysref
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_sync axi_ad9625_1_jesd/rx_sync
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_sof axi_ad9625_1_jesd/rx_start_of_frame
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_data axi_ad9625_1_jesd/rx_tdata
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_1_core/rx_clk
|
||||
ad_connect util_fmcadc5_1_gt/rx_data axi_ad9625_1_core/rx_data
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_fmcadc5_cpack/adc_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_rst axi_fmcadc5_cpack/adc_rst
|
||||
ad_xcvrcon util_fmcadc5_0_xcvr axi_ad9625_0_xcvr axi_ad9625_0_jesd
|
||||
ad_xcvrcon util_fmcadc5_1_xcvr axi_ad9625_1_xcvr axi_ad9625_1_jesd
|
||||
|
||||
delete_bd_objs [get_bd_nets -of_objects [get_bd_pins util_fmcadc5_1_xcvr/rx_out_clk_0]]
|
||||
delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9625_1_jesd_rstgen/peripheral_reset]]
|
||||
delete_bd_objs [get_bd_cells axi_ad9625_1_jesd_rstgen]
|
||||
|
||||
ad_xcvrpll util_fmcadc5_0_xcvr/rx_out_clk_0 util_fmcadc5_1_xcvr/rx_clk_*
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_jesd/rx_core_clk
|
||||
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_1_jesd/rx_reset
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_0_core/rx_clk
|
||||
ad_connect axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_0_core/rx_sof
|
||||
ad_connect axi_ad9625_0_jesd/rx_tdata axi_ad9625_0_core/rx_data
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_core/rx_clk
|
||||
ad_connect axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_1_core/rx_sof
|
||||
ad_connect axi_ad9625_1_jesd/rx_tdata axi_ad9625_1_core/rx_data
|
||||
ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_0_core/adc_raddr_in
|
||||
ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_1_core/adc_raddr_in
|
||||
ad_connect axi_ad9625_0_core/adc_enable axi_fmcadc5_cpack/adc_enable_0
|
||||
ad_connect axi_ad9625_0_core/adc_valid axi_fmcadc5_cpack/adc_valid_0
|
||||
ad_connect axi_ad9625_0_core/adc_data axi_fmcadc5_cpack/adc_data_0
|
||||
ad_connect axi_ad9625_1_core/adc_enable axi_fmcadc5_cpack/adc_enable_1
|
||||
ad_connect axi_ad9625_1_core/adc_valid axi_fmcadc5_cpack/adc_valid_1
|
||||
ad_connect axi_ad9625_1_core/adc_data axi_fmcadc5_cpack/adc_data_1
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_fifo/adc_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_rst axi_ad9625_fifo/adc_rst
|
||||
ad_connect axi_fmcadc5_cpack/adc_valid axi_ad9625_fifo/adc_wr
|
||||
ad_connect axi_fmcadc5_cpack/adc_data axi_ad9625_fifo/adc_wdata
|
||||
ad_connect axi_ad9625_0_core/adc_dovf axi_ad9625_fifo/adc_wovf
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 util_ad9625_cpack/adc_clk
|
||||
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset util_ad9625_cpack/adc_rst
|
||||
ad_connect axi_ad9625_0_core/adc_enable util_ad9625_cpack/adc_enable_0
|
||||
ad_connect axi_ad9625_0_core/adc_valid util_ad9625_cpack/adc_valid_0
|
||||
ad_connect axi_ad9625_0_core/adc_data util_ad9625_cpack/adc_data_0
|
||||
ad_connect axi_ad9625_1_core/adc_enable util_ad9625_cpack/adc_enable_1
|
||||
ad_connect axi_ad9625_1_core/adc_valid util_ad9625_cpack/adc_valid_1
|
||||
ad_connect axi_ad9625_1_core/adc_data util_ad9625_cpack/adc_data_1
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk
|
||||
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
|
||||
ad_connect util_ad9625_cpack/adc_valid axi_ad9625_fifo/adc_wr
|
||||
ad_connect util_ad9625_cpack/adc_data axi_ad9625_fifo/adc_wdata
|
||||
ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_0_core/adc_dovf
|
||||
ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_1_core/adc_dovf
|
||||
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
|
||||
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
|
||||
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
|
||||
|
|
@ -266,8 +125,8 @@ ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
|
|||
|
||||
# interconnect (cpu)
|
||||
|
||||
ad_cpu_interconnect 0x44a60000 axi_fmcadc5_0_gt
|
||||
ad_cpu_interconnect 0x44b60000 axi_fmcadc5_1_gt
|
||||
ad_cpu_interconnect 0x44a60000 axi_ad9625_0_xcvr
|
||||
ad_cpu_interconnect 0x44b60000 axi_ad9625_1_xcvr
|
||||
ad_cpu_interconnect 0x44a10000 axi_ad9625_0_core
|
||||
ad_cpu_interconnect 0x44b10000 axi_ad9625_1_core
|
||||
ad_cpu_interconnect 0x44a91000 axi_ad9625_0_jesd
|
||||
|
|
@ -276,21 +135,23 @@ ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
|
|||
|
||||
# interconnect (gt/adc)
|
||||
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_0_gt/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_1_gt/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_0_xcvr/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_1_xcvr/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq
|
||||
ad_cpu_interrupt ps-12 mb-12 axi_ad9625_dma/irq
|
||||
|
||||
# sync
|
||||
|
||||
create_bd_port -dir O rx_clk
|
||||
create_bd_port -dir O up_clk
|
||||
create_bd_port -dir O up_rstn
|
||||
create_bd_port -dir O delay_clk
|
||||
create_bd_port -dir O delay_rst
|
||||
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 rx_clk
|
||||
ad_connect sys_cpu_clk up_clk
|
||||
ad_connect sys_cpu_resetn up_rstn
|
||||
ad_connect sys_200m_clk delay_clk
|
||||
|
|
|
|||
|
|
@ -22,11 +22,11 @@ M_DEPS += ../../common/vc707/vc707_system_bd.tcl
|
|||
M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v
|
||||
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
||||
M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
|
||||
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
|
||||
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
|
||||
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
|
||||
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
|
||||
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
|
||||
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
|
||||
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
|
||||
M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr
|
||||
|
||||
M_VIVADO := vivado -mode batch -source
|
||||
|
|
@ -57,11 +57,11 @@ clean:
|
|||
|
||||
clean-all:clean
|
||||
make -C ../../../library/axi_ad9625 clean
|
||||
make -C ../../../library/xilinx/axi_adxcvr clean
|
||||
make -C ../../../library/axi_dmac clean
|
||||
make -C ../../../library/axi_jesd_gt clean
|
||||
make -C ../../../library/util_adcfifo clean
|
||||
make -C ../../../library/xilinx/util_adxcvr clean
|
||||
make -C ../../../library/util_cpack clean
|
||||
make -C ../../../library/util_jesd_gt clean
|
||||
make -C ../../../library/util_mfifo clean
|
||||
|
||||
|
||||
|
|
@ -72,11 +72,11 @@ fmcadc5_vc707.sdk/system_top.hdf: $(M_DEPS)
|
|||
|
||||
lib:
|
||||
make -C ../../../library/axi_ad9625
|
||||
make -C ../../../library/xilinx/axi_adxcvr
|
||||
make -C ../../../library/axi_dmac
|
||||
make -C ../../../library/axi_jesd_gt
|
||||
make -C ../../../library/util_adcfifo
|
||||
make -C ../../../library/xilinx/util_adxcvr
|
||||
make -C ../../../library/util_cpack
|
||||
make -C ../../../library/util_jesd_gt
|
||||
make -C ../../../library/util_mfifo
|
||||
|
||||
####################################################################################
|
||||
|
|
|
|||
|
|
@ -18,13 +18,13 @@ set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc
|
|||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
|
||||
|
||||
ad_connect util_fmcadc5_0_gt/rx_rst mfifo_adc/din_rst
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk mfifo_adc/din_clk
|
||||
ad_connect axi_fmcadc5_cpack/adc_valid mfifo_adc/din_valid
|
||||
ad_connect axi_fmcadc5_cpack/adc_data mfifo_adc/din_data_0
|
||||
ad_connect util_fmcadc5_0_gt/rx_rst mfifo_adc/dout_rst
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk mfifo_adc/dout_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk ila_adc/clk
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/din_clk
|
||||
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/din_rst
|
||||
ad_connect util_ad9625_cpack/adc_valid mfifo_adc/din_valid
|
||||
ad_connect util_ad9625_cpack/adc_data mfifo_adc/din_data_0
|
||||
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/dout_rst
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
|
||||
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 ila_adc/clk
|
||||
ad_connect mfifo_adc/dout_valid ila_adc/probe0
|
||||
ad_connect mfifo_adc/dout_data_0 ila_adc/probe1
|
||||
|
||||
|
|
|
|||
|
|
@ -84,6 +84,8 @@ set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVCMOS18} [get_ports psync_1]
|
|||
|
||||
create_clock -name rx_ref_clk_0 -period 1.60 [get_ports rx_ref_clk_0_p]
|
||||
create_clock -name rx_ref_clk_1 -period 1.60 [get_ports rx_ref_clk_1_p]
|
||||
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_fmcadc5_0_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc5_0_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
|
||||
|
||||
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_0_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
|
||||
set_false_path -to [get_cells rx_sysref_m1_reg]
|
||||
|
||||
|
|
|
|||
|
|
@ -7,15 +7,13 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
|||
|
||||
adi_project_create fmcadc5_vc707
|
||||
adi_project_files fmcadc5_vc707 [list \
|
||||
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"../common/fmcadc5_spi.v" \
|
||||
"../common/fmcadc5_psync.v" \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
|
||||
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
|
||||
|
||||
set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc]
|
||||
"system_top.v"]
|
||||
|
||||
adi_project_run fmcadc5_vc707
|
||||
|
||||
|
|
|
|||
|
|
@ -34,207 +34,113 @@
|
|||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
sys_rst,
|
||||
sys_clk_p,
|
||||
sys_clk_n,
|
||||
input sys_rst,
|
||||
input sys_clk_p,
|
||||
input sys_clk_n,
|
||||
|
||||
uart_sin,
|
||||
uart_sout,
|
||||
input uart_sin,
|
||||
output uart_sout,
|
||||
|
||||
ddr3_addr,
|
||||
ddr3_ba,
|
||||
ddr3_cas_n,
|
||||
ddr3_ck_n,
|
||||
ddr3_ck_p,
|
||||
ddr3_cke,
|
||||
ddr3_cs_n,
|
||||
ddr3_dm,
|
||||
ddr3_dq,
|
||||
ddr3_dqs_n,
|
||||
ddr3_dqs_p,
|
||||
ddr3_odt,
|
||||
ddr3_ras_n,
|
||||
ddr3_reset_n,
|
||||
ddr3_we_n,
|
||||
output [ 13:0] ddr3_addr,
|
||||
output [ 2:0] ddr3_ba,
|
||||
output ddr3_cas_n,
|
||||
output [ 0:0] ddr3_ck_n,
|
||||
output [ 0:0] ddr3_ck_p,
|
||||
output [ 0:0] ddr3_cke,
|
||||
output [ 0:0] ddr3_cs_n,
|
||||
output [ 7:0] ddr3_dm,
|
||||
inout [ 63:0] ddr3_dq,
|
||||
inout [ 7:0] ddr3_dqs_n,
|
||||
inout [ 7:0] ddr3_dqs_p,
|
||||
output [ 0:0] ddr3_odt,
|
||||
output ddr3_ras_n,
|
||||
output ddr3_reset_n,
|
||||
output ddr3_we_n,
|
||||
|
||||
sgmii_rxp,
|
||||
sgmii_rxn,
|
||||
sgmii_txp,
|
||||
sgmii_txn,
|
||||
input sgmii_rxp,
|
||||
input sgmii_rxn,
|
||||
output sgmii_txp,
|
||||
output sgmii_txn,
|
||||
|
||||
phy_rstn,
|
||||
mgt_clk_p,
|
||||
mgt_clk_n,
|
||||
mdio_mdc,
|
||||
mdio_mdio,
|
||||
output phy_rstn,
|
||||
input mgt_clk_p,
|
||||
input mgt_clk_n,
|
||||
output mdio_mdc,
|
||||
inout mdio_mdio,
|
||||
|
||||
fan_pwm,
|
||||
output fan_pwm,
|
||||
|
||||
linear_flash_addr,
|
||||
linear_flash_adv_ldn,
|
||||
linear_flash_ce_n,
|
||||
linear_flash_oen,
|
||||
linear_flash_wen,
|
||||
linear_flash_dq_io,
|
||||
output [26:1] linear_flash_addr,
|
||||
output linear_flash_adv_ldn,
|
||||
output linear_flash_ce_n,
|
||||
output linear_flash_oen,
|
||||
output linear_flash_wen,
|
||||
inout [15:0] linear_flash_dq_io,
|
||||
|
||||
gpio_lcd,
|
||||
gpio_bd,
|
||||
inout [ 6:0] gpio_lcd,
|
||||
inout [ 20:0] gpio_bd,
|
||||
|
||||
iic_rstn,
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
output iic_rstn,
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
|
||||
rx_ref_clk_0_p,
|
||||
rx_ref_clk_0_n,
|
||||
rx_data_0_p,
|
||||
rx_data_0_n,
|
||||
rx_ref_clk_1_p,
|
||||
rx_ref_clk_1_n,
|
||||
rx_data_1_p,
|
||||
rx_data_1_n,
|
||||
rx_sysref_p,
|
||||
rx_sysref_n,
|
||||
rx_sync_0_p,
|
||||
rx_sync_0_n,
|
||||
rx_sync_1_p,
|
||||
rx_sync_1_n,
|
||||
input rx_ref_clk_0_p,
|
||||
input rx_ref_clk_0_n,
|
||||
input [ 7:0] rx_data_0_p,
|
||||
input [ 7:0] rx_data_0_n,
|
||||
input rx_ref_clk_1_p,
|
||||
input rx_ref_clk_1_n,
|
||||
input [ 7:0] rx_data_1_p,
|
||||
input [ 7:0] rx_data_1_n,
|
||||
output rx_sysref_p,
|
||||
output rx_sysref_n,
|
||||
output rx_sync_0_p,
|
||||
output rx_sync_0_n,
|
||||
output rx_sync_1_p,
|
||||
output rx_sync_1_n,
|
||||
|
||||
spi_csn_0,
|
||||
spi_csn_1,
|
||||
spi_clk,
|
||||
spi_sdio,
|
||||
spi_dirn,
|
||||
output spi_csn_0,
|
||||
output spi_csn_1,
|
||||
output spi_clk,
|
||||
inout spi_sdio,
|
||||
output spi_dirn,
|
||||
output dac_clk,
|
||||
output dac_data,
|
||||
output dac_sync_0,
|
||||
output dac_sync_1,
|
||||
|
||||
psync_0,
|
||||
psync_1,
|
||||
trig_p,
|
||||
trig_n,
|
||||
vdither_p,
|
||||
vdither_n,
|
||||
pwr_good,
|
||||
dac_clk,
|
||||
dac_data,
|
||||
dac_sync_0,
|
||||
dac_sync_1,
|
||||
fd_1,
|
||||
irq_1,
|
||||
fd_0,
|
||||
irq_0,
|
||||
pwdn_1,
|
||||
rst_1,
|
||||
drst_1,
|
||||
arst_1,
|
||||
pwdn_0,
|
||||
rst_0,
|
||||
drst_0,
|
||||
arst_0);
|
||||
|
||||
input sys_rst;
|
||||
input sys_clk_p;
|
||||
input sys_clk_n;
|
||||
|
||||
input uart_sin;
|
||||
output uart_sout;
|
||||
|
||||
output [ 13:0] ddr3_addr;
|
||||
output [ 2:0] ddr3_ba;
|
||||
output ddr3_cas_n;
|
||||
output [ 0:0] ddr3_ck_n;
|
||||
output [ 0:0] ddr3_ck_p;
|
||||
output [ 0:0] ddr3_cke;
|
||||
output [ 0:0] ddr3_cs_n;
|
||||
output [ 7:0] ddr3_dm;
|
||||
inout [ 63:0] ddr3_dq;
|
||||
inout [ 7:0] ddr3_dqs_n;
|
||||
inout [ 7:0] ddr3_dqs_p;
|
||||
output [ 0:0] ddr3_odt;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_reset_n;
|
||||
output ddr3_we_n;
|
||||
|
||||
input sgmii_rxp;
|
||||
input sgmii_rxn;
|
||||
output sgmii_txp;
|
||||
output sgmii_txn;
|
||||
|
||||
output phy_rstn;
|
||||
input mgt_clk_p;
|
||||
input mgt_clk_n;
|
||||
output mdio_mdc;
|
||||
inout mdio_mdio;
|
||||
|
||||
output fan_pwm;
|
||||
|
||||
output [26:1] linear_flash_addr;
|
||||
output linear_flash_adv_ldn;
|
||||
output linear_flash_ce_n;
|
||||
output linear_flash_oen;
|
||||
output linear_flash_wen;
|
||||
inout [15:0] linear_flash_dq_io;
|
||||
|
||||
inout [ 6:0] gpio_lcd;
|
||||
inout [ 20:0] gpio_bd;
|
||||
|
||||
output iic_rstn;
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
input rx_ref_clk_0_p;
|
||||
input rx_ref_clk_0_n;
|
||||
input [ 7:0] rx_data_0_p;
|
||||
input [ 7:0] rx_data_0_n;
|
||||
input rx_ref_clk_1_p;
|
||||
input rx_ref_clk_1_n;
|
||||
input [ 7:0] rx_data_1_p;
|
||||
input [ 7:0] rx_data_1_n;
|
||||
output rx_sysref_p;
|
||||
output rx_sysref_n;
|
||||
output rx_sync_0_p;
|
||||
output rx_sync_0_n;
|
||||
output rx_sync_1_p;
|
||||
output rx_sync_1_n;
|
||||
|
||||
output spi_csn_0;
|
||||
output spi_csn_1;
|
||||
output spi_clk;
|
||||
inout spi_sdio;
|
||||
output spi_dirn;
|
||||
output dac_clk;
|
||||
output dac_data;
|
||||
output dac_sync_0;
|
||||
output dac_sync_1;
|
||||
|
||||
output psync_0;
|
||||
output psync_1;
|
||||
input trig_p;
|
||||
input trig_n;
|
||||
output vdither_p;
|
||||
output vdither_n;
|
||||
inout pwr_good;
|
||||
inout fd_1;
|
||||
inout irq_1;
|
||||
inout fd_0;
|
||||
inout irq_0;
|
||||
inout pwdn_1;
|
||||
inout rst_1;
|
||||
output drst_1;
|
||||
output arst_1;
|
||||
inout pwdn_0;
|
||||
inout rst_0;
|
||||
output drst_0;
|
||||
output arst_0;
|
||||
output psync_0,
|
||||
output psync_1,
|
||||
input trig_p,
|
||||
input trig_n,
|
||||
output vdither_p,
|
||||
output vdither_n,
|
||||
inout pwr_good,
|
||||
inout fd_1,
|
||||
inout irq_1,
|
||||
inout fd_0,
|
||||
inout irq_0,
|
||||
inout pwdn_1,
|
||||
inout rst_1,
|
||||
output drst_1,
|
||||
output arst_1,
|
||||
inout pwdn_0,
|
||||
inout rst_0,
|
||||
output drst_0,
|
||||
output arst_0);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 4:0] gpio_o_60_56_d = 'd0;
|
||||
reg gpio_dld = 'd0;
|
||||
reg rx_sysref_m1 = 'd0;
|
||||
reg rx_sysref_m2 = 'd0;
|
||||
reg rx_sysref_int = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
|
|
@ -250,7 +156,6 @@ module system_top (
|
|||
wire rx_clk;
|
||||
wire rx_ref_clk_0;
|
||||
wire rx_ref_clk_1;
|
||||
wire rx_sysref_s;
|
||||
wire rx_sync_0;
|
||||
wire rx_sync_1;
|
||||
wire up_rstn;
|
||||
|
|
@ -287,6 +192,14 @@ module system_top (
|
|||
end
|
||||
end
|
||||
|
||||
// sysref internal
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
rx_sysref_m1 <= gpio_o[32];
|
||||
rx_sysref_m2 <= rx_sysref_m1;
|
||||
rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_lvds_out #(
|
||||
|
|
@ -297,8 +210,8 @@ module system_top (
|
|||
.IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"))
|
||||
i_rx_sysref (
|
||||
.tx_clk (rx_clk),
|
||||
.tx_data_p (rx_sysref_s),
|
||||
.tx_data_n (rx_sysref_s),
|
||||
.tx_data_p (rx_sysref_int),
|
||||
.tx_data_n (rx_sysref_int),
|
||||
.tx_data_out_p (rx_sysref_p),
|
||||
.tx_data_out_n (rx_sysref_n),
|
||||
.up_clk (up_clk),
|
||||
|
|
@ -424,15 +337,44 @@ module system_top (
|
|||
.phy_rstn (phy_rstn),
|
||||
.phy_sd (1'b1),
|
||||
.rx_clk (rx_clk),
|
||||
.rx_data_0_n (rx_data_0_n),
|
||||
.rx_data_0_p (rx_data_0_p),
|
||||
.rx_data_1_n (rx_data_1_n),
|
||||
.rx_data_1_p (rx_data_1_p),
|
||||
.rx_data_0_n (rx_data_0_n[0]),
|
||||
.rx_data_0_p (rx_data_0_p[0]),
|
||||
.rx_data_1_0_n (rx_data_1_n[0]),
|
||||
.rx_data_1_0_p (rx_data_1_p[0]),
|
||||
.rx_data_1_1_n (rx_data_1_n[1]),
|
||||
.rx_data_1_1_p (rx_data_1_p[1]),
|
||||
.rx_data_1_2_n (rx_data_1_n[2]),
|
||||
.rx_data_1_2_p (rx_data_1_p[2]),
|
||||
.rx_data_1_3_n (rx_data_1_n[3]),
|
||||
.rx_data_1_3_p (rx_data_1_p[3]),
|
||||
.rx_data_1_4_n (rx_data_1_n[4]),
|
||||
.rx_data_1_4_p (rx_data_1_p[4]),
|
||||
.rx_data_1_5_n (rx_data_1_n[5]),
|
||||
.rx_data_1_5_p (rx_data_1_p[5]),
|
||||
.rx_data_1_6_n (rx_data_1_n[6]),
|
||||
.rx_data_1_6_p (rx_data_1_p[6]),
|
||||
.rx_data_1_7_n (rx_data_1_n[7]),
|
||||
.rx_data_1_7_p (rx_data_1_p[7]),
|
||||
.rx_data_1_n (rx_data_0_n[1]),
|
||||
.rx_data_1_p (rx_data_0_p[1]),
|
||||
.rx_data_2_n (rx_data_0_n[2]),
|
||||
.rx_data_2_p (rx_data_0_p[2]),
|
||||
.rx_data_3_n (rx_data_0_n[3]),
|
||||
.rx_data_3_p (rx_data_0_p[3]),
|
||||
.rx_data_4_n (rx_data_0_n[4]),
|
||||
.rx_data_4_p (rx_data_0_p[4]),
|
||||
.rx_data_5_n (rx_data_0_n[5]),
|
||||
.rx_data_5_p (rx_data_0_p[5]),
|
||||
.rx_data_6_n (rx_data_0_n[6]),
|
||||
.rx_data_6_p (rx_data_0_p[6]),
|
||||
.rx_data_7_n (rx_data_0_n[7]),
|
||||
.rx_data_7_p (rx_data_0_p[7]),
|
||||
.rx_ref_clk_0 (rx_ref_clk_0),
|
||||
.rx_ref_clk_1 (rx_ref_clk_1),
|
||||
.rx_sync_0 (rx_sync_0),
|
||||
.rx_sync_1 (rx_sync_1),
|
||||
.rx_sysref (rx_sysref_s),
|
||||
.rx_sync_1_0 (rx_sync_1),
|
||||
.rx_sysref_0 (rx_sysref_int),
|
||||
.rx_sysref_1_0 (rx_sysref_int),
|
||||
.sgmii_rxn (sgmii_rxn),
|
||||
.sgmii_rxp (sgmii_rxp),
|
||||
.sgmii_txn (sgmii_txn),
|
||||
|
|
|
|||
Loading…
Reference in New Issue