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spi_engine_execution: code refactoring 

The added modification do not chnage the functionality of the module.
main
Istvan Csomortani 2020-07-09 15:32:53 +01:00 committed by István Csomortáni
parent 45d806ff11
commit 11947f2e7e
1 changed files with 9 additions and 8 deletions
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17
library/spi_engine/spi_engine_execution/spi_engine_execution.v
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@ -61,7 +61,7 @@ module spi_engine_execution #(
input sdi_data_ready,
output reg sdi_data_valid,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
input sync_ready,
output reg sync_valid,
@ -141,7 +141,7 @@ reg sdi_enabled = 1'b0;
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+1){1'b0}};
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
wire [1:0] inst = cmd[13:12];
wire [1:0] inst_d1 = cmd_d1[13:12];
@ -397,8 +397,7 @@ assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
// be latched at one of the next consecutive SCLK edge.
always @(posedge clk) begin
trigger_rx_d[0] <= trigger_rx;
trigger_rx_d[SDI_DELAY+1:1] <= trigger_rx_d[SDI_DELAY:0];
trigger_rx_d <= {trigger_rx_d, trigger_rx};
end
assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
@ -415,13 +414,15 @@ generate
always @(posedge clk) begin
if (cs_active_s) begin
data_sdi_shift <= {DATA_WIDTH{1'b0}};
end else if (trigger_rx_s == 1'b1) begin
data_sdi_shift <= {data_sdi_shift[DATA_WIDTH-2:0], sdi[i]};
data_sdi_shift <= 0;
end else begin
if (trigger_rx_s == 1'b1) begin
data_sdi_shift <= {data_sdi_shift, sdi[i]};
end
end
end
assign sdi_data[((i+1)*DATA_WIDTH)-1:i*DATA_WIDTH] = data_sdi_shift;
assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
end
endgenerate