Laszlo Nagy
Laszlo Nagy
parent
b27f3ac18f
commit
118e1f9e8b
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := adrv9001_zed
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M_DEPS += ../common/adrv9001_bd.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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LIB_DEPS += axi_adrv9001
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += axi_sysid
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_i2c_mixer
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_out_n] ;## G07 FMC_HPC0_LA00_CC_N IO_L13N_T2_MRCC_34
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_out_p] ;## G06 FMC_HPC0_LA00_CC_P IO_L13P_T2_MRCC_34
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set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_out_n] ;## G10 FMC_HPC0_LA03_N IO_L16N_T2_34
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set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_out_p] ;## G09 FMC_HPC0_LA03_P IO_L16P_T2_34
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set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18 } [get_ports rx1_qdata_out_n] ;## H11 FMC_HPC0_LA04_N IO_L15N_T2_DQS_34
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18 } [get_ports rx1_qdata_out_p] ;## H10 FMC_HPC0_LA04_P IO_L15P_T2_DQS_34
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS18 } [get_ports rx1_strobe_out_n] ;## H08 FMC_HPC0_LA02_N IO_L20N_T3_34
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS18 } [get_ports rx1_strobe_out_p] ;## H07 FMC_HPC0_LA02_P IO_L20P_T3_34
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set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18 } [get_ports rx2_dclk_out_n] ;## D21 FMC_HPC0_LA17_CC_N IO_L13N_T2_MRCC_35
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set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS18 } [get_ports rx2_dclk_out_p] ;## D20 FMC_HPC0_LA17_CC_P IO_L13P_T2_MRCC_35
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set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS18 } [get_ports rx2_idata_out_n] ;## G22 FMC_HPC0_LA20_N IO_L22N_T3_AD7N_35
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set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18 } [get_ports rx2_idata_out_p] ;## G21 FMC_HPC0_LA20_P IO_L22P_T3_AD7P_35
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set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18 } [get_ports rx2_qdata_out_n] ;## H23 FMC_HPC0_LA19_N IO_L4N_T0_35
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18 } [get_ports rx2_qdata_out_p] ;## H22 FMC_HPC0_LA19_P IO_L4P_T0_35
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set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS18 } [get_ports rx2_strobe_out_n] ;## H26 FMC_HPC0_LA21_N IO_L21N_T3_DQS_AD14N_35
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set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18 } [get_ports rx2_strobe_out_p] ;## H25 FMC_HPC0_LA21_P IO_L21P_T3_DQS_AD14P_35
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set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_in_n] ;## H14 FMC_HPC0_LA07_N IO_L21N_T3_DQS_34
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set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_in_p] ;## H13 FMC_HPC0_LA07_P IO_L21P_T3_DQS_34
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_out_n] ;## D09 FMC_HPC0_LA01_CC_N IO_L14N_T2_SRCC_34
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_out_p] ;## D08 FMC_HPC0_LA01_CC_P IO_L14P_T2_SRCC_34
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set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS18 } [get_ports tx1_idata_in_n] ;## G13 FMC_HPC0_LA08_N IO_L8N_T1_34
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set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS18 } [get_ports tx1_idata_in_p] ;## G12 FMC_HPC0_LA08_P IO_L8P_T1_34
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18 } [get_ports tx1_qdata_in_n] ;## D12 FMC_HPC0_LA05_N IO_L7N_T1_34
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18 } [get_ports tx1_qdata_in_p] ;## D11 FMC_HPC0_LA05_P IO_L7P_T1_34
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS18 } [get_ports tx1_strobe_in_n] ;## C11 FMC_HPC0_LA06_N IO_L10N_T1_34
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set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS18 } [get_ports tx1_strobe_in_p] ;## C10 FMC_HPC0_LA06_P IO_L10P_T1_34
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set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_in_n] ;## G25 FMC_HPC0_LA22_N IO_L20N_T3_AD6N_35
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_in_p] ;## G24 FMC_HPC0_LA22_P IO_L20P_T3_AD6P_35
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set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_out_n] ;## C23 FMC_HPC0_LA18_CC_N IO_L14N_T2_AD4N_SRCC_35
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set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_out_p] ;## C22 FMC_HPC0_LA18_CC_P IO_L14P_T2_AD4P_SRCC_35
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set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS18 } [get_ports tx2_idata_in_n] ;## D24 FMC_HPC0_LA23_N IO_L3N_T0_DQS_AD1N_35
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set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18 } [get_ports tx2_idata_in_p] ;## D23 FMC_HPC0_LA23_P IO_L3P_T0_DQS_AD1P_35
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set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18 } [get_ports tx2_qdata_in_n] ;## G28 FMC_HPC0_LA25_N IO_L16N_T2_35
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set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18 } [get_ports tx2_qdata_in_p] ;## G27 FMC_HPC0_LA25_P IO_L16P_T2_35
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set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS18 } [get_ports tx2_strobe_in_n] ;## H29 FMC_HPC0_LA24_N IO_L10N_T1_AD11N_35
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set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18 } [get_ports tx2_strobe_in_p] ;## H28 FMC_HPC0_LA24_P IO_L10P_T1_AD11P_35
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# clocks
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#create_clock -name ref_clk -period 25.00 [get_ports fpga_ref_clk_p]
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create_clock -name rx1_dclk_out -period 12.5 [get_ports rx1_dclk_out_p]
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create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_out_p]
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create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_out_p]
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create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_out_p]
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set_clock_latency -source -early 2 [get_clocks rx1_dclk_out]
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set_clock_latency -source -early 2 [get_clocks rx2_dclk_out]
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set_clock_latency -source -late 5 [get_clocks rx1_dclk_out]
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set_clock_latency -source -late 5 [get_clocks rx2_dclk_out]
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@ -0,0 +1,11 @@
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source ../common/adrv9001_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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# constraints
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# adrv9001
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports dev_clk_out] ; # H04 FMC_HPC0_CLK0_M2C_P IO_L12P_T1_MRCC_34
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set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports dgpio_0] ; # G18 FMC_HPC0_LA16_P IO_L9P_T1_DQS_34
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set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS18} [get_ports dgpio_1] ; # G19 FMC_HPC0_LA16_N IO_L9N_T1_DQS_34
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set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports dgpio_2] ; # H20 FMC_HPC0_LA15_N IO_L2N_T0_34
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set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS18} [get_ports dgpio_3] ; # H17 FMC_HPC0_LA11_N IO_L5N_T0_34
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set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS18} [get_ports dgpio_4] ; # D15 FMC_HPC0_LA09_N IO_L17N_T2_34
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set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS18} [get_ports dgpio_5] ; # C15 FMC_HPC0_LA10_N IO_L22N_T3_34
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set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports dgpio_6] ; # C26 FMC_HPC0_LA27_P IO_L17P_T2_AD5P_35
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set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports dgpio_7] ; # D26 FMC_HPC0_LA26_P IO_L5P_T0_AD9P_35
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set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports dgpio_8] ; # H31 FMC_HPC0_LA28_P IO_L9P_T1_DQS_AD3P_35
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports dgpio_9] ; # H32 FMC_HPC0_LA28_N IO_L9N_T1_DQS_AD3N_35
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set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS18} [get_ports dgpio_10] ; # H16 FMC_HPC0_LA11_P IO_L5P_T0_34
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports dgpio_11] ; # C27 FMC_HPC0_LA27_N IO_L17N_T2_AD5N_35
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set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS18} [get_ports gp_int] ; # H34 FMC_HPC0_LA30_P IO_L7P_T1_AD2P_35
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports mode] ; # D17 FMC_HPC0_LA13_P IO_L4P_T0_34
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set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS18} [get_ports reset_trx] ; # D18 FMC_HPC0_LA13_N IO_L4N_T0_34
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set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS18} [get_ports rx1_enable] ; # C14 FMC_HPC0_LA10_P IO_L22P_T3_34
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set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports rx2_enable] ; # D27 FMC_HPC0_LA26_N IO_L5N_T0_AD9N_35
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set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS18} [get_ports sm_fan_tach] ; # H05 FMC_HPC0_CLK0_M2C_N IO_L12N_T1_MRCC_34
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set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; # G15 FMC_HPC0_LA12_P IO_L18P_T2_34
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set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS18} [get_ports spi_dio] ; # G31 FMC_HPC0_LA29_N IO_L11N_T1_SRCC_35
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set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports spi_do] ; # G16 FMC_HPC0_LA12_N IO_L18N_T2_34
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set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports spi_en] ; # H19 FMC_HPC0_LA15_P IO_L2P_T0_34
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set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS18} [get_ports tx1_enable] ; # D14 FMC_HPC0_LA09_P IO_L17P_T2_34
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports tx2_enable] ; # G30 FMC_HPC0_LA29_P IO_L11P_T1_SRCC_35
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set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports vadj_test_1] ; # G33 FMC_HPC0_LA31_P IO_L8P_T1_AD10P_35
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set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports vadj_test_2] ; # G34 FMC_HPC0_LA31_N IO_L8N_T1_AD10N_35
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# redefine contraints from common file for VADJ 1.8V
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set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports otg_vbusoc]
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set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## BTNC
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set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## BTND
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set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## BTNL
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set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## BTNR
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set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## BTNU
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set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[11]] ; ## SW0
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set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[12]] ; ## SW1
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set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[13]] ; ## SW2
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set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports gpio_bd[14]] ; ## SW3
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## SW4
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set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[16]] ; ## SW5
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set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[17]] ; ## SW6
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set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[18]] ; ## SW7
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set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[27]] ; ## XADC-GIO0
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set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[28]] ; ## XADC-GIO1
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[29]] ; ## XADC-GIO2
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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[30]] ; ## XADC-GIO3
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set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[31]] ; ## OTG-RESETN
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project adrv9001_zed 0 [list \
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CMOS_LVDS_N 1 \
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]
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adi_project_files adrv9001_zed [list \
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"system_top.v" \
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"system_constr.xdc" \
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"cmos_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
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set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
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adi_project_run adrv9001_zed
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [31:0] gpio_bd,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [15:0] hdmi_data,
|
||||
|
||||
output i2s_mclk,
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
output i2s_sdata_out,
|
||||
input i2s_sdata_in,
|
||||
|
||||
output spdif,
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
inout [ 1:0] iic_mux_scl,
|
||||
inout [ 1:0] iic_mux_sda,
|
||||
|
||||
input otg_vbusoc,
|
||||
|
||||
// FMC connector
|
||||
output spi_clk,
|
||||
output spi_dio,
|
||||
input spi_do,
|
||||
output spi_en,
|
||||
|
||||
// Device clock passed through 9001
|
||||
input dev_clk_out,
|
||||
|
||||
inout dgpio_0,
|
||||
inout dgpio_1,
|
||||
inout dgpio_2,
|
||||
inout dgpio_3,
|
||||
inout dgpio_4,
|
||||
inout dgpio_5,
|
||||
inout dgpio_6,
|
||||
inout dgpio_7,
|
||||
inout dgpio_8,
|
||||
inout dgpio_9,
|
||||
inout dgpio_10,
|
||||
inout dgpio_11,
|
||||
|
||||
inout gp_int,
|
||||
inout mode,
|
||||
inout reset_trx,
|
||||
|
||||
input rx1_dclk_out_n,
|
||||
input rx1_dclk_out_p,
|
||||
inout rx1_enable,
|
||||
input rx1_idata_out_n,
|
||||
input rx1_idata_out_p,
|
||||
input rx1_qdata_out_n,
|
||||
input rx1_qdata_out_p,
|
||||
input rx1_strobe_out_n,
|
||||
input rx1_strobe_out_p,
|
||||
|
||||
input rx2_dclk_out_n,
|
||||
input rx2_dclk_out_p,
|
||||
inout rx2_enable,
|
||||
input rx2_idata_out_n,
|
||||
input rx2_idata_out_p,
|
||||
input rx2_qdata_out_n,
|
||||
input rx2_qdata_out_p,
|
||||
input rx2_strobe_out_n,
|
||||
input rx2_strobe_out_p,
|
||||
|
||||
output tx1_dclk_in_n,
|
||||
output tx1_dclk_in_p,
|
||||
input tx1_dclk_out_n,
|
||||
input tx1_dclk_out_p,
|
||||
inout tx1_enable,
|
||||
output tx1_idata_in_n,
|
||||
output tx1_idata_in_p,
|
||||
output tx1_qdata_in_n,
|
||||
output tx1_qdata_in_p,
|
||||
output tx1_strobe_in_n,
|
||||
output tx1_strobe_in_p,
|
||||
|
||||
output tx2_dclk_in_n,
|
||||
output tx2_dclk_in_p,
|
||||
input tx2_dclk_out_n,
|
||||
input tx2_dclk_out_p,
|
||||
inout tx2_enable,
|
||||
output tx2_idata_in_n,
|
||||
output tx2_idata_in_p,
|
||||
output tx2_qdata_in_n,
|
||||
output tx2_qdata_in_p,
|
||||
output tx2_strobe_in_n,
|
||||
output tx2_strobe_in_p,
|
||||
|
||||
inout sm_fan_tach,
|
||||
output vadj_test_1,
|
||||
output vadj_test_2
|
||||
);
|
||||
|
||||
// internal registers
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
// multi-ssi synchronization
|
||||
//
|
||||
assign mssi_sync = gpio_o[54];
|
||||
|
||||
assign {vadj_test_2,vadj_test_1} = 2'b11;
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(32)
|
||||
) i_iobuf_carrier (
|
||||
.dio_t(gpio_t[31:0]),
|
||||
.dio_i(gpio_o[31:0]),
|
||||
.dio_o(gpio_i[31:0]),
|
||||
.dio_p(gpio_bd));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(20)) i_iobuf (
|
||||
.dio_t ({gpio_t[51:32]}),
|
||||
.dio_i ({gpio_o[51:32]}),
|
||||
.dio_o ({gpio_i[51:32]}),
|
||||
.dio_p ({tx2_enable, // 51
|
||||
tx1_enable, // 50
|
||||
rx2_enable, // 49
|
||||
rx1_enable, // 48
|
||||
sm_fan_tach, // 47
|
||||
reset_trx, // 46
|
||||
mode, // 45
|
||||
gp_int, // 44
|
||||
dgpio_11, // 43
|
||||
dgpio_10, // 42
|
||||
dgpio_9, // 41
|
||||
dgpio_8, // 40
|
||||
dgpio_7, // 39
|
||||
dgpio_6, // 38
|
||||
dgpio_5, // 37
|
||||
dgpio_4, // 36
|
||||
dgpio_3, // 35
|
||||
dgpio_2, // 34
|
||||
dgpio_1, // 33
|
||||
dgpio_0 })); // 32
|
||||
|
||||
assign gpio_i[63:52] = gpio_o[63:52];
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
|
||||
.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
|
||||
.dio_i (iic_mux_scl_o_s),
|
||||
.dio_o (iic_mux_scl_i_s),
|
||||
.dio_p (iic_mux_scl));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
|
||||
.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
|
||||
.dio_i (iic_mux_sda_o_s),
|
||||
.dio_o (iic_mux_sda_i_s),
|
||||
.dio_p (iic_mux_sda));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif),
|
||||
//FMC connections
|
||||
.ref_clk (1'b0),
|
||||
.mssi_sync (mssi_sync),
|
||||
|
||||
.tx_output_enable (1'b1),
|
||||
|
||||
.rx1_dclk_in_n (rx1_dclk_out_n),
|
||||
.rx1_dclk_in_p (rx1_dclk_out_p),
|
||||
.rx1_idata_in_n (rx1_idata_out_n),
|
||||
.rx1_idata_in_p (rx1_idata_out_p),
|
||||
.rx1_qdata_in_n (rx1_qdata_out_n),
|
||||
.rx1_qdata_in_p (rx1_qdata_out_p),
|
||||
.rx1_strobe_in_n (rx1_strobe_out_n),
|
||||
.rx1_strobe_in_p (rx1_strobe_out_p),
|
||||
|
||||
.rx2_dclk_in_n (rx2_dclk_out_n),
|
||||
.rx2_dclk_in_p (rx2_dclk_out_p),
|
||||
.rx2_idata_in_n (rx2_idata_out_n),
|
||||
.rx2_idata_in_p (rx2_idata_out_p),
|
||||
.rx2_qdata_in_n (rx2_qdata_out_n),
|
||||
.rx2_qdata_in_p (rx2_qdata_out_p),
|
||||
.rx2_strobe_in_n (rx2_strobe_out_n),
|
||||
.rx2_strobe_in_p (rx2_strobe_out_p),
|
||||
|
||||
.tx1_dclk_out_n (tx1_dclk_in_n),
|
||||
.tx1_dclk_out_p (tx1_dclk_in_p),
|
||||
.tx1_dclk_in_n (tx1_dclk_out_n),
|
||||
.tx1_dclk_in_p (tx1_dclk_out_p),
|
||||
.tx1_idata_out_n (tx1_idata_in_n),
|
||||
.tx1_idata_out_p (tx1_idata_in_p),
|
||||
.tx1_qdata_out_n (tx1_qdata_in_n),
|
||||
.tx1_qdata_out_p (tx1_qdata_in_p),
|
||||
.tx1_strobe_out_n (tx1_strobe_in_n),
|
||||
.tx1_strobe_out_p (tx1_strobe_in_p),
|
||||
|
||||
.tx2_dclk_out_n (tx2_dclk_in_n),
|
||||
.tx2_dclk_out_p (tx2_dclk_in_p),
|
||||
.tx2_dclk_in_n (tx2_dclk_out_n),
|
||||
.tx2_dclk_in_p (tx2_dclk_out_p),
|
||||
.tx2_idata_out_n (tx2_idata_in_n),
|
||||
.tx2_idata_out_p (tx2_idata_in_p),
|
||||
.tx2_qdata_out_n (tx2_qdata_in_n),
|
||||
.tx2_qdata_out_p (tx2_qdata_in_p),
|
||||
.tx2_strobe_out_n (tx2_strobe_in_n),
|
||||
.tx2_strobe_out_p (tx2_strobe_in_p),
|
||||
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (spi_clk),
|
||||
.spi0_csn_0_o (spi_en),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi_do),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (spi_dio),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o ()
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue