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cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line 

Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.

If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
main
Istvan Csomortani 2020-10-02 08:09:23 +01:00 committed by István Csomortáni
parent dae1de0405
commit 11822e2824
1 changed files with 2 additions and 2 deletions
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4
projects/cn0540/coraz7s/system_constr.xdc
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@ -35,6 +35,6 @@ create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of
create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports cn0540_spi_sclk]
# input delays for MISO lines (SDO for the device)
set_input_delay -clock [get_clocks SCLK_clk] -max 0.6 [get_ports cn0540_spi_miso] -clock_fall
set_input_delay -clock [get_clocks SCLK_clk] -min 0.1 [get_ports cn0540_spi_miso] -clock_fall
set_input_delay -clock [get_clocks spi_clk] [get_property PERIOD [get_clocks spi_clk]] \
[get_ports -filter {NAME =~ "cn0540_spi_miso"}]