axi_dacfifo: Fix clock for read address generation

2017-02-24 15:47:04 +02:00 · 2017-02-24 15:47:04 +02:00 · 11623e79be
parent 3e596347fd
commit 11623e79be
1 changed files with 1 additions and 1 deletions
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v
@ -230,7 +230,7 @@ module axi_dacfifo_bypass #(

  assign dac_mem_rea_s = dac_valid & dac_mem_ready;

-  always @(posedge dma_clk) begin
+  always @(posedge dac_clk) begin
    if (dac_rst == 1'b1) begin
      dac_mem_raddr <= 'h0;
      dac_mem_raddr_g <= 'h0;