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fmcjesdadc1: VC707, Updated project to the latest framework

main
Adrian Costina 2015-03-30 18:08:19 +03:00
parent c7e4ba5083
commit 11379939d0
3 changed files with 36 additions and 74 deletions
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4
projects/fmcjesdadc1/vc707/system_constr.xdc
View File

@ -14,7 +14,7 @@ set_property -dict {PACKAGE_PIN A5 } [get_ports rx_data_n[3]]
set_property -dict {PACKAGE_PIN U31 IOSTANDARD LVCMOS18} [get_ports rx_sync] ; ## G36 FMC_HPC_LA33_P
set_property -dict {PACKAGE_PIN T31 IOSTANDARD LVCMOS18} [get_ports rx_sysref] ; ## G37 FMC_HPC_LA33_N
set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports spi_csn] ; ## G34 FMC_HPC_LA31_N
set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports spi_csn_0] ; ## G34 FMC_HPC_LA31_N
set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## G33 FMC_HPC_LA31_P
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## H37 FMC_HPC_LA32_P
@ -22,10 +22,8 @@ set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports spi_sdio
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 8.80 [get_nets i_system_wrapper/system_i/axi_ad9250_gt_rx_clk]
#create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {rx_div_clk}
#set_clock_groups -asynchronous -group {fmc_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]

1
projects/fmcjesdadc1/vc707/system_project.tcl
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@ -1,6 +1,7 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcjesdadc1_vc707
adi_project_files fmcjesdadc1_vc707 [list \

105
projects/fmcjesdadc1/vc707/system_top.v
View File

@ -85,21 +85,12 @@ module system_top (
linear_flash_dq_io,
gpio_lcd,
gpio_led,
gpio_sw,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref,
@ -107,7 +98,7 @@ module system_top (
rx_data_p,
rx_data_n,
spi_csn,
spi_csn_0,
spi_clk,
spi_sdio);
@ -154,22 +145,13 @@ module system_top (
output linear_flash_wen;
inout [15:0] linear_flash_dq_io;
output [ 6:0] gpio_lcd;
output [ 7:0] gpio_led;
input [12:0] gpio_sw;
inout [ 6:0] gpio_lcd;
inout [20:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [35:0] hdmi_data;
output spdif;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref;
@ -177,7 +159,7 @@ module system_top (
input [ 3:0] rx_data_p;
input [ 3:0] rx_data_n;
output spi_csn;
output spi_csn_0;
output spi_clk;
inout spi_sdio;
@ -190,12 +172,14 @@ module system_top (
// internal signals
wire [14:0] gpio_i;
wire [14:0] gpio_o;
wire [14:0] gpio_t;
wire rx_ref_clk;
wire spi_miso;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 7:0] spi_csn;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire rx_ref_clk;
wire adc_clk;
wire [127:0] rx_gt_data;
wire adc_0_enable_a;
@ -208,6 +192,12 @@ module system_top (
wire [31:0] adc_1_data_b;
wire [31:0] mb_intrs;
assign ddr3_1_p = 2'b11;
assign ddr3_1_n = 3'b000;
assign iic_rstn = 1'b1;
assign fan_pwm = 1'b1;
assign spi_csn_0 = spi_csn[0];
// pack & unpack here
always @(posedge adc_clk) begin
@ -285,19 +275,14 @@ module system_top (
.O (rx_ref_clk),
.ODIV2 ());
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
.dt (gpio_t),
.di (gpio_o),
.do (gpio_i),
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf (
.dt (gpio_t[20:0]),
.di (gpio_o[20:0]),
.do (gpio_i[20:0]),
.dio (gpio_bd));
assign spi_adc_clk = spi_clk;
assign spi_clk_clk = spi_clk;
assign fan_pwm = 1'b1;
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.spi_csn (spi_csn),
.spi_csn (spi_csn_0),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
@ -327,9 +312,13 @@ module system_top (
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.linear_flash_dq_io(linear_flash_dq_io),
.gpio_lcd_tri_o (gpio_lcd),
.gpio_led_tri_o (gpio_led),
.gpio_sw_tri_i (gpio_sw),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio_lcd_tri_io (gpio_lcd),
.adc_0_data_a (adc_0_data_a),
.adc_0_data_b (adc_0_data_b),
.adc_0_enable_a (adc_0_enable_a),
@ -349,38 +338,13 @@ module system_top (
.dma_1_data (dma_1_data),
.dma_1_sync (1'b1),
.dma_1_wr (dma_1_wr),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn),
.mb_intr_10 (mb_intrs[10]),
.mb_intr_11 (mb_intrs[11]),
.mb_intr_12 (mb_intrs[12]),
.mb_intr_13 (mb_intrs[13]),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_14 (mb_intrs[14]),
.mb_intr_15 (mb_intrs[15]),
.mb_intr_16 (mb_intrs[16]),
.mb_intr_17 (mb_intrs[17]),
.mb_intr_18 (mb_intrs[18]),
.mb_intr_19 (mb_intrs[19]),
.mb_intr_20 (mb_intrs[20]),
.mb_intr_21 (mb_intrs[21]),
.mb_intr_22 (mb_intrs[22]),
.mb_intr_23 (mb_intrs[23]),
.mb_intr_24 (mb_intrs[24]),
.mb_intr_25 (mb_intrs[25]),
.mb_intr_26 (mb_intrs[26]),
.mb_intr_27 (mb_intrs[27]),
.mb_intr_28 (mb_intrs[28]),
.mb_intr_29 (mb_intrs[29]),
.mb_intr_30 (mb_intrs[30]),
.mb_intr_31 (mb_intrs[31]),
.ad9250_0_dma_intr (mb_intrs[10]),
.ad9250_1_dma_intr (mb_intrs[11]),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
@ -390,7 +354,6 @@ module system_top (
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
@ -406,7 +369,7 @@ module system_top (
.rx_sysref (rx_sysref),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (1'b1),
.spi_csn_i (8'hff),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),