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ad_ip_jesd204_tpl_dac: Add option for an external synchronization pin 

The external synchronization signal should be synchronous with the
dac clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received

Added EXT_SYNC parameter to be able to keep the dac_sync original
behavior
main
Adrian Costina 2019-05-16 12:34:43 +01:00
parent 5d4c6701d9
commit 10c9f7a70d
5 changed files with 53 additions and 12 deletions
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12
library/common/up_dac_common.v
View File

@ -68,6 +68,7 @@ module up_dac_common #(
output dac_datafmt,
output [15:0] dac_datarate,
input dac_status,
input dac_sync_in_status,
input dac_status_unf,
input [31:0] dac_clk_ratio,
output up_dac_ce,
@ -147,6 +148,7 @@ module up_dac_common #(
wire up_rreq_s;
wire up_xfer_done_s;
wire up_status_s;
wire up_sync_in_status;
wire up_status_unf_s;
wire dac_sync_s;
wire dac_frame_s;
@ -389,7 +391,7 @@ module up_dac_common #(
7'h14: up_rdata_int <= {31'd0, up_dac_frame};
7'h15: up_rdata_int <= up_dac_clk_count_s;
7'h16: up_rdata_int <= dac_clk_ratio;
7'h17: up_rdata_int <= {31'd0, up_status_s};
7'h17: up_rdata_int <= {30'd0, up_sync_in_status, up_status_s};
7'h18: up_rdata_int <= {31'd0, up_dac_clksel};
7'h1c: up_rdata_int <= {3'd0, up_drp_rwn_s, up_drp_addr, 16'b0};
7'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
@ -440,14 +442,16 @@ module up_dac_common #(
dac_datafmt,
dac_datarate}));
up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_status_s,
.up_data_status ({up_sync_in_status,
up_status_s,
up_status_unf_s}),
.d_rst (dac_rst),
.d_clk (dac_clk),
.d_data_status ({ dac_status,
.d_data_status ({ dac_sync_in_status,
dac_status,
dac_status_unf}));
// generate frame and enable

14
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
View File

@ -39,7 +39,8 @@ module ad_ip_jesd204_tpl_dac #(
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1
parameter IQCORRECTION_DISABLE = 1,
parameter EXT_SYNC = 0
) (
// jesd interface
// link_clk is (line-rate/40)
@ -56,6 +57,10 @@ module ad_ip_jesd204_tpl_dac #(
input [NUM_LANES*8*OCTETS_PER_BEAT-1:0] dac_ddata,
input dac_dunf,
// external sync, should be on the link_clk clock domain
input dac_sync_in,
// axi interface
input s_axi_aclk,
@ -95,6 +100,7 @@ module ad_ip_jesd204_tpl_dac #(
// internal signals
wire dac_sync;
wire dac_sync_in_status;
wire dac_dds_format;
wire [NUM_CHANNELS*16-1:0] dac_dds_scale_0_s;
@ -152,6 +158,7 @@ module ad_ip_jesd204_tpl_dac #(
.dac_dunf (dac_dunf),
.dac_sync (dac_sync),
.dac_sync_in_status (dac_sync_in_status),
.dac_dds_format (dac_dds_format),
.dac_dds_scale_0 (dac_dds_scale_0_s),
@ -193,7 +200,8 @@ module ad_ip_jesd204_tpl_dac #(
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW)
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.EXT_SYNC (EXT_SYNC)
) i_core (
.clk (link_clk),
@ -207,6 +215,8 @@ module ad_ip_jesd204_tpl_dac #(
.dac_ddata (dac_ddata),
.dac_sync (dac_sync),
.dac_sync_in_status (dac_sync_in_status),
.dac_sync_in (dac_sync_in),
.dac_dds_format (dac_dds_format),
.dac_dds_scale_0 (dac_dds_scale_0_s),

35
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
View File

@ -37,7 +37,8 @@ module ad_ip_jesd204_tpl_dac_core #(
parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * BITS_PER_SAMPLE * NUM_CHANNELS,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16
parameter DDS_CORDIC_PHASE_DW = 16,
parameter EXT_SYNC = 0
) (
// dac interface
input clk,
@ -53,6 +54,11 @@ module ad_ip_jesd204_tpl_dac_core #(
// Configuration interface
input dac_sync,
input dac_sync_in,
output dac_sync_in_status,
input dac_dds_format,
input [NUM_CHANNELS*4-1:0] dac_data_sel,
@ -78,13 +84,31 @@ module ad_ip_jesd204_tpl_dac_core #(
localparam DAC_DATA_WIDTH = DAC_CDW * NUM_CHANNELS;
localparam DMA_CDW = DATA_PATH_WIDTH * BITS_PER_SAMPLE;
assign link_valid = 1'b1;
wire [DAC_DATA_WIDTH-1:0] dac_data_s;
wire [DAC_CDW-1:0] pn7_data;
wire [DAC_CDW-1:0] pn15_data;
reg dac_sync_in_d1 ='d0;
reg dac_sync_in_arm ='d0;
reg dac_sync_d1 = 'd0;
assign link_valid = 1'b1;
assign dac_sync_in_status = dac_sync_in_arm;
always @(posedge clk) begin
dac_sync_d1 <= dac_sync;
dac_sync_in_d1 <= dac_sync_in;
if ((~dac_sync_d1&dac_sync) == 1'b1) begin
dac_sync_in_arm <= 1'b1;
end else if ((~dac_sync_in_d1&dac_sync_in) == 1'b1) begin
dac_sync_in_arm <= 1'b0;
end else if (EXT_SYNC == 1'b0) begin
dac_sync_in_arm <= 1'b0;
end
end
// device interface
ad_ip_jesd204_tpl_dac_framer #(
@ -107,7 +131,7 @@ module ad_ip_jesd204_tpl_dac_core #(
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION)
) i_pn_gen (
.clk (clk),
.reset (dac_sync),
.reset (dac_sync_in_arm),
.pn7_data (pn7_data),
.pn15_data (pn15_data)
@ -115,8 +139,7 @@ module ad_ip_jesd204_tpl_dac_core #(
// dac valid
assign dac_valid = {NUM_CHANNELS{1'b1}};
assign dac_valid = {NUM_CHANNELS{~dac_sync_in_arm}};
generate
genvar i;
@ -147,7 +170,7 @@ module ad_ip_jesd204_tpl_dac_core #(
.pn7_data (pn7_data),
.pn15_data (pn15_data),
.dac_data_sync (dac_sync),
.dac_data_sync (dac_sync_in_arm),
.dac_dds_format (dac_dds_format),
.dac_data_sel (dac_data_sel[4*i+:4]),

1
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
View File

@ -145,6 +145,7 @@ set i 0
foreach {k v w} {
"DATAPATH_DISABLE" "Disable Datapath" "checkBox" \
"EXT_SYNC" "Enable external SYNC" "checkBox" \
"IQCORRECTION_DISABLE" "Disable IQ Correction" "checkBox" \
"DDS_TYPE" "DDS Type" "comboBox" \
"DDS_CORDIC_DW" "CORDIC DDS Data Width" "text" \

3
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
View File

@ -68,6 +68,8 @@ module ad_ip_jesd204_tpl_dac_regmap #(
output dac_sync,
input dac_sync_in_status,
output [NUM_CHANNELS*4-1:0] dac_data_sel,
output dac_dds_format,
@ -198,6 +200,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
.dac_clk (link_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync),
.dac_sync_in_status (dac_sync_in_status),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),