diff --git a/projects/ad9082_fmca_ebz/zc706/Makefile b/projects/ad9082_fmca_ebz/zc706/Makefile
new file mode 100644
index 000000000..9ffd152dc
--- /dev/null
+++ b/projects/ad9082_fmca_ebz/zc706/Makefile
@@ -0,0 +1,39 @@
+####################################################################################
+## Copyright 2018(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad9081_fmca_ebz_zc706
+
+M_DEPS += ../../ad9081_fmca_ebz/zc706/timing_constr.xdc
+M_DEPS += ../../ad9081_fmca_ebz/zc706/system_constr.xdc
+M_DEPS += ../../ad9081_fmca_ebz/zc706/system_top.v
+M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+M_DEPS += ../../common/zc706/zc706_system_constr.xdc
+M_DEPS += ../../common/zc706/zc706_system_bd.tcl
+M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
+M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
+M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_3w_spi.v
+
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_hdmi_tx
+LIB_DEPS += axi_spdif_tx
+LIB_DEPS += axi_sysid
+LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
+LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
+LIB_DEPS += jesd204/axi_jesd204_rx
+LIB_DEPS += jesd204/axi_jesd204_tx
+LIB_DEPS += jesd204/jesd204_rx
+LIB_DEPS += jesd204/jesd204_tx
+LIB_DEPS += sysid_rom
+LIB_DEPS += util_adcfifo
+LIB_DEPS += util_dacfifo
+LIB_DEPS += util_pack/util_cpack2
+LIB_DEPS += util_pack/util_upack2
+LIB_DEPS += xilinx/axi_adxcvr
+LIB_DEPS += xilinx/util_adxcvr
+
+include ../../scripts/project-xilinx.mk
diff --git a/projects/ad9082_fmca_ebz/zc706/system_bd.tcl b/projects/ad9082_fmca_ebz/zc706/system_bd.tcl
new file mode 100644
index 000000000..f1866e99f
--- /dev/null
+++ b/projects/ad9082_fmca_ebz/zc706/system_bd.tcl
@@ -0,0 +1,20 @@
+
+## ADC FIFO depth in samples per converter
+set adc_fifo_samples_per_converter [expr 32*1024]
+## DAC FIFO depth in samples per converter
+set dac_fifo_samples_per_converter [expr 32*1024]
+
+source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
+source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
+source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
+source ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file
+
diff --git a/projects/ad9082_fmca_ebz/zc706/system_project.tcl b/projects/ad9082_fmca_ebz/zc706/system_project.tcl
new file mode 100644
index 000000000..31b4dd18b
--- /dev/null
+++ b/projects/ad9082_fmca_ebz/zc706/system_project.tcl
@@ -0,0 +1,60 @@
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+# get_env_param retrieves parameter value from the environment if exists,
+# other case use the default value
+#
+#   Use over-writable parameters from the environment.
+#
+#    e.g.
+#      make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1
+#      make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1
+
+#
+# Parameter description:
+#   JESD_MODE : Used link layer encoder mode
+#      64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
+#      8B10B  - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
+#
+#   RX_RATE :  Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
+#   TX_RATE :  Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
+#   [RX/TX]_PLL_SEL :  Used PLL in the Xilinx PHY used in 64B66B mode
+#                      Encoding is:
+#                         0 - CPLL
+#                         1 - QPLL0
+#                         2 - QPLL1
+#   REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
+#   [RX/TX]_JESD_M : Number of converters per link
+#   [RX/TX]_JESD_L : Number of lanes per link
+#   [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
+#   [RX/TX]_NUM_LINKS : Number of links
+#
+#  
+#  !!! For this carrier only 8B10B mode is supported !!!
+#
+
+adi_project ad9082_fmca_ebz_zc706 0 [list \
+  JESD_MODE    8B10B \
+  RX_JESD_M    [get_env_param RX_JESD_M    4 ] \
+  RX_JESD_L    [get_env_param RX_JESD_L    8 ] \
+  RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
+  RX_JESD_NP   [get_env_param RX_JESD_NP   16] \
+  RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
+  TX_JESD_M    [get_env_param TX_JESD_M    4 ] \
+  TX_JESD_L    [get_env_param TX_JESD_L    8 ] \
+  TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
+  TX_JESD_NP   [get_env_param TX_JESD_NP   16] \
+  TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
+]
+
+adi_project_files ad9082_fmca_ebz_zc706 [list \
+  "../../ad9081_fmca_ebz/zc706/system_top.v" \
+  "../../ad9081_fmca_ebz/zc706/system_constr.xdc" \
+  "../../ad9081_fmca_ebz/zc706/timing_constr.xdc" \
+  "../../../library/common/ad_3w_spi.v" \
+  "$ad_hdl_dir/library/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
+
+adi_project_run ad9082_fmca_ebz_zc706
+