constraints: Split the regmap CDC constraint into separate file

library/altera/common/up_clock_mon_constr.sdc

@@ -0,0 +1,4 @@
+
+set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|d_count_toggle*]       -to [get_registers *up_clock_mon:i_clock_mon|up_count_toggle_m1*]
+set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|d_count_hold*]         -to [get_registers *up_clock_mon:i_clock_mon|up_d_count*]
+set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|up_count_toggle*]      -to [get_registers *up_clock_mon:i_clock_mon|d_count_toggle_m1*]

library/altera/common/up_rst_constr.sdc

@@ -0,0 +1,2 @@
+
+set_false_path  -from [get_registers *up_*preset*]                                    -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*]

library/altera/common/up_xfer_cntrl_constr.sdc

@@ -0,0 +1,4 @@
+
+set_false_path  -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_xfer_toggle*]      -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_state_m1*]
+set_false_path  -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_toggle*]     -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_xfer_toggle_m1*]
+set_false_path  -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_data*]       -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_data_cntrl*]

library/altera/common/up_xfer_status_constr.sdc

@@ -0,0 +1,4 @@
+
+set_false_path  -from [get_registers *up_xfer_status:i_xfer_status|up_xfer_toggle*]   -to [get_registers *up_xfer_status:i_xfer_status|d_xfer_state_m1*]
+set_false_path  -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_toggle*]    -to [get_registers *up_xfer_status:i_xfer_status|up_xfer_toggle_m1*]
+set_false_path  -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_data*]      -to [get_registers *up_xfer_status:i_xfer_status|up_data_status*]

library/axi_ad9122/axi_ad9122_hw.tcl

@@ -21,7 +21,10 @@ ad_ip_files axi_ad9122 [list \
     axi_ad9122_core.v \
     axi_ad9122_if.v \
     axi_ad9122.v \
-    $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
+    $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc \
+    $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc \
+    $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \
+    $ad_hdl_dir/library/altera/common/up_rst_constr.sdc \
     axi_ad9122_constr.sdc] \
     axi_ad9122_fileset
 

library/axi_ad9144/axi_ad9144_hw.tcl

@@ -30,7 +30,10 @@ add_fileset_file axi_ad9144_channel.v VERILOG PATH axi_ad9144_channel.v
 add_fileset_file axi_ad9144_core.v    VERILOG PATH axi_ad9144_core.v
 add_fileset_file axi_ad9144_if.v      VERILOG PATH axi_ad9144_if.v
 add_fileset_file axi_ad9144.v         VERILOG PATH axi_ad9144.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
+add_fileset_file up_xfer_status_constr.sdc  SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
+add_fileset_file up_clock_mon_constr.sdc  SDC PATH $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
+add_fileset_file up_rst_constr.sdc  SDC PATH $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
 
 # parameters
 

library/axi_ad9152/axi_ad9152_hw.tcl

@@ -29,7 +29,10 @@ add_fileset_file axi_ad9152_channel.v VERILOG PATH axi_ad9152_channel.v
 add_fileset_file axi_ad9152_core.v    VERILOG PATH axi_ad9152_core.v
 add_fileset_file axi_ad9152_if.v      VERILOG PATH axi_ad9152_if.v
 add_fileset_file axi_ad9152.v         VERILOG PATH axi_ad9152.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file up_xfer_cntrl_constr.sdc   SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
+add_fileset_file up_xfer_status_constr.sdc  SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
+add_fileset_file up_clock_mon_constr.sdc    SDC PATH $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
+add_fileset_file up_rst_constr.sdc          SDC PATH $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
 
 # parameters
 

library/axi_ad9250/axi_ad9250_hw.tcl

@@ -29,7 +29,10 @@ add_fileset_file axi_ad9250_pnmon.v   VERILOG PATH axi_ad9250_pnmon.v
 add_fileset_file axi_ad9250_if.v      VERILOG PATH axi_ad9250_if.v
 add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v
 add_fileset_file axi_ad9250.v         VERILOG PATH axi_ad9250.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file up_xfer_cntrl_constr.sdc   SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
+add_fileset_file up_xfer_status_constr.sdc  SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
+add_fileset_file up_clock_mon_constr.sdc    SDC PATH  $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
+add_fileset_file up_rst_constr.sdc          SDC PATH  $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
 
 # parameters
 

library/axi_ad9361/axi_ad9361_hw.tcl

@@ -39,7 +39,10 @@ ad_ip_files axi_ad9361 [list\
   axi_ad9361_tdd.v \
   axi_ad9361_tdd_if.v \
   axi_ad9361.v \
-  $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
+  $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc \
+  $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc \
+  $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \
+  $ad_hdl_dir/library/altera/common/up_rst_constr.sdc \
   axi_ad9361_constr.sdc] \
   axi_ad9361_fileset
 
@@ -66,7 +69,7 @@ ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group}
 # interfaces
 
 ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
- 
+
 ad_alt_intf signal dac_sync_in input 1
 ad_alt_intf signal dac_sync_out output 1
 ad_alt_intf signal tdd_sync input 1

library/axi_ad9371/axi_ad9371_hw.tcl

@@ -38,7 +38,10 @@ add_fileset_file axi_ad9371_rx_os.v         VERILOG PATH axi_ad9371_rx_os.v
 add_fileset_file axi_ad9371_tx_channel.v    VERILOG PATH axi_ad9371_tx_channel.v
 add_fileset_file axi_ad9371_tx.v            VERILOG PATH axi_ad9371_tx.v
 add_fileset_file axi_ad9371.v               VERILOG PATH axi_ad9371.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc       SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file up_xfer_cntrl_constr.sdc   SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
+add_fileset_file up_xfer_status_constr.sdc  SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
+add_fileset_file up_clock_mon_constr.sdc    SDC PATH  $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
+add_fileset_file up_rst_constr.sdc          SDC PATH  $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
 
 # parameters
 

library/axi_ad9671/axi_ad9671_hw.tcl

@@ -30,7 +30,10 @@ add_fileset_file axi_ad9671_pnmon.v   VERILOG PATH axi_ad9671_pnmon.v
 add_fileset_file axi_ad9671_if.v      VERILOG PATH axi_ad9671_if.v
 add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v
 add_fileset_file axi_ad9671.v         VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file up_xfer_cntrl_constr.sdc   SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
+add_fileset_file up_xfer_status_constr.sdc  SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
+add_fileset_file up_clock_mon_constr.sdc    SDC PATH  $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
+add_fileset_file up_rst_constr.sdc          SDC PATH  $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
 
 # parameters
 

library/axi_ad9680/axi_ad9680_hw.tcl

@@ -29,7 +29,10 @@ add_fileset_file axi_ad9680_pnmon.v   VERILOG PATH axi_ad9680_pnmon.v
 add_fileset_file axi_ad9680_channel.v VERILOG PATH axi_ad9680_channel.v
 add_fileset_file axi_ad9680_if.v      VERILOG PATH axi_ad9680_if.v
 add_fileset_file axi_ad9680.v         VERILOG PATH axi_ad9680.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
+add_fileset_file up_xfer_cntrl_constr.sdc   SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
+add_fileset_file up_xfer_status_constr.sdc  SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
+add_fileset_file up_clock_mon_constr.sdc    SDC PATH  $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
+add_fileset_file up_rst_constr.sdc          SDC PATH  $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
 
 # parameters
 

library/axi_ad9684/axi_ad9684_hw.tcl

@@ -19,7 +19,10 @@ ad_ip_files axi_ad9684 [list \
     axi_ad9684_if.v \
     axi_ad9684_channel.v \
     axi_ad9684.v \
-    $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
+    $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc \
+    $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc \
+    $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \
+    $ad_hdl_dir/library/altera/common/up_rst_constr.sdc \
     axi_ad9684_constr.sdc] \
     axi_ad9684_fileset
 

library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl

@@ -30,8 +30,11 @@ add_fileset_file axi_hdmi_tx_vdma.v       VERILOG PATH axi_hdmi_tx_vdma.v
 add_fileset_file axi_hdmi_tx_es.v         VERILOG PATH axi_hdmi_tx_es.v
 add_fileset_file axi_hdmi_tx_core.v       VERILOG PATH axi_hdmi_tx_core.v
 add_fileset_file axi_hdmi_tx.v            VERILOG PATH axi_hdmi_tx.v TOP_LEVEL_FILE
-add_fileset_file ad_axi_ip_constr.sdc     SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
-add_fileset_file axi_hdmi_tx_constr.sdc   SDC     PATH axi_hdmi_tx_constr.sdc
+add_fileset_file up_xfer_cntrl_constr.sdc   SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
+add_fileset_file up_xfer_status_constr.sdc  SDC PATH  $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
+add_fileset_file up_clock_mon_constr.sdc    SDC PATH  $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
+add_fileset_file up_rst_constr.sdc          SDC PATH  $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
+add_fileset_file axi_hdmi_tx_constr.sdc     SDC PATH axi_hdmi_tx_constr.sdc
 
 # parameters
 

library/common/ad_axi_ip_constr.sdc

@@ -1,12 +0,0 @@
-
-set_false_path  -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_xfer_toggle*]      -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_state_m1*]
-set_false_path  -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_toggle*]     -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_xfer_toggle_m1*]
-set_false_path  -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_data*]       -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_data_cntrl*]
-set_false_path  -from [get_registers *up_xfer_status:i_xfer_status|up_xfer_toggle*]   -to [get_registers *up_xfer_status:i_xfer_status|d_xfer_state_m1*]
-set_false_path  -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_toggle*]    -to [get_registers *up_xfer_status:i_xfer_status|up_xfer_toggle_m1*]
-set_false_path  -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_data*]      -to [get_registers *up_xfer_status:i_xfer_status|up_data_status*] 
-set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|d_count_toggle*]       -to [get_registers *up_clock_mon:i_clock_mon|up_count_toggle_m1*]
-set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|d_count_hold*]         -to [get_registers *up_clock_mon:i_clock_mon|up_d_count*]
-set_false_path  -from [get_registers *up_clock_mon:i_clock_mon|up_count_toggle*]      -to [get_registers *up_clock_mon:i_clock_mon|d_count_toggle_m1*]
-set_false_path  -from [get_registers *up_*preset*]                                    -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*]
-