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intel/adi_jesd204: Add support for external core clock 

In Subclass 1 mode, we need to use a separate clock (device clock) to
drive the link and transport layer of the interface. Implement the
required infrastructure for this scenario.

The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
main
Istvan Csomortani 2019-08-23 13:56:43 +01:00 committed by István Csomortáni
parent aeaefd2c1c
commit 103cbe73dc
1 changed files with 35 additions and 5 deletions
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40
library/intel/adi_jesd204/adi_jesd204_hw.tcl
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@ -119,6 +119,12 @@ ad_ip_parameter SOFT_PCS BOOLEAN true false { \
DISPLAY_NAME "Enable Soft PCS" \
}
ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN 0 false { \
DISPLAY_HINT "radio" \
DISPLAY_NAME "External Device Clock Enable"\
ALLOWED_RANGES { "0:Disabled" "1:Enabled" }
}
proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
add_instance phy_reset_control altera_xcvr_reset_control
set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true
@ -247,6 +253,7 @@ proc jesd204_compose {} {
set soft_pcs [get_parameter_value "SOFT_PCS"]
set device_family [get_parameter_value "DEVICE_FAMILY"]
set device [get_parameter_value "DEVICE"]
set ext_device_clk_en [get_parameter_value "EXT_DEVICE_CLK_EN"]
set pllclk_frequency [expr $lane_rate / 2]
set linkclk_frequency [expr $lane_rate / 40]
@ -291,12 +298,15 @@ proc jesd204_compose {} {
set_instance_parameter_value link_pll {rcfg_separate_avmm_busy} {1}
add_connection ref_clock.out_clk link_pll.pll_refclk0
## link clock configuration (also known as device clock, which will be used
## by the upper layers for the data path, it can come from the PCS or external)
add_instance link_clock altera_clock_bridge
set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2
add_connection link_pll.outclk0 link_clock.in_clk
add_interface link_clk clock source
set_interface_property link_clk EXPORT_OF link_clock.out_clk
add_instance link_reset altera_reset_bridge
set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2
@ -346,12 +356,27 @@ proc jesd204_compose {} {
set_instance_parameter_value phy NUM_OF_LANES $num_of_lanes
set_instance_parameter_value phy REGISTER_INPUTS $register_inputs
set_instance_parameter_value phy LANE_INVERT $lane_invert
set_instance_parameter_value phy EXT_DEVICE_CLK_EN $ext_device_clk_en
add_connection link_clock.out_clk_1 phy.link_clk
add_connection link_reset.out_reset phy.link_reset
add_connection sys_clock.clk phy.reconfig_clk
add_connection sys_clock.clk_reset phy.reconfig_reset
## connect the required device clock
if {$ext_device_clk_en} {
add_instance ext_device_clock altera_clock_bridge
set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2
add_interface device_clk clock sink
set_interface_property device_clk EXPORT_OF ext_device_clock.in_clk
add_connection ext_device_clock.out_clk phy.device_clk
set_interface_property link_clk EXPORT_OF ext_device_clock.out_clk_1
} else {
set_interface_property link_clk EXPORT_OF link_clock.out_clk
}
if {$tx_or_rx_n} {
set tx_rx "tx"
set data_direction sink
@ -378,13 +403,18 @@ proc jesd204_compose {} {
add_connection sys_clock.clk axi_jesd204_${tx_rx}.s_axi_clock
add_connection sys_clock.clk_reset axi_jesd204_${tx_rx}.s_axi_reset
add_connection link_clock.out_clk_1 axi_jesd204_${tx_rx}.core_clock
add_connection link_reset.out_reset axi_jesd204_${tx_rx}.core_reset_ext
add_instance jesd204_${tx_rx} jesd204_${tx_rx}
set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
add_connection link_clock.out_clk_1 jesd204_${tx_rx}.clock
if {$ext_device_clk_en} {
add_connection ext_device_clock.out_clk axi_jesd204_${tx_rx}.core_clock
add_connection ext_device_clock.out_clk jesd204_${tx_rx}.clock
} else {
add_connection link_clock.out_clk_1 axi_jesd204_${tx_rx}.core_clock
add_connection link_clock.out_clk_1 jesd204_${tx_rx}.clock
}
add_connection link_reset.out_reset axi_jesd204_${tx_rx}.core_reset_ext
add_connection axi_jesd204_${tx_rx}.core_reset jesd204_${tx_rx}.reset
foreach intf $jesd204_intfs {