avl_dacfifo: Delete unused files
Istvan Csomortani
István Csomortáni
parent
5b58fb67f0
commit
0fe3d4423d
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@ -10,8 +10,6 @@ ALTERA_DEPS += ../../common/ad_g2b.v
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ALTERA_DEPS += ../../common/ad_mem.v
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ALTERA_DEPS += ../../common/util_delay.v
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ALTERA_DEPS += avl_dacfifo.v
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ALTERA_DEPS += avl_dacfifo_byteenable_coder.v
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ALTERA_DEPS += avl_dacfifo_byteenable_decoder.v
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ALTERA_DEPS += avl_dacfifo_constr.sdc
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ALTERA_DEPS += avl_dacfifo_hw.tcl
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ALTERA_DEPS += avl_dacfifo_rd.v
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@ -1,229 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module avl_dacfifo_byteenable_coder #(
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parameter MEM_RATIO = 8,
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parameter LAST_BEATS_WIDTH = 3) (
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input avl_clk,
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input [LAST_BEATS_WIDTH-1:0] avl_last_beats,
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input avl_enable,
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output reg [ 63:0] avl_byteenable
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);
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always @(posedge avl_clk) begin
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if (avl_enable == 1'b1) begin
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case (avl_last_beats)
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0 : begin
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case (MEM_RATIO)
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2 : avl_byteenable <= {32'b0, {32{1'b1}}};
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4 : avl_byteenable <= {48'b0, {16{1'b1}}};
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8 : avl_byteenable <= {56'b0, {8{1'b1}}};
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16 : avl_byteenable <= {60'b0, {4{1'b1}}};
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32 : avl_byteenable <= {62'b0, {2{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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1 : begin
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case (MEM_RATIO)
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4 : avl_byteenable <= {32'b0, {32{1'b1}}};
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8 : avl_byteenable <= {48'b0, {16{1'b1}}};
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16 : avl_byteenable <= {56'b0, {8{1'b1}}};
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32 : avl_byteenable <= {60'b0, {4{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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2 : begin
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case (MEM_RATIO)
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4 : avl_byteenable <= {16'b0, {48{1'b1}}};
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8 : avl_byteenable <= {40'b0, {24{1'b1}}};
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16 : avl_byteenable <= {52'b0, {12{1'b1}}};
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32 : avl_byteenable <= {58'b0, {6{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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3 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {32'b0, {32{1'b1}}};
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16 : avl_byteenable <= {48'b0, {16{1'b1}}};
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32 : avl_byteenable <= {56'b0, {8{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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4 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {24'b0, {40{1'b1}}};
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16 : avl_byteenable <= {44'b0, {20{1'b1}}};
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32 : avl_byteenable <= {54'b0, {10{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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5 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {16'b0, {48{1'b1}}};
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16 : avl_byteenable <= {40'b0, {24{1'b1}}};
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32 : avl_byteenable <= {52'b0, {12{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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6 : begin
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case (MEM_RATIO)
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8 : avl_byteenable <= {8'b0, {56{1'b1}}};
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16 : avl_byteenable <= {36'b0, {28{1'b1}}};
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32 : avl_byteenable <= {50'b0, {14{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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7 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {32'b0, {32{1'b1}}};
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32 : avl_byteenable <= {48'b0, {16{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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8 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {28'b0, {36{1'b1}}};
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32 : avl_byteenable <= {46'b0, {18{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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9 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {24'b0, {40{1'b1}}};
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32 : avl_byteenable <= {44'b0, {20{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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10 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {20'b0, {44{1'b1}}};
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32 : avl_byteenable <= {42'b0, {22{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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11 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {16'b0, {48{1'b1}}};
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32 : avl_byteenable <= {40'b0, {24{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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12 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {12'b0, {52{1'b1}}};
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32 : avl_byteenable <= {38'b0, {26{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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13 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {8'b0, {56{1'b1}}};
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32 : avl_byteenable <= {36'b0, {28{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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14 : begin
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case (MEM_RATIO)
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16 : avl_byteenable <= {4'b0, {60{1'b1}}};
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32 : avl_byteenable <= {34'b0, {30{1'b1}}};
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end
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15 : begin
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case (MEM_RATIO)
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32 : avl_byteenable <= {32'b0, {32{1'b1}}};
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default: avl_byteenable <= {64{1'b1}};
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endcase
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end
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16 : begin
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avl_byteenable <= {30'b0, {34{1'b1}}};
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end
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17 : begin
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avl_byteenable <= {28'b0, {36{1'b1}}};
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end
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18 : begin
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avl_byteenable <= {26'b0, {38{1'b1}}};
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end
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19 : begin
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avl_byteenable <= {24'b0, {40{1'b1}}};
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end
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20 : begin
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avl_byteenable <= {22'b0, {42{1'b1}}};
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end
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21 : begin
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avl_byteenable <= {20'b0, {44{1'b1}}};
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end
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22 : begin
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avl_byteenable <= {18'b0, {46{1'b1}}};
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end
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23 : begin
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avl_byteenable <= {16'b0, {48{1'b1}}};
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end
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24 : begin
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avl_byteenable <= {14'b0, {50{1'b1}}};
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end
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25 : begin
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avl_byteenable <= {12'b0, {52{1'b1}}};
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end
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26 : begin
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avl_byteenable <= {10'b0, {54{1'b1}}};
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end
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27 : begin
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avl_byteenable <= {8'b0, {56{1'b1}}};
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end
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28 : begin
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avl_byteenable <= {6'b0, {58{1'b1}}};
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end
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29 : begin
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avl_byteenable <= {4'b0, {60{1'b1}}};
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end
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30 : begin
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avl_byteenable <= {2'b0, {62{1'b1}}};
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end
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default : avl_byteenable <= {64{1'b1}};
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endcase
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end else begin
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avl_byteenable <= {64{1'b1}};
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end
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end
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endmodule
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@ -1,274 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
|
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//
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||||
// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module avl_dacfifo_byteenable_decoder #(
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parameter MEM_RATIO = 8,
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parameter LAST_BEATS_WIDTH = 3) (
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input avl_clk,
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input [ 63:0] avl_byteenable,
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input avl_enable,
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output reg [LAST_BEATS_WIDTH-1:0] avl_last_beats
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);
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always @(posedge avl_clk) begin
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if (avl_enable == 1'b1) begin
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case (avl_byteenable)
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64'b0000000000000000000000000000000000000000000000000000000000000011: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 0;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000000000000000000001111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 1;
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16 : avl_last_beats <= 0;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000000000000000000111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 2;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000000000000000011111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 3;
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16 : avl_last_beats <= 1;
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8 : avl_last_beats <= 0;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000000000000001111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 4;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000000000000111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 5;
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16 : avl_last_beats <= 2;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000000000011111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 6;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000000001111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 7;
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16 : avl_last_beats <= 3;
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8 : avl_last_beats <= 1;
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4 : avl_last_beats <= 0;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000000111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 8;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000000011111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 9;
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16 : avl_last_beats <= 4;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000001111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 10;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000000111111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 11;
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16 : avl_last_beats <= 5;
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8 : avl_last_beats <= 2;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000000011111111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 12;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000001111111111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 13;
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16 : avl_last_beats <= 6;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000000111111111111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 14;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000000011111111111111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 15;
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16 : avl_last_beats <= 7;
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8 : avl_last_beats <= 3;
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4 : avl_last_beats <= 1;
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2 : avl_last_beats <= 0;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000001111111111111111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 16;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000000111111111111111111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 17;
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16 : avl_last_beats <= 8;
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default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
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endcase
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end
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64'b0000000000000000000000000011111111111111111111111111111111111111: begin
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case (MEM_RATIO)
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32 : avl_last_beats <= 18;
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||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000000000000000000001111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 19;
|
||||
16 : avl_last_beats <= 9;
|
||||
8 : avl_last_beats <= 4;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000000000000000000111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 20;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000000000000000011111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 21;
|
||||
16 : avl_last_beats <= 10;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000000000000001111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 22;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000000000000111111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 23;
|
||||
16 : avl_last_beats <= 11;
|
||||
8 : avl_last_beats <= 5;
|
||||
4 : avl_last_beats <= 2;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000000000011111111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 24;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000000001111111111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 25;
|
||||
16 : avl_last_beats <= 12;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000000111111111111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 26;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000000011111111111111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 27;
|
||||
16 : avl_last_beats <= 13;
|
||||
8 : avl_last_beats <= 6;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000001111111111111111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 28;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0000111111111111111111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 29;
|
||||
16 : avl_last_beats <= 14;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
64'b0011111111111111111111111111111111111111111111111111111111111111: begin
|
||||
case (MEM_RATIO)
|
||||
32 : avl_last_beats <= 30;
|
||||
default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end
|
||||
default: avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
endcase
|
||||
end else begin
|
||||
avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -10,8 +10,6 @@ ad_ip_files avl_dacfifo [list\
|
|||
$ad_hdl_dir/library/common/ad_g2b.v \
|
||||
$ad_hdl_dir/library/common/ad_mem.v \
|
||||
util_dacfifo_bypass.v \
|
||||
avl_dacfifo_byteenable_coder.v \
|
||||
avl_dacfifo_byteenable_decoder.v \
|
||||
avl_dacfifo_wr.v \
|
||||
avl_dacfifo_rd.v \
|
||||
avl_dacfifo.v \
|
||||
|
|
|
|||
Loading…
Reference in New Issue