From 0fe3d4423d716f5a6b0972b4cfd99f98b56ba685 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 11 Apr 2018 10:19:19 +0100 Subject: [PATCH] avl_dacfifo: Delete unused files --- library/altera/avl_dacfifo/Makefile | 2 - .../avl_dacfifo_byteenable_coder.v | 229 --------------- .../avl_dacfifo_byteenable_decoder.v | 274 ------------------ library/altera/avl_dacfifo/avl_dacfifo_hw.tcl | 2 - 4 files changed, 507 deletions(-) delete mode 100644 library/altera/avl_dacfifo/avl_dacfifo_byteenable_coder.v delete mode 100644 library/altera/avl_dacfifo/avl_dacfifo_byteenable_decoder.v diff --git a/library/altera/avl_dacfifo/Makefile b/library/altera/avl_dacfifo/Makefile index 6d2cc1a19..9cd8dd609 100644 --- a/library/altera/avl_dacfifo/Makefile +++ b/library/altera/avl_dacfifo/Makefile @@ -10,8 +10,6 @@ ALTERA_DEPS += ../../common/ad_g2b.v ALTERA_DEPS += ../../common/ad_mem.v ALTERA_DEPS += ../../common/util_delay.v ALTERA_DEPS += avl_dacfifo.v -ALTERA_DEPS += avl_dacfifo_byteenable_coder.v -ALTERA_DEPS += avl_dacfifo_byteenable_decoder.v ALTERA_DEPS += avl_dacfifo_constr.sdc ALTERA_DEPS += avl_dacfifo_hw.tcl ALTERA_DEPS += avl_dacfifo_rd.v diff --git a/library/altera/avl_dacfifo/avl_dacfifo_byteenable_coder.v b/library/altera/avl_dacfifo/avl_dacfifo_byteenable_coder.v deleted file mode 100644 index b4c3907c1..000000000 --- a/library/altera/avl_dacfifo/avl_dacfifo_byteenable_coder.v +++ /dev/null @@ -1,229 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module avl_dacfifo_byteenable_coder #( - - parameter MEM_RATIO = 8, - parameter LAST_BEATS_WIDTH = 3) ( - - input avl_clk, - - input [LAST_BEATS_WIDTH-1:0] avl_last_beats, - input avl_enable, - - output reg [ 63:0] avl_byteenable - -); - - always @(posedge avl_clk) begin - if (avl_enable == 1'b1) begin - case (avl_last_beats) - 0 : begin - case (MEM_RATIO) - 2 : avl_byteenable <= {32'b0, {32{1'b1}}}; - 4 : avl_byteenable <= {48'b0, {16{1'b1}}}; - 8 : avl_byteenable <= {56'b0, {8{1'b1}}}; - 16 : avl_byteenable <= {60'b0, {4{1'b1}}}; - 32 : avl_byteenable <= {62'b0, {2{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 1 : begin - case (MEM_RATIO) - 4 : avl_byteenable <= {32'b0, {32{1'b1}}}; - 8 : avl_byteenable <= {48'b0, {16{1'b1}}}; - 16 : avl_byteenable <= {56'b0, {8{1'b1}}}; - 32 : avl_byteenable <= {60'b0, {4{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 2 : begin - case (MEM_RATIO) - 4 : avl_byteenable <= {16'b0, {48{1'b1}}}; - 8 : avl_byteenable <= {40'b0, {24{1'b1}}}; - 16 : avl_byteenable <= {52'b0, {12{1'b1}}}; - 32 : avl_byteenable <= {58'b0, {6{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 3 : begin - case (MEM_RATIO) - 8 : avl_byteenable <= {32'b0, {32{1'b1}}}; - 16 : avl_byteenable <= {48'b0, {16{1'b1}}}; - 32 : avl_byteenable <= {56'b0, {8{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 4 : begin - case (MEM_RATIO) - 8 : avl_byteenable <= {24'b0, {40{1'b1}}}; - 16 : avl_byteenable <= {44'b0, {20{1'b1}}}; - 32 : avl_byteenable <= {54'b0, {10{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 5 : begin - case (MEM_RATIO) - 8 : avl_byteenable <= {16'b0, {48{1'b1}}}; - 16 : avl_byteenable <= {40'b0, {24{1'b1}}}; - 32 : avl_byteenable <= {52'b0, {12{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 6 : begin - case (MEM_RATIO) - 8 : avl_byteenable <= {8'b0, {56{1'b1}}}; - 16 : avl_byteenable <= {36'b0, {28{1'b1}}}; - 32 : avl_byteenable <= {50'b0, {14{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 7 : begin - case (MEM_RATIO) - 16 : avl_byteenable <= {32'b0, {32{1'b1}}}; - 32 : avl_byteenable <= {48'b0, {16{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 8 : begin - case (MEM_RATIO) - 16 : avl_byteenable <= {28'b0, {36{1'b1}}}; - 32 : avl_byteenable <= {46'b0, {18{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 9 : begin - case (MEM_RATIO) - 16 : avl_byteenable <= {24'b0, {40{1'b1}}}; - 32 : avl_byteenable <= {44'b0, {20{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 10 : begin - case (MEM_RATIO) - 16 : avl_byteenable <= {20'b0, {44{1'b1}}}; - 32 : avl_byteenable <= {42'b0, {22{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 11 : begin - case (MEM_RATIO) - 16 : avl_byteenable <= {16'b0, {48{1'b1}}}; - 32 : avl_byteenable <= {40'b0, {24{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 12 : begin - case (MEM_RATIO) - 16 : avl_byteenable <= {12'b0, {52{1'b1}}}; - 32 : avl_byteenable <= {38'b0, {26{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 13 : begin - case (MEM_RATIO) - 16 : avl_byteenable <= {8'b0, {56{1'b1}}}; - 32 : avl_byteenable <= {36'b0, {28{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 14 : begin - case (MEM_RATIO) - 16 : avl_byteenable <= {4'b0, {60{1'b1}}}; - 32 : avl_byteenable <= {34'b0, {30{1'b1}}}; - default : avl_byteenable <= {64{1'b1}}; - endcase - end - 15 : begin - case (MEM_RATIO) - 32 : avl_byteenable <= {32'b0, {32{1'b1}}}; - default: avl_byteenable <= {64{1'b1}}; - endcase - end - 16 : begin - avl_byteenable <= {30'b0, {34{1'b1}}}; - end - 17 : begin - avl_byteenable <= {28'b0, {36{1'b1}}}; - end - 18 : begin - avl_byteenable <= {26'b0, {38{1'b1}}}; - end - 19 : begin - avl_byteenable <= {24'b0, {40{1'b1}}}; - end - 20 : begin - avl_byteenable <= {22'b0, {42{1'b1}}}; - end - 21 : begin - avl_byteenable <= {20'b0, {44{1'b1}}}; - end - 22 : begin - avl_byteenable <= {18'b0, {46{1'b1}}}; - end - 23 : begin - avl_byteenable <= {16'b0, {48{1'b1}}}; - end - 24 : begin - avl_byteenable <= {14'b0, {50{1'b1}}}; - end - 25 : begin - avl_byteenable <= {12'b0, {52{1'b1}}}; - end - 26 : begin - avl_byteenable <= {10'b0, {54{1'b1}}}; - end - 27 : begin - avl_byteenable <= {8'b0, {56{1'b1}}}; - end - 28 : begin - avl_byteenable <= {6'b0, {58{1'b1}}}; - end - 29 : begin - avl_byteenable <= {4'b0, {60{1'b1}}}; - end - 30 : begin - avl_byteenable <= {2'b0, {62{1'b1}}}; - end - default : avl_byteenable <= {64{1'b1}}; - endcase - end else begin - avl_byteenable <= {64{1'b1}}; - end - end - -endmodule diff --git a/library/altera/avl_dacfifo/avl_dacfifo_byteenable_decoder.v b/library/altera/avl_dacfifo/avl_dacfifo_byteenable_decoder.v deleted file mode 100644 index 3926532fd..000000000 --- a/library/altera/avl_dacfifo/avl_dacfifo_byteenable_decoder.v +++ /dev/null @@ -1,274 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module avl_dacfifo_byteenable_decoder #( - - parameter MEM_RATIO = 8, - parameter LAST_BEATS_WIDTH = 3) ( - - input avl_clk, - - input [ 63:0] avl_byteenable, - input avl_enable, - - output reg [LAST_BEATS_WIDTH-1:0] avl_last_beats -); - - always @(posedge avl_clk) begin - if (avl_enable == 1'b1) begin - case (avl_byteenable) - 64'b0000000000000000000000000000000000000000000000000000000000000011: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 0; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000000000000000000001111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 1; - 16 : avl_last_beats <= 0; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000000000000000000111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 2; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000000000000000011111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 3; - 16 : avl_last_beats <= 1; - 8 : avl_last_beats <= 0; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000000000000001111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 4; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000000000000111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 5; - 16 : avl_last_beats <= 2; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000000000011111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 6; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000000001111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 7; - 16 : avl_last_beats <= 3; - 8 : avl_last_beats <= 1; - 4 : avl_last_beats <= 0; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000000111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 8; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000000011111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 9; - 16 : avl_last_beats <= 4; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000001111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 10; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000000111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 11; - 16 : avl_last_beats <= 5; - 8 : avl_last_beats <= 2; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000000011111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 12; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000001111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 13; - 16 : avl_last_beats <= 6; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000000111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 14; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000000011111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 15; - 16 : avl_last_beats <= 7; - 8 : avl_last_beats <= 3; - 4 : avl_last_beats <= 1; - 2 : avl_last_beats <= 0; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000001111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 16; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000000111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 17; - 16 : avl_last_beats <= 8; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000000011111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 18; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000001111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 19; - 16 : avl_last_beats <= 9; - 8 : avl_last_beats <= 4; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000000111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 20; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000000011111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 21; - 16 : avl_last_beats <= 10; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000001111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 22; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000000111111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 23; - 16 : avl_last_beats <= 11; - 8 : avl_last_beats <= 5; - 4 : avl_last_beats <= 2; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000000011111111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 24; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000001111111111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 25; - 16 : avl_last_beats <= 12; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000000111111111111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 26; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000000011111111111111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 27; - 16 : avl_last_beats <= 13; - 8 : avl_last_beats <= 6; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000001111111111111111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 28; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0000111111111111111111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 29; - 16 : avl_last_beats <= 14; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - 64'b0011111111111111111111111111111111111111111111111111111111111111: begin - case (MEM_RATIO) - 32 : avl_last_beats <= 30; - default : avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end - default: avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - endcase - end else begin - avl_last_beats <= {LAST_BEATS_WIDTH{1'b1}}; - end - end - -endmodule - diff --git a/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl b/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl index 6c3c3473b..ef8f8d07c 100644 --- a/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl +++ b/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl @@ -10,8 +10,6 @@ ad_ip_files avl_dacfifo [list\ $ad_hdl_dir/library/common/ad_g2b.v \ $ad_hdl_dir/library/common/ad_mem.v \ util_dacfifo_bypass.v \ - avl_dacfifo_byteenable_coder.v \ - avl_dacfifo_byteenable_decoder.v \ avl_dacfifo_wr.v \ avl_dacfifo_rd.v \ avl_dacfifo.v \