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scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface

main
Istvan Csomortani 2018-08-14 14:53:45 +01:00 committed by István Csomortáni
parent 04ce10a570
commit 0f7a3b953a
25 changed files with 156 additions and 149 deletions
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4
library/axi_ad9122/axi_ad9122_hw.tcl
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@ -76,7 +76,7 @@ add_interface_port device_if dac_sync_in dac_sync_in Input 1
# dma interface
ad_alt_intf clock dac_div_clk Output 1
ad_interface clock dac_div_clk Output 1
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_valid_0 valid Output 1
@ -92,7 +92,7 @@ add_interface_port dac_ch_1 dac_ddata_1 data Input 64
set_interface_property dac_ch_1 associatedClock if_dac_div_clk
set_interface_property dac_ch_1 associatedReset none
ad_alt_intf signal dac_dunf input 1 unf
ad_interface signal dac_dunf input 1 unf
# SERDES instances and configurations

6
library/axi_ad9144/axi_ad9144_hw.tcl
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@ -71,7 +71,7 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
# transceiver interface
ad_alt_intf clock tx_clk input 1
ad_interface clock tx_clk input 1
add_interface if_tx_data avalon_streaming source
add_interface_port if_tx_data tx_data data output 128*(QUAD_OR_DUAL_N+1)
@ -82,7 +82,7 @@ set_interface_property if_tx_data dataBitsPerSymbol 128
# dma interface
ad_alt_intf clock dac_clk output 1
ad_interface clock dac_clk output 1
for {set i 0} {$i < 4} {incr i} {
add_interface dac_ch_${i} conduit end
@ -94,7 +94,7 @@ for {set i 0} {$i < 4} {incr i} {
set_interface_property dac_ch_${i} associatedReset none
}
ad_alt_intf signal dac_dunf input 1 unf
ad_interface signal dac_dunf input 1 unf
proc p_axi_ad9144 {} {

6
library/axi_ad9152/axi_ad9152_hw.tcl
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@ -64,7 +64,7 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
# transceiver interface
ad_alt_intf clock tx_clk input 1
ad_interface clock tx_clk input 1
add_interface if_tx_data avalon_streaming source
add_interface_port if_tx_data tx_data data output 128
@ -75,7 +75,7 @@ set_interface_property if_tx_data dataBitsPerSymbol 128
# dma interface
ad_alt_intf clock dac_clk output 1
ad_interface clock dac_clk output 1
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_enable_0 enable Output 1
@ -93,5 +93,5 @@ add_interface_port dac_ch_1 dac_ddata_1 data Input 64
set_interface_property dac_ch_1 associatedClock if_tx_clk
set_interface_property dac_ch_1 associatedReset none
ad_alt_intf signal dac_dunf input 1 unf
ad_interface signal dac_dunf input 1 unf

8
library/axi_ad9250/axi_ad9250_hw.tcl
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@ -59,8 +59,8 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# transceiver interface
ad_alt_intf clock rx_clk input 1
ad_alt_intf signal rx_sof input 4 export
ad_interface clock rx_clk input 1
ad_interface signal rx_sof input 4 export
add_interface if_rx_data avalon_streaming sink
add_interface_port if_rx_data rx_data data input 64
@ -71,7 +71,7 @@ set_interface_property if_rx_data dataBitsPerSymbol 64
# dma interface
ad_alt_intf clock adc_clk output 1
ad_interface clock adc_clk output 1
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_a enable Output 1
@ -89,5 +89,5 @@ add_interface_port adc_ch_1 adc_data_b data Output 32
set_interface_property adc_ch_1 associatedClock if_rx_clk
set_interface_property adc_ch_1 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_interface signal adc_dovf input 1 ovf

36
library/axi_ad9361/axi_ad9361_hw.tcl
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@ -77,16 +77,16 @@ adi_add_auto_fpga_spec_params
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
ad_alt_intf signal dac_sync_in input 1
ad_alt_intf signal dac_sync_out output 1
ad_alt_intf signal tdd_sync input 1
ad_alt_intf signal tdd_sync_cntr output 1
ad_interface signal dac_sync_in input 1
ad_interface signal dac_sync_out output 1
ad_interface signal tdd_sync input 1
ad_interface signal tdd_sync_cntr output 1
ad_alt_intf clock delay_clk input 1
ad_alt_intf clock l_clk output 1
ad_alt_intf clock clk input 1
ad_interface clock delay_clk input 1
ad_interface clock l_clk output 1
ad_interface clock clk input 1
ad_alt_intf reset rst output 1 if_clk
ad_interface reset rst output 1 if_clk
set_interface_property if_rst associatedResetSinks s_axi_reset
add_interface adc_ch_0 conduit end
@ -121,8 +121,8 @@ add_interface_port adc_ch_3 adc_data_q1 data Output 16
set_interface_property adc_ch_3 associatedClock if_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_r1_mode output 1 r1_mode
ad_interface signal adc_dovf input 1 ovf
ad_interface signal adc_r1_mode output 1 r1_mode
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_enable_i0 enable Output 1
@ -156,15 +156,15 @@ add_interface_port dac_ch_3 dac_data_q1 data Input 16
set_interface_property dac_ch_3 associatedClock if_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dunf input 1 unf
ad_alt_intf signal dac_r1_mode output 1 r1_mode
ad_interface signal dac_dunf input 1 unf
ad_interface signal dac_r1_mode output 1 r1_mode
ad_alt_intf signal up_enable input 1
ad_alt_intf signal up_txnrx input 1
ad_alt_intf signal up_dac_gpio_in input 32
ad_alt_intf signal up_dac_gpio_out output 32
ad_alt_intf signal up_adc_gpio_in input 32
ad_alt_intf signal up_adc_gpio_out output 32
ad_interface signal up_enable input 1
ad_interface signal up_txnrx input 1
ad_interface signal up_dac_gpio_in input 32
ad_interface signal up_dac_gpio_out output 32
ad_interface signal up_adc_gpio_in input 32
ad_interface signal up_adc_gpio_out output 32
# updates

20
library/axi_ad9371/axi_ad9371_hw.tcl
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@ -80,8 +80,8 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# transceiver interface
ad_alt_intf clock adc_clk input 1
ad_alt_intf signal adc_rx_sof input 4 export
ad_interface clock adc_clk input 1
ad_interface signal adc_rx_sof input 4 export
add_interface if_adc_rx_data avalon_streaming sink
add_interface_port if_adc_rx_data adc_rx_data data input 64
add_interface_port if_adc_rx_data adc_rx_valid valid input 1
@ -89,8 +89,8 @@ add_interface_port if_adc_rx_data adc_rx_ready ready output 1
set_interface_property if_adc_rx_data associatedClock if_adc_clk
set_interface_property if_adc_rx_data dataBitsPerSymbol 64
ad_alt_intf clock adc_os_clk input 1
ad_alt_intf signal adc_rx_os_sof input 4 export
ad_interface clock adc_os_clk input 1
ad_interface signal adc_rx_os_sof input 4 export
add_interface if_adc_rx_os_data avalon_streaming sink
add_interface_port if_adc_rx_os_data adc_rx_os_data data input 64
add_interface_port if_adc_rx_os_data adc_rx_os_valid valid input 1
@ -98,7 +98,7 @@ add_interface_port if_adc_rx_os_data adc_rx_os_ready ready output 1
set_interface_property if_adc_rx_os_data associatedClock if_adc_os_clk
set_interface_property if_adc_rx_os_data dataBitsPerSymbol 64
ad_alt_intf clock dac_clk input 1
ad_interface clock dac_clk input 1
add_interface if_dac_tx_data avalon_streaming source
add_interface_port if_dac_tx_data dac_tx_data data output 128
add_interface_port if_dac_tx_data dac_tx_valid valid output 1
@ -108,8 +108,8 @@ set_interface_property if_dac_tx_data dataBitsPerSymbol 128
# master/slave
ad_alt_intf signal dac_sync_in input 1
ad_alt_intf signal dac_sync_out output 1
ad_interface signal dac_sync_in input 1
ad_interface signal dac_sync_out output 1
# adc-channel interface
@ -145,7 +145,7 @@ add_interface_port adc_ch_3 adc_data_q1 data Output 16
set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_interface signal adc_dovf input 1 ovf
# adc-os-channel interface
@ -165,7 +165,7 @@ add_interface_port adc_os_ch_1 adc_os_data_q0 data Output 32
set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk
set_interface_property adc_os_ch_1 associatedReset none
ad_alt_intf signal adc_os_dovf input 1 ovf
ad_interface signal adc_os_dovf input 1 ovf
# dac-channel interface
@ -201,5 +201,5 @@ add_interface_port dac_ch_3 dac_data_q1 data Input 32
set_interface_property dac_ch_3 associatedClock if_dac_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dunf input 1 unf
ad_interface signal dac_dunf input 1 unf

10
library/axi_ad9671/axi_ad9671_hw.tcl
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@ -61,8 +61,8 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# transceiver interface
ad_alt_intf clock rx_clk input 1
ad_alt_intf signal rx_sof input 4 export
ad_interface clock rx_clk input 1
ad_interface signal rx_sof input 4 export
add_interface if_rx_data avalon_streaming sink
add_interface_port if_rx_data rx_data data input 64*QUAD_OR_DUAL_N+64
@ -80,8 +80,8 @@ add_interface_port if_sync adc_raddr_out raddr_out Output 4
# dma interface
ad_alt_intf clock adc_clk output 1
ad_alt_intf reset adc_rst output 1 if_adc_clk
ad_interface clock adc_clk output 1
ad_interface reset adc_rst output 1 if_adc_clk
add_interface adc_ch conduit end
add_interface_port adc_ch adc_enable enable Output 8
@ -91,5 +91,5 @@ add_interface_port adc_ch adc_data data Output 128
set_interface_property adc_ch associatedClock if_rx_clk
set_interface_property adc_ch associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_interface signal adc_dovf input 1 ovf

8
library/axi_ad9680/axi_ad9680_hw.tcl
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@ -59,8 +59,8 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# transceiver interface
ad_alt_intf clock rx_clk input 1
ad_alt_intf signal rx_sof input 4 export
ad_interface clock rx_clk input 1
ad_interface signal rx_sof input 4 export
add_interface if_rx_data avalon_streaming sink
add_interface_port if_rx_data rx_data data input 128
@ -71,7 +71,7 @@ set_interface_property if_rx_data dataBitsPerSymbol 128
# dma interface
ad_alt_intf clock adc_clk output 1
ad_interface clock adc_clk output 1
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_0 enable Output 1
@ -89,5 +89,5 @@ add_interface_port adc_ch_1 adc_data_1 data Output 64
set_interface_property adc_ch_1 associatedClock if_rx_clk
set_interface_property adc_ch_1 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_interface signal adc_dovf input 1 ovf

6
library/axi_ad9684/axi_ad9684_hw.tcl
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@ -75,8 +75,8 @@ add_interface_port device_if adc_data_in_n adc_data_in_n Input 14
# dma interface
ad_alt_intf clock adc_clk output 1
ad_alt_intf reset adc_rst output 1 if_adc_clk
ad_interface clock adc_clk output 1
ad_interface reset adc_rst output 1 if_adc_clk
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_valid_0 valid Output 1
@ -92,7 +92,7 @@ add_interface_port adc_ch_1 adc_data_1 data Output 32
set_interface_property adc_ch_1 associatedClock if_adc_clk
set_interface_property adc_ch_1 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_interface signal adc_dovf input 1 ovf
# SERDES instances and configurations

20
library/axi_adrv9009/axi_adrv9009_hw.tcl
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@ -143,8 +143,8 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# transceiver interface
ad_alt_intf clock adc_clk input 1
ad_alt_intf signal adc_rx_sof input 4 export
ad_interface clock adc_clk input 1
ad_interface signal adc_rx_sof input 4 export
add_interface if_adc_rx_data avalon_streaming sink
add_interface_port if_adc_rx_data adc_rx_data data input 64
add_interface_port if_adc_rx_data adc_rx_valid valid input 1
@ -152,8 +152,8 @@ add_interface_port if_adc_rx_data adc_rx_ready ready output 1
set_interface_property if_adc_rx_data associatedClock if_adc_clk
set_interface_property if_adc_rx_data dataBitsPerSymbol 64
ad_alt_intf clock adc_os_clk input 1
ad_alt_intf signal adc_rx_os_sof input 4 export
ad_interface clock adc_os_clk input 1
ad_interface signal adc_rx_os_sof input 4 export
add_interface if_adc_rx_os_data avalon_streaming sink
add_interface_port if_adc_rx_os_data adc_rx_os_data data input 64
add_interface_port if_adc_rx_os_data adc_rx_os_valid valid input 1
@ -161,7 +161,7 @@ add_interface_port if_adc_rx_os_data adc_rx_os_ready ready output 1
set_interface_property if_adc_rx_os_data associatedClock if_adc_os_clk
set_interface_property if_adc_rx_os_data dataBitsPerSymbol 64
ad_alt_intf clock dac_clk input 1
ad_interface clock dac_clk input 1
add_interface if_dac_tx_data avalon_streaming source
add_interface_port if_dac_tx_data dac_tx_data data output 128
add_interface_port if_dac_tx_data dac_tx_valid valid output 1
@ -171,8 +171,8 @@ set_interface_property if_dac_tx_data dataBitsPerSymbol 128
# master/slave
ad_alt_intf signal dac_sync_in input 1
ad_alt_intf signal dac_sync_out output 1
ad_interface signal dac_sync_in input 1
ad_interface signal dac_sync_out output 1
# adc-channel interface
@ -208,7 +208,7 @@ add_interface_port adc_ch_3 adc_data_q1 data Output 16
set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_interface signal adc_dovf input 1 ovf
# adc-os-channel interface
@ -244,7 +244,7 @@ add_interface_port adc_os_ch_3 adc_os_data_q1 data Output 32
set_interface_property adc_os_ch_3 associatedClock if_adc_os_clk
set_interface_property adc_os_ch_3 associatedReset none
ad_alt_intf signal adc_os_dovf input 1 ovf
ad_interface signal adc_os_dovf input 1 ovf
# dac-channel interface
@ -280,5 +280,5 @@ add_interface_port dac_ch_3 dac_data_q1 data Input 32
set_interface_property dac_ch_3 associatedClock if_dac_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dunf input 1 unf
ad_interface signal dac_dunf input 1 unf

32
library/axi_dmac/axi_dmac_hw.tcl
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@ -289,8 +289,8 @@ add_interface_port m_src_axi_reset m_src_axi_aresetn reset_n Input 1
# axis destination/source
ad_alt_intf clock m_axis_aclk input 1 clk
ad_alt_intf signal m_axis_xfer_req output 1 xfer_req
ad_interface clock m_axis_aclk input 1 clk
ad_interface signal m_axis_xfer_req output 1 xfer_req
add_interface m_axis axi4stream start
set_interface_property m_axis associatedClock if_m_axis_aclk
@ -305,8 +305,8 @@ add_interface_port m_axis m_axis_dest tdest Output DMA_AXIS_DEST_W
add_interface_port m_axis m_axis_strb tstrb Output DMA_DATA_WIDTH_DEST/8
add_interface_port m_axis m_axis_keep tkeep Output DMA_DATA_WIDTH_DEST/8
ad_alt_intf clock s_axis_aclk input 1 clk
ad_alt_intf signal s_axis_xfer_req output 1 xfer_req
ad_interface clock s_axis_aclk input 1 clk
ad_interface signal s_axis_xfer_req output 1 xfer_req
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock if_s_axis_aclk
@ -323,19 +323,19 @@ add_interface_port s_axis s_axis_keep tkeep Input DMA_DATA_WIDTH_SRC/8
# fifo destination/source
ad_alt_intf clock fifo_rd_clk input 1 clk
ad_alt_intf signal fifo_rd_en input 1 valid
ad_alt_intf signal fifo_rd_valid output 1 valid
ad_alt_intf signal fifo_rd_dout output DMA_DATA_WIDTH_DEST data
ad_alt_intf signal fifo_rd_underflow output 1 unf
ad_alt_intf signal fifo_rd_xfer_req output 1 xfer_req
ad_interface clock fifo_rd_clk input 1 clk
ad_interface signal fifo_rd_en input 1 valid
ad_interface signal fifo_rd_valid output 1 valid
ad_interface signal fifo_rd_dout output DMA_DATA_WIDTH_DEST data
ad_interface signal fifo_rd_underflow output 1 unf
ad_interface signal fifo_rd_xfer_req output 1 xfer_req
ad_alt_intf clock fifo_wr_clk input 1 clk
ad_alt_intf signal fifo_wr_en input 1 valid
ad_alt_intf signal fifo_wr_din input DMA_DATA_WIDTH_SRC data
ad_alt_intf signal fifo_wr_overflow output 1 ovf
ad_alt_intf signal fifo_wr_sync input 1 sync
ad_alt_intf signal fifo_wr_xfer_req output 1 xfer_req
ad_interface clock fifo_wr_clk input 1 clk
ad_interface signal fifo_wr_en input 1 valid
ad_interface signal fifo_wr_din input DMA_DATA_WIDTH_SRC data
ad_interface signal fifo_wr_overflow output 1 ovf
ad_interface signal fifo_wr_sync input 1 sync
ad_interface signal fifo_wr_xfer_req output 1 xfer_req
proc add_axi_master_interface {axi_type port suffix} {
add_interface $port $axi_type start

15
library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
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@ -101,7 +101,14 @@ add_interface_port hdmi_if hdmi_36_data h36_data Output 36
add_interface vdma_clock clock end
add_interface_port vdma_clock vdma_clk clk Input 1
ad_alt_intf signal vdma_ready output 1 ready
ad_alt_intf signal vdma_valid input 1 valid
ad_alt_intf signal vdma_data input 64 data
ad_alt_intf signal vdma_end_of_frame input 1 last
add_interface vdma_if avalon_streaming end
set_interface_property vdma_if associatedClock vdma_clock
add_interface_port vdma_if vdma_valid valid Input 1
add_interface_port vdma_if vdma_data data Input 64
add_interface_port vdma_if vdma_ready ready Output 1
# frame sync
ad_interface signal vdma_fs output 1
ad_interface signal vdma_fs_ret input 1

20
library/intel/avl_dacfifo/avl_dacfifo_hw.tcl
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@ -30,9 +30,9 @@ ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000
# interfaces
ad_alt_intf clock dma_clk input 1 clk
ad_alt_intf reset dma_rst input 1 if_dma_clk
ad_alt_intf signal dma_xfer_req input 1 xfer_req
ad_interface clock dma_clk input 1 clk
ad_interface reset dma_rst input 1 if_dma_clk
ad_interface signal dma_xfer_req input 1 xfer_req
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock if_dma_clk
@ -42,14 +42,14 @@ add_interface_port s_axis dma_xfer_last tlast Input 1
add_interface_port s_axis dma_ready tready Output 1
add_interface_port s_axis dma_data tdata Input DMA_DATA_WIDTH
ad_alt_intf clock dac_clk input 1 clk
ad_alt_intf reset dac_rst input 1 if_dac_clk
ad_alt_intf signal dac_valid input 1 valid
ad_alt_intf signal dac_data output DAC_DATA_WIDTH data
ad_alt_intf signal dac_dunf output 1 unf
ad_alt_intf signal dac_xfer_out output 1 xfer_out
ad_interface clock dac_clk input 1 clk
ad_interface reset dac_rst input 1 if_dac_clk
ad_interface signal dac_valid input 1 valid
ad_interface signal dac_data output DAC_DATA_WIDTH data
ad_interface signal dac_dunf output 1 unf
ad_interface signal dac_xfer_out output 1 xfer_out
ad_alt_intf signal bypass input 1 bypass
ad_interface signal bypass input 1 bypass
add_interface avl_clock clock end
add_interface_port avl_clock avl_clk clk input 1

2
library/intel/axi_adxcvr/axi_adxcvr_hw.tcl
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@ -56,7 +56,7 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
# xcvr interface
ad_alt_intf reset up_rst output 1 s_axi_clock
ad_interface reset up_rst output 1 s_axi_clock
set_interface_property if_up_rst associatedResetSinks s_axi_reset
add_interface core_pll_locked conduit end

8
library/intel/util_clkdiv/util_clkdiv_hw.tcl
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@ -18,8 +18,8 @@ add_fileset_file util_clkdiv.v VERILOG PATH util_clkdiv.v TOP_LEVEL_FILE
# defaults
ad_alt_intf clock clk input 1
ad_alt_intf reset reset input 1 if_clk
ad_alt_intf clock clk_out output 1
ad_alt_intf reset reset_out output 1 if_clk_out
ad_interface clock clk input 1
ad_interface reset reset input 1 if_clk
ad_interface clock clk_out output 1
ad_interface reset reset_out output 1 if_clk_out

4
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
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@ -162,7 +162,7 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
add_interface link_clk clock end
add_interface_port link_clk link_clk clk Input 1
ad_alt_intf signal link_sof input 4 export
ad_interface signal link_sof input 4 export
# We don't expect too large values for a and b, trivial implementation will do
proc gcd {a b} {
@ -264,5 +264,5 @@ proc p_ad_ip_jesd204_tpl_adc_elab {} {
set_interface_property adc_ch_$i associatedClock link_clk
}
ad_alt_intf signal adc_dovf input 1 ovf
ad_interface signal adc_dovf input 1 ovf
}

2
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
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@ -504,5 +504,5 @@ proc p_ad_ip_jesd204_tpl_dac_elab {} {
set_interface_property dac_ch_$i associatedClock link_clk
}
ad_alt_intf signal dac_dunf input 1 unf
ad_interface signal dac_dunf input 1 unf
}

2
library/scripts/adi_ip_intel.tcl
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@ -11,7 +11,7 @@
# \param[arg_2] - Optional argument to define the associated reset sink for a
# reset interface
#
proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
proc ad_interface {type name dir width {arg_1 ""} {arg_2 ""}} {
if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "input"])} {
add_interface if_${name} clock sink

16
library/util_adcfifo/util_adcfifo_hw.tcl
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@ -46,15 +46,15 @@ proc p_util_adcfifo {} {
# interfaces
ad_alt_intf clock adc_clk input 1 adc_clk
ad_alt_intf reset adc_rst input 1 if_adc_clk
ad_alt_intf signal adc_wr input 1 valid
ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data
ad_alt_intf signal adc_wovf output 1 ovf
ad_interface clock adc_clk input 1 adc_clk
ad_interface reset adc_rst input 1 if_adc_clk
ad_interface signal adc_wr input 1 valid
ad_interface signal adc_wdata input ADC_DATA_WIDTH data
ad_interface signal adc_wovf output 1 ovf
ad_alt_intf clock dma_clk input 1 clk
ad_alt_intf signal dma_xfer_req input 1 xfer_req
ad_alt_intf signal dma_xfer_status output 4 xfer_status
ad_interface clock dma_clk input 1 clk
ad_interface signal dma_xfer_req input 1 xfer_req
ad_interface signal dma_xfer_status output 4 xfer_status
add_interface m_axis axi4stream start
set_interface_property m_axis associatedClock if_dma_clk

18
library/util_bsplit/util_bsplit_hw.tcl
View File

@ -36,8 +36,8 @@ set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
# avalon streaming
ad_alt_intf signal data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH
ad_alt_intf signal split_data_0 output CHANNEL_DATA_WIDTH data
ad_interface signal data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH
ad_interface signal split_data_0 output CHANNEL_DATA_WIDTH data
proc p_util_bsplit {} {
@ -45,25 +45,25 @@ proc p_util_bsplit {} {
set p_ch_dw [get_parameter_value "CHANNEL_DATA_WIDTH"]
if {[get_parameter_value NUM_OF_CHANNELS] > 1} {
ad_alt_intf signal split_data_1 output CHANNEL_DATA_WIDTH data
ad_interface signal split_data_1 output CHANNEL_DATA_WIDTH data
}
if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
ad_alt_intf signal split_data_2 output CHANNEL_DATA_WIDTH data
ad_interface signal split_data_2 output CHANNEL_DATA_WIDTH data
}
if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
ad_alt_intf signal split_data_3 output CHANNEL_DATA_WIDTH data
ad_interface signal split_data_3 output CHANNEL_DATA_WIDTH data
}
if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
ad_alt_intf signal split_data_4 output CHANNEL_DATA_WIDTH data
ad_interface signal split_data_4 output CHANNEL_DATA_WIDTH data
}
if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
ad_alt_intf signal split_data_5 output CHANNEL_DATA_WIDTH data
ad_interface signal split_data_5 output CHANNEL_DATA_WIDTH data
}
if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
ad_alt_intf signal split_data_6 output CHANNEL_DATA_WIDTH data
ad_interface signal split_data_6 output CHANNEL_DATA_WIDTH data
}
if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
ad_alt_intf signal split_data_7 output CHANNEL_DATA_WIDTH data
ad_interface signal split_data_7 output CHANNEL_DATA_WIDTH data
}
}

20
library/util_dacfifo/util_dacfifo_hw.tcl
View File

@ -21,9 +21,9 @@ ad_ip_parameter DATA_WIDTH INTEGER 128
# interfaces
ad_alt_intf clock dma_clk input 1 clk
ad_alt_intf reset dma_rst input 1 if_dma_clk
ad_alt_intf signal dma_xfer_req input 1 xfer_req
ad_interface clock dma_clk input 1 clk
ad_interface reset dma_rst input 1 if_dma_clk
ad_interface signal dma_xfer_req input 1 xfer_req
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock if_dma_clk
@ -33,12 +33,12 @@ add_interface_port s_axis dma_xfer_last tlast Input 1
add_interface_port s_axis dma_ready tready Output 1
add_interface_port s_axis dma_data tdata Input DATA_WIDTH
ad_alt_intf clock dac_clk input 1
ad_alt_intf reset dac_rst input 1 if_dac_clk
ad_alt_intf signal dac_valid input 1 valid
ad_alt_intf signal dac_data output DATA_WIDTH data
ad_alt_intf signal dac_xfer_out output 1 xfer_req
ad_alt_intf signal dac_dunf output 1 unf
ad_interface clock dac_clk input 1
ad_interface reset dac_rst input 1 if_dac_clk
ad_interface signal dac_valid input 1 valid
ad_interface signal dac_data output DATA_WIDTH data
ad_interface signal dac_xfer_out output 1 xfer_req
ad_interface signal dac_dunf output 1 unf
ad_alt_intf signal bypass input 1 bypass
ad_interface signal bypass input 1 bypass

10
library/util_pack/util_cpack2/util_cpack2_hw.tcl
View File

@ -64,12 +64,12 @@ proc util_cpack_elab {} {
add_interface_port reset reset reset Input 1
set_interface_property reset associatedClock clk
ad_alt_intf signal packed_fifo_wr_en output 1 valid
ad_alt_intf signal packed_fifo_wr_sync output 1 sync
ad_alt_intf signal packed_fifo_wr_data output $total_data_width data
ad_alt_intf signal packed_fifo_wr_overflow input 1 ovf
ad_interface signal packed_fifo_wr_en output 1 valid
ad_interface signal packed_fifo_wr_sync output 1 sync
ad_interface signal packed_fifo_wr_data output $total_data_width data
ad_interface signal packed_fifo_wr_overflow input 1 ovf
ad_alt_intf signal fifo_wr_overflow output 1 ovf
ad_interface signal fifo_wr_overflow output 1 ovf
for {set n 0} {$n < $num_channels} {incr n} {
add_interface adc_ch_${n} conduit end

8
library/util_pack/util_upack2/util_upack2_hw.tcl
View File

@ -81,17 +81,17 @@ proc util_upack_elab {} {
add_interface_port s_axis s_axis_ready tready Output 1
add_interface_port s_axis s_axis_data tdata Input $total_data_width
} else {
ad_alt_intf signal packed_fifo_rd_en output 1 valid
ad_interface signal packed_fifo_rd_en output 1 valid
set_port_property packed_fifo_rd_en fragment_list "s_axis_ready"
ad_alt_intf signal packed_fifo_rd_data input $total_data_width data
ad_interface signal packed_fifo_rd_data input $total_data_width data
set_port_property packed_fifo_rd_data fragment_list \
[format "s_axis_data(%d:0)" [expr $total_data_width - 1]]
ad_alt_intf signal s_axis_valid input 1 valid
ad_interface signal s_axis_valid input 1 valid
set_port_property s_axis_valid TERMINATION TRUE
set_port_property s_axis_valid TERMINATION_VALUE 1
}
ad_alt_intf signal fifo_rd_underflow output 1 unf
ad_interface signal fifo_rd_underflow output 1 unf
for {set n 0} {$n < $num_channels} {incr n} {
add_interface dac_ch_${n} conduit end

12
library/util_rfifo/util_rfifo_hw.tcl
View File

@ -19,10 +19,10 @@ ad_ip_parameter DIN_ADDRESS_WIDTH INTEGER 8
# defaults
ad_alt_intf clock din_clk input 1
ad_alt_intf reset-n din_rstn input 1 if_din_clk
ad_alt_intf clock dout_clk input 1
ad_alt_intf reset dout_rst input 1 if_dout_clk
ad_interface clock din_clk input 1
ad_interface reset-n din_rstn input 1 if_din_clk
ad_interface clock dout_clk input 1
ad_interface reset dout_rst input 1 if_dout_clk
add_interface din_0 conduit end
add_interface_port din_0 din_enable_0 enable Output 1
@ -40,8 +40,8 @@ add_interface_port dout_0 dout_data_0 data Output DOUT_DATA_WIDTH
set_interface_property dout_0 associatedClock if_dout_clk
set_interface_property dout_0 associatedReset none
ad_alt_intf signal din_unf input 1 unf
ad_alt_intf signal dout_unf output 1 unf
ad_interface signal din_unf input 1 unf
ad_interface signal dout_unf output 1 unf
proc util_rfifo_elab {} {

12
library/util_wfifo/util_wfifo_hw.tcl
View File

@ -51,11 +51,11 @@ set_parameter_property DIN_ADDRESS_WIDTH HDL_PARAMETER true
# defaults
ad_alt_intf clock din_clk input 1
ad_alt_intf reset din_rst input 1 if_din_clk
ad_interface clock din_clk input 1
ad_interface reset din_rst input 1 if_din_clk
ad_alt_intf clock dout_clk input 1
ad_alt_intf reset-n dout_rstn input 1 if_dout_clk
ad_interface clock dout_clk input 1
ad_interface reset-n dout_rstn input 1 if_dout_clk
add_interface din_0 conduit end
add_interface_port din_0 din_enable_0 enable Input 1
@ -73,8 +73,8 @@ add_interface_port dout_0 dout_data_0 data Output DOUT_DATA_WIDTH
set_interface_property dout_0 associatedClock if_dout_clk
set_interface_property dout_0 associatedReset none
ad_alt_intf signal din_ovf output 1 ovf
ad_alt_intf signal dout_ovf input 1 ovf
ad_interface signal din_ovf output 1 ovf
ad_interface signal dout_ovf input 1 ovf
proc p_util_wfifo {} {