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fmcjesdadc1: Fixed project 

- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
main
Adrian Costina 2016-02-19 14:09:57 +02:00
parent d94f157454
commit 0f37dd6424
5 changed files with 780 additions and 479 deletions
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942
projects/common/a5gt/a5gt_system_bd.qsys
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File diff suppressed because one or more lines are too long

90
projects/fmcjesdadc1/a5gt/system_bd.qsys
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@ -9,14 +9,6 @@
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element a5gt_base
{
datum _sortIndex
@ -73,6 +65,14 @@
type = "String";
}
}
element fmcjesdadc1.axi_jesd204_rx_avs
{
datum baseAddress
{
value = "262144";
type = "String";
}
}
element fmcjesdadc1.axi_jesd_xcvr_s_axi
{
datum baseAddress
@ -169,6 +169,22 @@
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />
@ -308,26 +324,26 @@
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a5gt_base</parameter>
</module>
<module name="fmcjesdadc1" kind="fmcjesdadc1_bd" version="1.0" enabled="1">
<parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /></address-map>]]></parameter>
<parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 29" />
<parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x10000000' end='0x20000000' /></address-map>]]></parameter>
<parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 29" />
<parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 28" />
<parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5gt_base_sys_ddr3_cntrl.avl' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 28" />
<parameter name="AUTO_CPU_CLK_CLOCK_DOMAIN" value="9" />
<parameter name="AUTO_CPU_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_CPU_CLK_RESET_DOMAIN" value="9" />
<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="9" />
<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="10" />
<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="9" />
<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="10" />
<parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="6" />
<parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="6" />
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="7" />
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="7" />
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcjesdadc1</parameter>
</module>
<module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
@ -335,7 +351,7 @@
</module>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="fmcjesdadc1.axi_dmac_0_m_axi"
end="a5gt_base.sys_mem_interconnect_s0">
<parameter name="arbitrationPriority" value="1" />
@ -344,7 +360,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="fmcjesdadc1.axi_dmac_1_m_axi"
end="a5gt_base.sys_mem_interconnect_s0">
<parameter name="arbitrationPriority" value="1" />
@ -353,7 +369,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_ad9250_0_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -362,7 +378,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_ad9250_1_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -371,7 +387,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_dmac_0_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -380,7 +396,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_dmac_1_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -389,7 +405,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a5gt_base.sys_cpu_interconnect_m0"
end="fmcjesdadc1.axi_jesd_xcvr_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -398,46 +414,46 @@
</connection>
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.clk"
end="a5gt_base.sys_clk" />
<connection
kind="clock"
version="15.0"
start="sys_clk.clk"
end="fmcjesdadc1.sys_clk" />
version="15.1"
start="a5gt_base.cpu_clk"
end="fmcjesdadc1.cpu_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="a5gt_base.mem_clk"
end="fmcjesdadc1.mem_clk" />
<connection
kind="interrupt"
version="15.0"
version="15.1"
start="a5gt_base.sys_intr"
end="fmcjesdadc1.axi_dmac_0_intr">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
version="15.0"
version="15.1"
start="a5gt_base.sys_intr"
end="fmcjesdadc1.axi_dmac_1_intr">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_clk.clk_reset"
end="a5gt_base.sys_rst" />
<connection
kind="reset"
version="15.0"
start="sys_clk.clk_reset"
end="fmcjesdadc1.sys_rst" />
version="15.1"
start="a5gt_base.cpu_rst"
end="fmcjesdadc1.cpu_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="a5gt_base.mem_rst"
end="fmcjesdadc1.mem_rst" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

7
projects/fmcjesdadc1/a5gt/system_constr.sdc
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@ -9,6 +9,9 @@ derive_clock_uncertainty
set_clock_groups -exclusive \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_clock_groups -asynchronous \
-group {ref_clk_250mhz} \
-group [get_clocks {i_system_bd|fmcjesdadc1|xcvr_rx_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]

4
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -5,8 +5,8 @@ source ../../scripts/adi_env.tcl
project_new fmcjesdadc1_a5gt -overwrite
source "../../common/a5gt/a5gt_system_assign.tcl"
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a5gt;../../../library/**/*"
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a5gt/;../../../library/**/*"
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"

216
projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys
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@ -9,14 +9,6 @@
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Arria V";
type = "String";
}
}
element axi_ad9250_0
{
datum _sortIndex
@ -434,11 +426,18 @@
internal="axi_dmac_1.s_axi"
type="axi4lite"
dir="end" />
<interface
name="axi_jesd204_rx_avs"
internal="xcvr_core.jesd204_rx_avs"
type="avalon"
dir="end" />
<interface
name="axi_jesd_xcvr_s_axi"
internal="axi_jesd_xcvr.s_axi"
type="axi4lite"
dir="end" />
<interface name="cpu_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
<interface name="cpu_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
<interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
<interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
<interface
@ -457,8 +456,6 @@
internal="axi_jesd_xcvr.if_rx_ext_sysref_out"
type="conduit"
dir="end" />
<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
<interface name="tx_ref_clk" internal="axi_jesd_xcvr.if_tx_ref_clk" />
<module name="axi_ad9250_0" kind="axi_ad9250" version="1.0" enabled="1">
<parameter name="DEVICE_TYPE" value="0" />
@ -474,14 +471,14 @@
<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
<parameter name="AXI_SLICE_DEST" value="0" />
<parameter name="AXI_SLICE_SRC" value="0" />
<parameter name="CYCLIC" value="1" />
<parameter name="DMA_2D_TRANSFER" value="1" />
<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
<parameter name="CYCLIC" value="0" />
<parameter name="DMA_2D_TRANSFER" value="0" />
<parameter name="DMA_DATA_WIDTH_DEST" value="256" />
<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="DMA_LENGTH_WIDTH" value="14" />
<parameter name="DMA_LENGTH_WIDTH" value="24" />
<parameter name="DMA_TYPE_DEST" value="0" />
<parameter name="DMA_TYPE_SRC" value="2" />
<parameter name="FIFO_SIZE" value="4" />
<parameter name="FIFO_SIZE" value="64" />
<parameter name="ID" value="0" />
<parameter name="SYNC_TRANSFER_START" value="0" />
</module>
@ -491,14 +488,14 @@
<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
<parameter name="AXI_SLICE_DEST" value="0" />
<parameter name="AXI_SLICE_SRC" value="0" />
<parameter name="CYCLIC" value="1" />
<parameter name="DMA_2D_TRANSFER" value="1" />
<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
<parameter name="CYCLIC" value="0" />
<parameter name="DMA_2D_TRANSFER" value="0" />
<parameter name="DMA_DATA_WIDTH_DEST" value="256" />
<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="DMA_LENGTH_WIDTH" value="14" />
<parameter name="DMA_LENGTH_WIDTH" value="24" />
<parameter name="DMA_TYPE_DEST" value="0" />
<parameter name="DMA_TYPE_SRC" value="2" />
<parameter name="FIFO_SIZE" value="4" />
<parameter name="FIFO_SIZE" value="64" />
<parameter name="ID" value="0" />
<parameter name="SYNC_TRANSFER_START" value="0" />
</module>
@ -508,37 +505,37 @@
<parameter name="RX_NUM_OF_LANES" value="4" />
<parameter name="TX_NUM_OF_LANES" value="4" />
</module>
<module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
<module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
<module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" />
<parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" />
</module>
<module
name="rx_ref_clk"
kind="altera_clock_bridge"
version="15.0"
version="15.1"
enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="250000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" />
<parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" />
</module>
<module name="util_bsplit" kind="util_bsplit" version="1.0" enabled="1">
@ -553,7 +550,7 @@
<parameter name="CHANNEL_DATA_WIDTH" value="32" />
<parameter name="NUM_OF_CHANNELS" value="2" />
</module>
<module name="xcvr_core" kind="altera_jesd204" version="15.0" enabled="1">
<module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
<parameter name="ADJCNT" value="0" />
<parameter name="ADJDIR" value="0" />
<parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
@ -566,6 +563,13 @@
<parameter name="DID" value="0" />
<parameter name="DLB_TEST" value="0" />
<parameter name="ECC_EN" value="0" />
<parameter name="ED_DEV_KIT" value="NONE" />
<parameter name="ED_FILESET_SIM" value="false" />
<parameter name="ED_FILESET_SYNTH" value="false" />
<parameter name="ED_GENERIC_5SERIES" value="No" />
<parameter name="ED_GENERIC_A10" value="No" />
<parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
<parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
<parameter name="GUI_CFG_F" value="4" />
<parameter name="GUI_EN_CFG_F" value="false" />
<parameter name="HD" value="0" />
@ -612,13 +616,13 @@
<module
name="xcvr_rst_cntrl"
kind="altera_xcvr_reset_control"
version="15.0"
version="15.1"
enabled="1">
<parameter name="CHANNELS" value="4" />
<parameter name="PLLS" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
<parameter name="RX_ENABLE" value="1" />
<parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="RX_PER_CHANNEL" value="1" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
<parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="SYS_CLK_IN_MHZ" value="100" />
@ -627,8 +631,9 @@
<parameter name="TX_PLL_ENABLE" value="0" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
<parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="T_RX_ANALOGRESET" value="80" />
<parameter name="T_RX_DIGITALRESET" value="8000" />
<parameter name="T_TX_ANALOGRESET" value="0" />
<parameter name="T_TX_DIGITALRESET" value="20" />
<parameter name="device_family" value="Arria V" />
<parameter name="gui_pll_cal_busy" value="0" />
@ -636,7 +641,7 @@
<parameter name="gui_split_interfaces" value="0" />
<parameter name="gui_tx_auto_reset" value="1" />
</module>
<module name="xcvr_rx_pll" kind="altera_pll" version="15.0" enabled="1">
<module name="xcvr_rx_pll" kind="altera_pll" version="15.1" enabled="1">
<parameter name="debug_print_output" value="false" />
<parameter name="debug_use_rbc_taf_method" value="false" />
<parameter name="device" value="5AGTFD7K3F40I3" />
@ -699,7 +704,7 @@
<parameter name="gui_cascade_outclk_index" value="0" />
<parameter name="gui_channel_spacing" value="0.0" />
<parameter name="gui_clk_bad" value="false" />
<parameter name="gui_device_speed_grade" value="1" />
<parameter name="gui_device_speed_grade" value="2" />
<parameter name="gui_divide_factor_c0" value="1" />
<parameter name="gui_divide_factor_c1" value="1" />
<parameter name="gui_divide_factor_c10" value="1" />
@ -841,114 +846,112 @@
</module>
<connection
kind="avalon_streaming"
version="15.0"
version="15.1"
start="xcvr_core.jesd204_rx_link"
end="axi_jesd_xcvr.if_rx_ip_avl" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="axi_ad9250_0.if_adc_clk"
end="util_cpack_0.if_adc_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="axi_ad9250_1.if_adc_clk"
end="util_cpack_1.if_adc_clk" />
<connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
<connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="axi_ad9250_1.if_adc_clk"
end="axi_dmac_1.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.1"
start="axi_ad9250_0.if_adc_clk"
end="axi_dmac_0.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.1"
start="sys_clk.out_clk"
end="xcvr_rst_cntrl.clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="xcvr_core.jesd204_rx_avs_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="mem_clk.out_clk"
end="axi_dmac_1.m_dest_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="mem_clk.out_clk"
end="axi_dmac_0.m_dest_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="rx_ref_clk.out_clk"
end="xcvr_core.pll_ref_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="rx_ref_clk.out_clk"
end="xcvr_rx_pll.refclk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9250_1.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_dmac_0.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_dmac_1.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_jesd_xcvr.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9250_0.s_axi_clock" />
<connection
kind="clock"
version="15.0"
start="xcvr_rx_pll.outclk0"
end="axi_dmac_1.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.0"
start="xcvr_rx_pll.outclk0"
end="axi_dmac_0.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="axi_ad9250_1.if_rx_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="axi_ad9250_0.if_rx_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="axi_jesd_xcvr.if_rx_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="axi_jesd_xcvr.if_tx_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="xcvr_core.rxlink_clk" />
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.dev_lane_aligned"
end="xcvr_core.alldev_lane_aligned">
<parameter name="endPort" value="" />
@ -959,7 +962,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9250_0.fifo_ch_0_in"
end="util_cpack_0.fifo_ch_0">
<parameter name="endPort" value="" />
@ -970,7 +973,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9250_1.fifo_ch_0_in"
end="util_cpack_1.fifo_ch_0">
<parameter name="endPort" value="" />
@ -981,7 +984,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9250_0.fifo_ch_1_in"
end="util_cpack_0.fifo_ch_1">
<parameter name="endPort" value="" />
@ -992,7 +995,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9250_1.fifo_ch_1_in"
end="util_cpack_1.fifo_ch_1">
<parameter name="endPort" value="" />
@ -1003,7 +1006,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_cpack_0.if_adc_data"
end="axi_dmac_0.if_fifo_wr_din">
<parameter name="endPort" value="" />
@ -1014,7 +1017,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_cpack_1.if_adc_data"
end="axi_dmac_1.if_fifo_wr_din">
<parameter name="endPort" value="" />
@ -1025,7 +1028,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_cpack_0.if_adc_sync"
end="axi_dmac_0.if_fifo_wr_sync">
<parameter name="endPort" value="" />
@ -1036,7 +1039,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_cpack_1.if_adc_sync"
end="axi_dmac_1.if_fifo_wr_sync">
<parameter name="endPort" value="" />
@ -1047,7 +1050,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_dmac_0.if_fifo_wr_en"
end="util_cpack_0.if_adc_valid">
<parameter name="endPort" value="" />
@ -1058,7 +1061,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_dmac_1.if_fifo_wr_en"
end="util_cpack_1.if_adc_valid">
<parameter name="endPort" value="" />
@ -1069,7 +1072,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_dmac_0.if_fifo_wr_overflow"
end="axi_ad9250_0.if_adc_dovf">
<parameter name="endPort" value="" />
@ -1080,7 +1083,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_dmac_1.if_fifo_wr_overflow"
end="axi_ad9250_1.if_adc_dovf">
<parameter name="endPort" value="" />
@ -1091,7 +1094,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_data"
end="util_bsplit.if_data">
<parameter name="endPort" value="" />
@ -1102,7 +1105,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9250_0.if_rx_data"
end="util_bsplit.if_split_data_0">
<parameter name="endPort" value="" />
@ -1113,7 +1116,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sync"
end="xcvr_core.dev_sync_n">
<parameter name="endPort" value="" />
@ -1124,7 +1127,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sysref"
end="xcvr_core.sysref">
<parameter name="endPort" value="" />
@ -1135,7 +1138,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_bsplit.if_split_data_1"
end="axi_ad9250_1.if_rx_data">
<parameter name="endPort" value="" />
@ -1146,7 +1149,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.rx_analogreset"
end="xcvr_core.rx_analogreset">
<parameter name="endPort" value="" />
@ -1157,7 +1160,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.rx_cal_busy"
end="xcvr_rst_cntrl.rx_cal_busy">
<parameter name="endPort" value="" />
@ -1168,7 +1171,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.rx_digitalreset"
end="xcvr_rst_cntrl.rx_digitalreset">
<parameter name="endPort" value="" />
@ -1179,7 +1182,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.rx_is_lockedtodata"
end="xcvr_core.rx_islockedtodata">
<parameter name="endPort" value="" />
@ -1190,7 +1193,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.rx_ready"
end="axi_jesd_xcvr.if_rx_ready">
<parameter name="endPort" value="" />
@ -1201,7 +1204,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.sof"
end="axi_jesd_xcvr.if_rx_ip_sof">
<parameter name="endPort" value="" />
@ -1212,72 +1215,67 @@
</connection>
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_ad9250_1.if_adc_rst"
end="util_cpack_1.if_adc_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_ad9250_0.if_adc_rst"
end="util_cpack_0.if_adc_rst" />
<connection
kind="reset"
version="15.0"
start="axi_jesd_xcvr.if_rst"
end="xcvr_rst_cntrl.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rst"
end="xcvr_rx_pll.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_rstn"
end="xcvr_core.rxlink_rst_n" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_core.jesd204_rx_avs_rst_n" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="axi_dmac_1.m_dest_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="axi_dmac_0.m_dest_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_rst_cntrl.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_ad9250_1.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_dmac_0.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_dmac_1.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_jesd_xcvr.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_ad9250_0.s_axi_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />