avl_dacfifo: Fix alv_mem_readen generation
parent
f456ebc6f0
commit
0f1e51ac98
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@ -76,6 +76,7 @@ module avl_dacfifo_wr #(
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wire [AVL_DATA_WIDTH-1:0] avl_mem_rdata_s;
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wire avl_mem_fetch_wr_address_s;
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wire avl_mem_readen_s;
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wire [AVL_MEM_ADDRESS_WIDTH :0] avl_mem_address_diff_s;
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wire avl_write_transfer_s;
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wire avl_last_transfer_req_s;
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wire avl_xfer_req_init_s;
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@ -96,7 +97,6 @@ module avl_dacfifo_wr #(
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_g;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address;
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reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address_next;
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reg avl_mem_fetch_wr_address;
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reg avl_mem_fetch_wr_address_m1;
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reg avl_mem_fetch_wr_address_m2;
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@ -250,21 +250,20 @@ module avl_dacfifo_wr #(
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avl_mem_fetch_wr_address_m2 <= 0;
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avl_mem_fetch_wr_address <= 0;
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avl_mem_wr_address <= 0;
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avl_mem_wr_address_next <= 0;
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end else begin
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avl_mem_fetch_wr_address_m1 <= dma_mem_read_control;
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avl_mem_fetch_wr_address_m2 <= avl_mem_fetch_wr_address_m1;
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avl_mem_fetch_wr_address <= avl_mem_fetch_wr_address_m2;
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if (avl_mem_fetch_wr_address_s == 1'b1) begin
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avl_mem_wr_address <= dma_mem_wr_address_d;
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avl_mem_wr_address_next <= avl_mem_wr_address + 1;
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end
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end
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end
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// Avalon write address and fifo read address generation
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assign avl_mem_readen_s = (avl_mem_rd_address == avl_mem_wr_address_next) ? 0 : avl_write_xfer_req;
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assign avl_mem_address_diff_s = {1'b1, avl_mem_wr_address} - avl_mem_rd_address;
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assign avl_mem_readen_s = (avl_mem_address_diff_s[AVL_MEM_ADDRESS_WIDTH-1:0] == 0) ? 0 : (avl_write_xfer_req & avl_ready);
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assign avl_write_transfer_s = avl_write & avl_ready;
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assign avl_write_transfer_done_s = avl_write_transfer & ~avl_write_transfer_s;
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