diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v new file mode 100755 index 000000000..ad88dcf76 --- /dev/null +++ b/library/axi_ad9250/axi_ad9250.v @@ -0,0 +1,375 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9250 ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // dma interface + + adc_clk, + adc_dwr, + adc_ddata, + adc_dsync, + adc_dovf, + adc_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready, + + // debug signals + + adc_mon_valid, + adc_mon_data); + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + parameter C_BASEADDR = 32'hffffffff; + parameter C_HIGHADDR = 32'h00000000; + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [63:0] rx_data; + + // dma interface + + output adc_clk; + output adc_dwr; + output [63:0] adc_ddata; + output adc_dsync; + input adc_dovf; + input adc_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // debug signals + + output adc_mon_valid; + output [55:0] adc_mon_data; + + // internal registers + + reg adc_data_cnt = 'd0; + reg adc_dsync = 'd0; + reg adc_dwr = 'd0; + reg [63:0] adc_ddata = 'd0; + reg up_adc_status_pn_err = 'd0; + reg up_adc_status_pn_oos = 'd0; + reg up_adc_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_ack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + + // internal signals + + wire [27:0] adc_data_a_s; + wire [27:0] adc_data_b_s; + wire adc_or_a_s; + wire adc_or_b_s; + wire adc_status_s; + wire adc_enable_a_s; + wire [31:0] adc_channel_data_a_s; + wire adc_enable_b_s; + wire [31:0] adc_channel_data_b_s; + wire up_adc_pn_err_a_s; + wire up_adc_pn_oos_a_s; + wire up_adc_or_a_s; + wire [31:0] up_adc_channel_rdata_a_s; + wire up_adc_channel_ack_a_s; + wire up_adc_pn_err_b_s; + wire up_adc_pn_oos_b_s; + wire up_adc_or_b_s; + wire [31:0] up_adc_channel_rdata_b_s; + wire up_adc_channel_ack_b_s; + wire [31:0] up_adc_common_rdata_s; + wire up_adc_common_ack_s; + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // monitor signals + + assign adc_mon_valid = 1'b1; + assign adc_mon_data[ 27: 0] = adc_data_a_s; + assign adc_mon_data[ 55: 28] = adc_data_b_s; + + // adc channels - dma interface + + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt; + case ({adc_enable_b_s, adc_enable_a_s}) + 2'b11: begin // both I and Q + adc_dsync <= 1'b1; + adc_dwr <= 1'b1; + adc_ddata <= {adc_channel_data_b_s[31:16], adc_channel_data_a_s[31:16], + adc_channel_data_b_s[15: 0], adc_channel_data_a_s[15: 0]}; + end + 2'b10: begin // Q only + adc_dsync <= 1'b1; + adc_dwr <= adc_data_cnt; + adc_ddata <= {adc_channel_data_b_s, adc_ddata[63:32]}; + end + 2'b01: begin // I only + adc_dsync <= 1'b1; + adc_dwr <= adc_data_cnt; + adc_ddata <= {adc_channel_data_a_s, adc_ddata[63:32]}; + end + default: begin // no channels + adc_dsync <= 1'b1; + adc_dwr <= 1'b1; + adc_ddata <= {4{16'hdead}}; + end + endcase + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_status_pn_err <= 'd0; + up_adc_status_pn_oos <= 'd0; + up_adc_status_or <= 'd0; + up_rdata <= 'd0; + up_ack <= 'd0; + end else begin + up_adc_status_pn_err <= up_adc_pn_err_a_s | up_adc_pn_err_b_s; + up_adc_status_pn_oos <= up_adc_pn_oos_a_s | up_adc_pn_oos_b_s; + up_adc_status_or <= up_adc_or_a_s | up_adc_or_b_s; + up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_a_s | up_adc_channel_rdata_b_s; + up_ack <= up_adc_common_ack_s | up_adc_channel_ack_a_s | up_adc_channel_ack_b_s; + end + end + + // main (device interface) + + axi_ad9250_if i_if ( + .rx_clk (rx_clk), + .rx_data (rx_data), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_a (adc_data_a_s), + .adc_data_b (adc_data_b_s), + .adc_or_a (adc_or_a_s), + .adc_or_b (adc_or_b_s), + .adc_status (adc_status_s)); + + // channel + + axi_ad9250_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_a_s), + .adc_or (adc_or_a_s), + .adc_dfmt_data (adc_channel_data_a_s), + .adc_enable (adc_enable_a_s), + .up_adc_pn_err (up_adc_pn_err_a_s), + .up_adc_pn_oos (up_adc_pn_oos_a_s), + .up_adc_or (up_adc_or_a_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_adc_channel_rdata_a_s), + .up_ack (up_adc_channel_ack_a_s)); + + // channel + + axi_ad9250_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_b_s), + .adc_or (adc_or_b_s), + .adc_dfmt_data (adc_channel_data_b_s), + .adc_enable (adc_enable_b_s), + .up_adc_pn_err (up_adc_pn_err_b_s), + .up_adc_pn_oos (up_adc_pn_oos_b_s), + .up_adc_or (up_adc_or_b_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_adc_channel_rdata_b_s), + .up_ack (up_adc_channel_ack_b_s)); + + // common processor control + + up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_status_pn_err (up_adc_status_pn_err), + .adc_status_pn_oos (up_adc_status_pn_oos), + .adc_status_or (up_adc_status_or), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd1), + .delay_clk (1'b0), + .delay_rst (), + .delay_sel (), + .delay_rwn (), + .delay_addr (), + .delay_wdata (), + .delay_rdata (5'd0), + .delay_ack_t (1'b0), + .delay_locked (1'b0), + .drp_clk (1'd0), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_adc_common_rdata_s), + .up_ack (up_adc_common_ack_s)); + + // up bus interface + + up_axi #( + .PCORE_BASEADDR (C_BASEADDR), + .PCORE_HIGHADDR (C_HIGHADDR)) + i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9250/axi_ad9250_alt.v b/library/axi_ad9250/axi_ad9250_alt.v new file mode 100755 index 000000000..bb4cd0087 --- /dev/null +++ b/library/axi_ad9250/axi_ad9250_alt.v @@ -0,0 +1,217 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9250_alt ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // dma interface + + adc_clk, + adc_dwr, + adc_ddata, + adc_dsync, + adc_dovf, + adc_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awid, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bid, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arid, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rid, + s_axi_rlast, + s_axi_rready, + + // debug signals + + adc_mon_valid, + adc_mon_data); + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [63:0] rx_data; + + // dma interface + + output adc_clk; + output adc_dwr; + output [63:0] adc_ddata; + output adc_dsync; + input adc_dovf; + input adc_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [13:0] s_axi_awaddr; + input [ 2:0] s_axi_awid; + input [ 7:0] s_axi_awlen; + input [ 2:0] s_axi_awsize; + input [ 1:0] s_axi_awburst; + input [ 0:0] s_axi_awlock; + input [ 3:0] s_axi_awcache; + input [ 2:0] s_axi_awprot; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + input s_axi_wlast; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + output [ 2:0] s_axi_bid; + input s_axi_bready; + input s_axi_arvalid; + input [13:0] s_axi_araddr; + input [ 2:0] s_axi_arid; + input [ 7:0] s_axi_arlen; + input [ 2:0] s_axi_arsize; + input [ 1:0] s_axi_arburst; + input [ 0:0] s_axi_arlock; + input [ 3:0] s_axi_arcache; + input [ 2:0] s_axi_arprot; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + output [ 2:0] s_axi_rid; + output s_axi_rlast; + input s_axi_rready; + + // debug signals + + output adc_mon_valid; + output [119:0] adc_mon_data; + + // defaults + + assign s_axi_bid = 3'd0; + assign s_axi_rid = 3'd0; + assign s_axi_rlast = 1'd0; + + // ad9250 lite version + + axi_ad9250 #( + .PCORE_ID (PCORE_ID), + .PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE), + .PCORE_IODELAY_GROUP ("adc_if_delay_group"), + .C_S_AXI_MIN_SIZE (32'hffff), + .C_BASEADDR (32'h00000000), + .C_HIGHADDR (32'hffffffff)) + i_ad9250 ( + .rx_clk (rx_clk), + .rx_data (rx_data), + .adc_clk (adc_clk), + .adc_dwr (adc_dwr), + .adc_ddata (adc_ddata), + .adc_dsync (adc_dsync), + .adc_dovf (adc_dovf), + .adc_dunf (adc_dunf), + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awaddr ({18'd0, s_axi_awaddr}), + .s_axi_awready (s_axi_awready), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_araddr ({18'd0, s_axi_araddr}), + .s_axi_arready (s_axi_arready), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rdata (s_axi_rdata), + .s_axi_rready (s_axi_rready), + .adc_mon_valid (adc_mon_valid), + .adc_mon_data (adc_mon_data)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9250/axi_ad9250_channel.v b/library/axi_ad9250/axi_ad9250_channel.v new file mode 100755 index 000000000..78ce1b1a1 --- /dev/null +++ b/library/axi_ad9250/axi_ad9250_channel.v @@ -0,0 +1,183 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad9250_channel ( + + // adc interface + + adc_clk, + adc_rst, + adc_data, + adc_or, + + // channel interface + + adc_dfmt_data, + adc_enable, + up_adc_pn_err, + up_adc_pn_oos, + up_adc_or, + + // processor interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack); + + // parameters + + parameter IQSEL = 0; + parameter CHID = 0; + + // adc interface + + input adc_clk; + input adc_rst; + input [27:0] adc_data; + input adc_or; + + // channel interface + + output [31:0] adc_dfmt_data; + output adc_enable; + output up_adc_pn_err; + output up_adc_pn_oos; + output up_adc_or; + + // processor interface + + input up_rstn; + input up_clk; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire adc_pn_type_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + + // instantiations + + axi_ad9250_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pn_type (adc_pn_type_s)); + + genvar n; + generate + for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1 + ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*14+13:n*14]), + .valid_out (), + .data_out (adc_dfmt_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_pn_sel (), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_pn_type (adc_pn_type_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl new file mode 100755 index 000000000..4d631c4ee --- /dev/null +++ b/library/axi_ad9250/axi_ad9250_hw.tcl @@ -0,0 +1,124 @@ + + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl + +set_module_property NAME axi_ad9250 +set_module_property DESCRIPTION "AXI AD9250 Interface" +set_module_property VERSION 1.0 +set_module_property DISPLAY_NAME axi_ad9250 + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL axi_ad9250_alt +add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v +add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v +add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v +add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v +add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v +add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v +add_fileset_file up_drp_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_drp_cntrl.v +add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v +add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v +add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v +add_fileset_file axi_ad9250_pnmon.v VERILOG PATH axi_ad9250_pnmon.v +add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v +add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v +add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v +add_fileset_file axi_ad9250_alt.v VERILOG PATH axi_ad9250_alt.v TOP_LEVEL_FILE + +# parameters + +add_parameter PCORE_ID INTEGER 0 +set_parameter_property PCORE_ID DEFAULT_VALUE 0 +set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID +set_parameter_property PCORE_ID TYPE INTEGER +set_parameter_property PCORE_ID UNITS None +set_parameter_property PCORE_ID HDL_PARAMETER true + +add_parameter PCORE_DEVICE_TYPE INTEGER 0 +set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0 +set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE +set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER +set_parameter_property PCORE_DEVICE_TYPE UNITS None +set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true + +# axi4 slave + +add_interface s_axi_clock clock end +add_interface_port s_axi_clock s_axi_aclk clk Input 1 + +add_interface s_axi_reset reset end +set_interface_property s_axi_reset associatedClock s_axi_clock +add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 + +add_interface s_axi axi4 end +set_interface_property s_axi associatedClock s_axi_clock +set_interface_property s_axi associatedReset s_axi_reset +add_interface_port s_axi s_axi_awvalid awvalid Input 1 +add_interface_port s_axi s_axi_awaddr awaddr Input 14 +add_interface_port s_axi s_axi_awready awready Output 1 +add_interface_port s_axi s_axi_wvalid wvalid Input 1 +add_interface_port s_axi s_axi_wdata wdata Input 32 +add_interface_port s_axi s_axi_wstrb wstrb Input 4 +add_interface_port s_axi s_axi_wready wready Output 1 +add_interface_port s_axi s_axi_bvalid bvalid Output 1 +add_interface_port s_axi s_axi_bresp bresp Output 2 +add_interface_port s_axi s_axi_bready bready Input 1 +add_interface_port s_axi s_axi_arvalid arvalid Input 1 +add_interface_port s_axi s_axi_araddr araddr Input 14 +add_interface_port s_axi s_axi_arready arready Output 1 +add_interface_port s_axi s_axi_rvalid rvalid Output 1 +add_interface_port s_axi s_axi_rresp rresp Output 2 +add_interface_port s_axi s_axi_rdata rdata Output 32 +add_interface_port s_axi s_axi_rready rready Input 1 +add_interface_port s_axi s_axi_awid awid Input 3 +add_interface_port s_axi s_axi_awlen awlen Input 8 +add_interface_port s_axi s_axi_awsize awsize Input 3 +add_interface_port s_axi s_axi_awburst awburst Input 2 +add_interface_port s_axi s_axi_awlock awlock Input 1 +add_interface_port s_axi s_axi_awcache awcache Input 4 +add_interface_port s_axi s_axi_awprot awprot Input 3 +add_interface_port s_axi s_axi_wlast wlast Input 1 +add_interface_port s_axi s_axi_bid bid Output 3 +add_interface_port s_axi s_axi_arid arid Input 3 +add_interface_port s_axi s_axi_arlen arlen Input 8 +add_interface_port s_axi s_axi_arsize arsize Input 3 +add_interface_port s_axi s_axi_arburst arburst Input 2 +add_interface_port s_axi s_axi_arlock arlock Input 1 +add_interface_port s_axi s_axi_arcache arcache Input 4 +add_interface_port s_axi s_axi_arprot arprot Input 3 +add_interface_port s_axi s_axi_rid rid Output 3 +add_interface_port s_axi s_axi_rlast rlast Output 1 + + +# transceiver interface + +add_interface xcvr_clk clock end +add_interface_port xcvr_clk rx_clk clk Input 1 + +add_interface xcvr_data conduit end +set_interface_property xcvr_data associatedClock xcvr_clk +add_interface_port xcvr_data rx_data data Input 64 + +# dma interface + +add_interface adc_clock clock start +add_interface_port adc_clock adc_clk clk Output 1 + +add_interface adc_dma_if conduit end +set_interface_property adc_dma_if associatedClock adc_clock +add_interface_port adc_dma_if adc_ddata ddata Output 64 +add_interface_port adc_dma_if adc_dsync dsync Output 1 +add_interface_port adc_dma_if adc_dovf dovf Input 1 +add_interface_port adc_dma_if adc_dunf dunf Input 1 +add_interface_port adc_dma_if adc_dwr dwr Output 1 + +# signal tap + +add_interface adc_mon_if conduit end +set_interface_property adc_mon_if associatedClock adc_clock +add_interface_port adc_mon_if adc_mon_valid valid Output 1 +add_interface_port adc_mon_if adc_mon_data data Output 56 + diff --git a/library/axi_ad9250/axi_ad9250_if.v b/library/axi_ad9250/axi_ad9250_if.v new file mode 100755 index 000000000..6d1cd1fbd --- /dev/null +++ b/library/axi_ad9250/axi_ad9250_if.v @@ -0,0 +1,122 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface + +`timescale 1ns/100ps + +module axi_ad9250_if ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // adc data output + + adc_clk, + adc_rst, + adc_data_a, + adc_data_b, + adc_or_a, + adc_or_b, + adc_status); + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [63:0] rx_data; + + // adc data output + + output adc_clk; + input adc_rst; + output [27:0] adc_data_a; + output [27:0] adc_data_b; + output adc_or_a; + output adc_or_b; + output adc_status; + + // internal registers + + reg adc_status = 'd0; + + // internal signals + + wire [15:0] adc_data_a_s1_s; + wire [15:0] adc_data_a_s0_s; + wire [15:0] adc_data_b_s1_s; + wire [15:0] adc_data_b_s0_s; + + // adc clock is the reference clock + + assign adc_clk = rx_clk; + assign adc_or_a = 1'b0; + assign adc_or_b = 1'b0; + + // adc channels + + assign adc_data_a = {adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]}; + + assign adc_data_b = {adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]}; + + // data multiplex + + assign adc_data_a_s1_s = {rx_data[25:24], rx_data[23:16], rx_data[31:26]}; + assign adc_data_a_s0_s = {rx_data[ 9: 8], rx_data[ 7: 0], rx_data[15:10]}; + + assign adc_data_b_s1_s = {rx_data[57:56], rx_data[55:48], rx_data[63:58]}; + assign adc_data_b_s0_s = {rx_data[41:40], rx_data[39:32], rx_data[47:42]}; + + // status + + always @(posedge rx_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9250/axi_ad9250_ip.tcl b/library/axi_ad9250/axi_ad9250_ip.tcl new file mode 100755 index 000000000..588d2ab43 --- /dev/null +++ b/library/axi_ad9250/axi_ad9250_ip.tcl @@ -0,0 +1,26 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9250 +adi_ip_files axi_ad9250 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "axi_ad9250_pnmon.v" \ + "axi_ad9250_channel.v" \ + "axi_ad9250_if.v" \ + "axi_ad9250.v" ] + +adi_ip_properties axi_ad9250 + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9250/axi_ad9250_pnmon.v b/library/axi_ad9250/axi_ad9250_pnmon.v new file mode 100755 index 000000000..50d35ed12 --- /dev/null +++ b/library/axi_ad9250/axi_ad9250_pnmon.v @@ -0,0 +1,224 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9250_pnmon ( + + // adc interface + + adc_clk, + adc_data, + + // pn out of sync and error + + adc_pn_oos, + adc_pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + + adc_pn_type); + + // adc interface + + input adc_clk; + input [27:0] adc_data; + + // pn out of sync and error + + output adc_pn_oos; + output adc_pn_err; + + // processor interface PN9 (0x0), PN23 (0x1) + + input adc_pn_type; + + // internal registers + + reg [27:0] adc_pn_data = 'd0; + reg adc_pn_match_d_1 = 'd0; + reg adc_pn_match_d_0 = 'd0; + reg adc_pn_match_z = 'd0; + reg adc_pn_err = 'd0; + reg [ 6:0] adc_pn_oos_count = 'd0; + reg adc_pn_oos = 'd0; + + // internal signals + + wire [27:0] adc_pn_data_in_s; + wire adc_pn_match_d_1_s; + wire adc_pn_match_d_0_s; + wire adc_pn_match_z_s; + wire adc_pn_match_s; + wire [27:0] adc_pn_data_s; + wire adc_pn_update_s; + wire adc_pn_err_s; + + // PN23 function + + function [27:0] pn23; + input [27:0] din; + reg [27:0] dout; + begin + dout[27] = din[22] ^ din[17]; + dout[26] = din[21] ^ din[16]; + dout[25] = din[20] ^ din[15]; + dout[24] = din[19] ^ din[14]; + dout[23] = din[18] ^ din[13]; + dout[22] = din[17] ^ din[12]; + dout[21] = din[16] ^ din[11]; + dout[20] = din[15] ^ din[10]; + dout[19] = din[14] ^ din[ 9]; + dout[18] = din[13] ^ din[ 8]; + dout[17] = din[12] ^ din[ 7]; + dout[16] = din[11] ^ din[ 6]; + dout[15] = din[10] ^ din[ 5]; + dout[14] = din[ 9] ^ din[ 4]; + dout[13] = din[ 8] ^ din[ 3]; + dout[12] = din[ 7] ^ din[ 2]; + dout[11] = din[ 6] ^ din[ 1]; + dout[10] = din[ 5] ^ din[ 0]; + dout[ 9] = din[ 4] ^ din[22] ^ din[17]; + dout[ 8] = din[ 3] ^ din[21] ^ din[16]; + dout[ 7] = din[ 2] ^ din[20] ^ din[15]; + dout[ 6] = din[ 1] ^ din[19] ^ din[14]; + dout[ 5] = din[ 0] ^ din[18] ^ din[13]; + dout[ 4] = din[22] ^ din[12]; + dout[ 3] = din[21] ^ din[11]; + dout[ 2] = din[20] ^ din[10]; + dout[ 1] = din[19] ^ din[ 9]; + dout[ 0] = din[18] ^ din[ 8]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [27:0] pn9; + input [27:0] din; + reg [27:0] dout; + begin + dout[27] = din[ 8] ^ din[ 4]; + dout[26] = din[ 7] ^ din[ 3]; + dout[25] = din[ 6] ^ din[ 2]; + dout[24] = din[ 5] ^ din[ 1]; + dout[23] = din[ 4] ^ din[ 0]; + dout[22] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[21] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[20] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[19] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[18] = din[ 8] ^ din[ 0]; + dout[17] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[16] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[15] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[14] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[13] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[12] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[11] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[10] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 9] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 8] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 4] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 2] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 1] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 0] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + pn9 = dout; + end + endfunction + + // pn sequence checking algorithm is commonly used in most applications. + // if oos is asserted (pn is out of sync): + // the next sequence is generated from the incoming data. + // if 16 sequences match consecutively, oos is cleared (de-asserted). + // if oos is de-asserted (pn is in sync) + // the next sequence is generated from the current sequence. + // if 64 sequences mismatch consecutively, oos is set (asserted). + // if oos is de-asserted, any spurious mismatches sets the error register. + // ideally, processor should make sure both oos == 0x0 and err == 0x0. + + assign adc_pn_data_in_s = {~adc_data[27], adc_data[26:14], ~adc_data[13], adc_data[12:0]}; + assign adc_pn_match_d_1_s = (adc_pn_data_in_s[27:14] == adc_pn_data[27:14]) ? 1'b1 : 1'b0; + assign adc_pn_match_d_0_s = (adc_pn_data_in_s[13: 0] == adc_pn_data[13: 0]) ? 1'b1 : 1'b0; + assign adc_pn_match_z_s = (adc_pn_data_in_s == 28'd0) ? 1'b0 : 1'b1; + assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z; + assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data; + assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s); + assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s); + + // pn running sequence + + always @(posedge adc_clk) begin + if (adc_pn_type == 1'b0) begin + adc_pn_data <= pn9(adc_pn_data_s); + end else begin + adc_pn_data <= pn23(adc_pn_data_s); + end + end + + // pn oos and counters (64 to clear and set). + + always @(posedge adc_clk) begin + adc_pn_match_d_1 <= adc_pn_match_d_1_s; + adc_pn_match_d_0 <= adc_pn_match_d_0_s; + adc_pn_match_z <= adc_pn_match_z_s; + adc_pn_err <= adc_pn_err_s; + if (adc_pn_update_s == 1'b1) begin + if (adc_pn_oos_count >= 16) begin + adc_pn_oos_count <= 'd0; + adc_pn_oos <= ~adc_pn_oos; + end else begin + adc_pn_oos_count <= adc_pn_oos_count + 1'b1; + adc_pn_oos <= adc_pn_oos; + end + end else begin + adc_pn_oos_count <= 'd0; + adc_pn_oos <= adc_pn_oos; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/projects/common/a5gt/a5gt_system_assign.tcl b/projects/common/a5gt/a5gt_system_assign.tcl new file mode 100755 index 000000000..98347fcf5 --- /dev/null +++ b/projects/common/a5gt/a5gt_system_assign.tcl @@ -0,0 +1,787 @@ + +# clocks and resets + +set_location_assignment PIN_C34 -to sys_clk +set_location_assignment PIN_D34 -to "sys_clk(n)" +set_instance_assignment -name IO_STANDARD LVDS -to sys_clk +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sys_clk -disable + +set_location_assignment PIN_L6 -to sys_resetn +set_instance_assignment -name IO_STANDARD "2.5 V" -to sys_resetn + +# ddr3 + +set_location_assignment PIN_B31 -to ddr3_a[0] +set_location_assignment PIN_A30 -to ddr3_a[1] +set_location_assignment PIN_A31 -to ddr3_a[2] +set_location_assignment PIN_A32 -to ddr3_a[3] +set_location_assignment PIN_A33 -to ddr3_a[4] +set_location_assignment PIN_B33 -to ddr3_a[5] +set_location_assignment PIN_H31 -to ddr3_a[6] +set_location_assignment PIN_J31 -to ddr3_a[7] +set_location_assignment PIN_C31 -to ddr3_a[8] +set_location_assignment PIN_D31 -to ddr3_a[9] +set_location_assignment PIN_C32 -to ddr3_a[10] +set_location_assignment PIN_D32 -to ddr3_a[11] +set_location_assignment PIN_N31 -to ddr3_a[12] +set_location_assignment PIN_P31 -to ddr3_a[13] +set_location_assignment PIN_M32 -to ddr3_ba[0] +set_location_assignment PIN_N32 -to ddr3_ba[1] +set_location_assignment PIN_J34 -to ddr3_ba[2] +set_location_assignment PIN_B30 -to ddr3_clk_p +set_location_assignment PIN_C30 -to ddr3_clk_n +set_location_assignment PIN_E31 -to ddr3_cke +set_location_assignment PIN_L34 -to ddr3_cs_n +set_location_assignment PIN_K34 -to ddr3_ras_n +set_location_assignment PIN_L33 -to ddr3_cas_n +set_location_assignment PIN_M33 -to ddr3_we_n +set_location_assignment PIN_G30 -to ddr3_reset_n +set_location_assignment PIN_L31 -to ddr3_odt +set_location_assignment PIN_F33 -to ddr3_rzq + +set_location_assignment PIN_N30 -to ddr3_dqs_p[0] +set_location_assignment PIN_P30 -to ddr3_dqs_n[0] +set_location_assignment PIN_R29 -to ddr3_dqs_p[1] +set_location_assignment PIN_T29 -to ddr3_dqs_n[1] +set_location_assignment PIN_J30 -to ddr3_dm[0] +set_location_assignment PIN_J29 -to ddr3_dm[1] +set_location_assignment PIN_B28 -to ddr3_dq[0] +set_location_assignment PIN_C29 -to ddr3_dq[1] +set_location_assignment PIN_R30 -to ddr3_dq[2] +set_location_assignment PIN_A29 -to ddr3_dq[3] +set_location_assignment PIN_A28 -to ddr3_dq[4] +set_location_assignment PIN_L30 -to ddr3_dq[5] +set_location_assignment PIN_D30 -to ddr3_dq[6] +set_location_assignment PIN_D29 -to ddr3_dq[7] +set_location_assignment PIN_L28 -to ddr3_dq[8] +set_location_assignment PIN_M28 -to ddr3_dq[9] +set_location_assignment PIN_H28 -to ddr3_dq[10] +set_location_assignment PIN_C28 -to ddr3_dq[11] +set_location_assignment PIN_D28 -to ddr3_dq[12] +set_location_assignment PIN_F28 -to ddr3_dq[13] +set_location_assignment PIN_M29 -to ddr3_dq[14] +set_location_assignment PIN_N29 -to ddr3_dq[15] + +set_location_assignment PIN_R28 -to ddr3_dqs_p[2] +set_location_assignment PIN_T28 -to ddr3_dqs_n[2] +set_location_assignment PIN_M26 -to ddr3_dqs_p[3] +set_location_assignment PIN_N26 -to ddr3_dqs_n[3] +set_location_assignment PIN_K27 -to ddr3_dm[2] +set_location_assignment PIN_J26 -to ddr3_dm[3] +set_location_assignment PIN_P27 -to ddr3_dq[16] +set_location_assignment PIN_R27 -to ddr3_dq[17] +set_location_assignment PIN_H27 -to ddr3_dq[18] +set_location_assignment PIN_B27 -to ddr3_dq[19] +set_location_assignment PIN_C27 -to ddr3_dq[20] +set_location_assignment PIN_E27 -to ddr3_dq[21] +set_location_assignment PIN_M27 -to ddr3_dq[22] +set_location_assignment PIN_N27 -to ddr3_dq[23] +set_location_assignment PIN_C26 -to ddr3_dq[24] +set_location_assignment PIN_D26 -to ddr3_dq[25] +set_location_assignment PIN_K25 -to ddr3_dq[26] +set_location_assignment PIN_R26 -to ddr3_dq[27] +set_location_assignment PIN_T27 -to ddr3_dq[28] +set_location_assignment PIN_A26 -to ddr3_dq[29] +set_location_assignment PIN_F26 -to ddr3_dq[30] +set_location_assignment PIN_G26 -to ddr3_dq[31] + +set_location_assignment PIN_A20 -to ddr3_dqs_p[4] +set_location_assignment PIN_B21 -to ddr3_dqs_n[4] +set_location_assignment PIN_C23 -to ddr3_dqs_p[5] +set_location_assignment PIN_D23 -to ddr3_dqs_n[5] +set_location_assignment PIN_M21 -to ddr3_dm[4] +set_location_assignment PIN_B22 -to ddr3_dm[5] +set_location_assignment PIN_D20 -to ddr3_dq[32] +set_location_assignment PIN_H21 -to ddr3_dq[33] +set_location_assignment PIN_D21 -to ddr3_dq[34] +set_location_assignment PIN_J21 -to ddr3_dq[35] +set_location_assignment PIN_A21 -to ddr3_dq[36] +set_location_assignment PIN_G21 -to ddr3_dq[37] +set_location_assignment PIN_A22 -to ddr3_dq[38] +set_location_assignment PIN_C20 -to ddr3_dq[39] +set_location_assignment PIN_A23 -to ddr3_dq[40] +set_location_assignment PIN_E22 -to ddr3_dq[41] +set_location_assignment PIN_L22 -to ddr3_dq[42] +set_location_assignment PIN_C22 -to ddr3_dq[43] +set_location_assignment PIN_N22 -to ddr3_dq[44] +set_location_assignment PIN_F22 -to ddr3_dq[45] +set_location_assignment PIN_P22 -to ddr3_dq[46] +set_location_assignment PIN_J22 -to ddr3_dq[47] + +set_location_assignment PIN_D24 -to ddr3_dqs_p[6] +set_location_assignment PIN_E24 -to ddr3_dqs_n[6] +set_location_assignment PIN_A25 -to ddr3_dqs_p[7] +set_location_assignment PIN_B25 -to ddr3_dqs_n[7] +set_location_assignment PIN_J23 -to ddr3_dm[6] +set_location_assignment PIN_D25 -to ddr3_dm[7] +set_location_assignment PIN_C24 -to ddr3_dq[48] +set_location_assignment PIN_M23 -to ddr3_dq[49] +set_location_assignment PIN_B24 -to ddr3_dq[50] +set_location_assignment PIN_R23 -to ddr3_dq[51] +set_location_assignment PIN_G24 -to ddr3_dq[52] +set_location_assignment PIN_G23 -to ddr3_dq[53] +set_location_assignment PIN_F24 -to ddr3_dq[54] +set_location_assignment PIN_F23 -to ddr3_dq[55] +set_location_assignment PIN_R24 -to ddr3_dq[56] +set_location_assignment PIN_G25 -to ddr3_dq[57] +set_location_assignment PIN_T26 -to ddr3_dq[58] +set_location_assignment PIN_E25 -to ddr3_dq[59] +set_location_assignment PIN_N24 -to ddr3_dq[60] +set_location_assignment PIN_K24 -to ddr3_dq[61] +set_location_assignment PIN_T25 -to ddr3_dq[62] +set_location_assignment PIN_P24 -to ddr3_dq[63] + +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_p +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt +set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_reset_n +set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_rzq + +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15] + +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31] + +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[32] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[33] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[34] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[35] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[36] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[37] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[38] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[39] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[40] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[41] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[42] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[43] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[44] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[45] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[46] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[47] + +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[48] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[49] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[50] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[51] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[52] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[53] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[54] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[55] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[56] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[57] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[58] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[59] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[60] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[61] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[62] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[63] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt + +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dm[0] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dm[1] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[0] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[1] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[2] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[3] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[4] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[5] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[6] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[7] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[8] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[9] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[10] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[11] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[12] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[13] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[14] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[15] + +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dm[2] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dm[3] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[16] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[17] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[18] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[19] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[20] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[21] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[22] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[23] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[24] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[25] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[26] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[27] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[28] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[29] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[30] +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[31] + +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_p +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_n + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15] + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31] + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[32] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[33] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[34] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[35] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[36] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[37] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[38] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[39] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[40] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[41] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[42] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[43] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[44] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[45] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[46] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[47] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[32] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[33] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[34] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[35] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[36] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[37] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[38] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[39] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[40] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[41] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[42] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[43] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[44] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[45] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[46] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[47] + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[48] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[49] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[50] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[51] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[52] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[53] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[54] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[55] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[56] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[57] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[58] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[59] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[60] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[61] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[62] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[63] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[48] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[49] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[50] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[51] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[52] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[53] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[54] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[55] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[56] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[57] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[58] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[59] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[60] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[61] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[62] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[63] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_p +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cke +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cs_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ras_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cas_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_we_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_reset_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_odt + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[14] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[15] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[16] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[17] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[18] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[19] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[20] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[21] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[22] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[23] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[24] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[25] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[26] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[27] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[28] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[29] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[30] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[31] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[32] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[33] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[34] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[35] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[36] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[37] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[38] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[39] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[40] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[41] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[42] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[43] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[44] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[45] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[46] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[47] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[48] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[49] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[50] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[51] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[52] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[53] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[54] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[55] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[56] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[57] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[58] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[59] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[60] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[61] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[62] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[63] + +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[0] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[0] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[1] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[1] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[0] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[1] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[0] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[1] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[2] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[3] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[4] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[5] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[6] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[7] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[8] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[9] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[10] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[11] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[12] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[13] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[14] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[15] + +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[2] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[2] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[3] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[3] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[2] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[3] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[16] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[17] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[18] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[19] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[20] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[21] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[22] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[23] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[24] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[25] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[26] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[27] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[28] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[29] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[30] +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[31] + +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_fmcjesdadc1|sys_ddr3_cntrl + +set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_addr_cmd_clk +set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_avl_clk +set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_config_clk +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_afi_clk +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_hr_clk + +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[4].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[5].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[6].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[7].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_mem_stable_n +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_n +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n + +# ethernet interface + +set_location_assignment PIN_M14 -to eth_rx_clk +set_location_assignment PIN_N14 -to eth_rx_data[0] +set_location_assignment PIN_N15 -to eth_rx_data[1] +set_location_assignment PIN_P15 -to eth_rx_data[2] +set_location_assignment PIN_B9 -to eth_rx_data[3] +set_location_assignment PIN_C9 -to eth_rx_cntrl[4] +set_location_assignment PIN_K18 -to eth_tx_clk_out[5] +set_location_assignment PIN_L18 -to eth_tx_data[0] +set_location_assignment PIN_R11 -to eth_tx_data[1] +set_location_assignment PIN_T11 -to eth_tx_data[2] +set_location_assignment PIN_H9 -to eth_tx_data[3] +set_location_assignment PIN_J9 -to eth_tx_cntrl +set_location_assignment PIN_F7 -to eth_mdc +set_location_assignment PIN_G7 -to eth_mdio_i +set_location_assignment PIN_F9 -to eth_mdio_o +set_location_assignment PIN_G9 -to eth_mdio_t + +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_clk +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_cntrl[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_clk_out[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_cntrl +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdc +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_i +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_o +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_t + +# leds + +set_location_assignment PIN_M19 -to led_grn[0] +set_location_assignment PIN_L19 -to led_grn[1] +set_location_assignment PIN_K19 -to led_grn[2] +set_location_assignment PIN_J19 -to led_grn[3] +set_location_assignment PIN_K20 -to led_grn[4] +set_location_assignment PIN_J20 -to led_grn[5] +set_location_assignment PIN_T20 -to led_grn[6] +set_location_assignment PIN_R20 -to led_grn[7] +set_location_assignment PIN_N20 -to led_red[0] +set_location_assignment PIN_C15 -to led_red[1] +set_location_assignment PIN_AL28 -to led_red[2] +set_location_assignment PIN_F11 -to led_red[3] +set_location_assignment PIN_AJ31 -to led_red[4] +set_location_assignment PIN_AN34 -to led_red[5] +set_location_assignment PIN_AJ34 -to led_red[6] +set_location_assignment PIN_AK33 -to led_red[7] +set_location_assignment PIN_D6 -to push_buttons[0] +set_location_assignment PIN_C6 -to push_buttons[1] +set_location_assignment PIN_K7 -to push_buttons[2] +set_location_assignment PIN_C8 -to dip_switches[0] +set_location_assignment PIN_D8 -to dip_switches[1] +set_location_assignment PIN_E7 -to dip_switches[2] +set_location_assignment PIN_E6 -to dip_switches[3] +set_location_assignment PIN_G8 -to dip_switches[4] +set_location_assignment PIN_F8 -to dip_switches[5] +set_location_assignment PIN_D15 -to dip_switches[6] +set_location_assignment PIN_G11 -to dip_switches[7] + +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[7] + + diff --git a/projects/fmcjesdadc1/a5gt/system_bd.qsys b/projects/fmcjesdadc1/a5gt/system_bd.qsys new file mode 100755 index 000000000..d1b19629f --- /dev/null +++ b/projects/fmcjesdadc1/a5gt/system_bd.qsys @@ -0,0 +1,2645 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + Create an adjpllin signal to connect with an upstream PLL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + sys_cpu.jtag_debug_module + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + ]]> + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_sys_int_mem + + ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NO_INTERACTIVE_WINDOWS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_sys_ethernet_desc_mem + + ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + Create an adjpllin signal to connect with an upstream PLL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc new file mode 100755 index 000000000..5a9ce1ef8 --- /dev/null +++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc @@ -0,0 +1,36 @@ +################################################################################ +################################################################################ + +create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}] +create_clock -period "4.000 ns" -name n_clk_250m [get_ports {ref_clk}] +create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}] +create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set clk_100m [get_clocks {i_fmcjesdadc1|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] +set clk_166m [get_clocks {i_fmcjesdadc1|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] +set clk_125m [get_clocks {i_fmcjesdadc1|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] +set clk_25m [get_clocks {i_fmcjesdadc1|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] +set clk_2m5 [get_clocks {i_fmcjesdadc1|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] +set clk_rxlink [get_clocks {i_fmcjesdadc1|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] + +set_false_path -from {sys_resetn} -to * +set_false_path -from $clk_100m -to $clk_166m +set_false_path -from $clk_100m -to $clk_rxlink +set_false_path -from $clk_166m -to $clk_100m +set_false_path -from $clk_166m -to $clk_rxlink +set_false_path -from $clk_rxlink -to $clk_100m +set_false_path -from $clk_rxlink -to $clk_166m + +set_false_path -from $clk_125m -to $clk_25m +set_false_path -from $clk_125m -to $clk_2m5 +set_false_path -from $clk_25m -to $clk_125m +set_false_path -from $clk_25m -to $clk_2m5 +set_false_path -from $clk_2m5 -to $clk_125m +set_false_path -from $clk_2m5 -to $clk_25m + +################################################################################ +################################################################################ + diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl new file mode 100755 index 000000000..2f33f1e1d --- /dev/null +++ b/projects/fmcjesdadc1/a5gt/system_project.tcl @@ -0,0 +1,859 @@ +################################################################################ +################################################################################ + +source ../../scripts/adi_env.tcl +project_new fmcjesdadc1 -overwrite + +set_global_assignment -name FAMILY "Arria V" +set_global_assignment -name DEVICE 5AGTFD7K3F40I5 +set_global_assignment -name TOP_LEVEL_ENTITY fmcjesdadc1_top +set_global_assignment -name SDC_FILE fmcjesdadc1.sdc +set_global_assignment -name QIP_FILE fmcjesdadc1/synthesis/fmcjesdadc1.qip +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v +set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v +set_global_assignment -name VERILOG_FILE fmcjesdadc1_top.v + +# clocks and resets + +set_location_assignment PIN_C34 -to sys_clk +set_location_assignment PIN_D34 -to "sys_clk(n)" +set_instance_assignment -name IO_STANDARD LVDS -to sys_clk +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sys_clk -disable + +set_location_assignment PIN_L6 -to sys_resetn +set_instance_assignment -name IO_STANDARD "2.5 V" -to sys_resetn + +# reference clock + +set_location_assignment PIN_AB9 -to ref_clk +set_location_assignment PIN_AB8 -to "ref_clk(n)" +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to ref_clk +set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to ref_clk +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to ref_clk + +# lane data + +set_location_assignment PIN_AE1 -to rx_data[0] +set_location_assignment PIN_AE2 -to "rx_data[0](n)" +set_location_assignment PIN_AA1 -to rx_data[1] +set_location_assignment PIN_AA2 -to "rx_data[1](n)" +set_location_assignment PIN_U1 -to rx_data[2] +set_location_assignment PIN_U2 -to "rx_data[2](n)" +set_location_assignment PIN_R1 -to rx_data[3] +set_location_assignment PIN_R2 -to "rx_data[3](n)" +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[0] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[1] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[2] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[3] +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[0] +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[1] +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[2] +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[3] + +# jesd signals + +set_location_assignment PIN_AD25 -to rx_sync +set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sync + +set_location_assignment PIN_AC24 -to rx_sysref +set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sysref + +# spi + +set_location_assignment PIN_AG27 -to spi_csn +set_location_assignment PIN_AH27 -to spi_clk +set_location_assignment PIN_AD24 -to spi_sdio + +set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn +set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio + +# ddr3 + +set_location_assignment PIN_B31 -to ddr3_a[0] +set_location_assignment PIN_A30 -to ddr3_a[1] +set_location_assignment PIN_A31 -to ddr3_a[2] +set_location_assignment PIN_A32 -to ddr3_a[3] +set_location_assignment PIN_A33 -to ddr3_a[4] +set_location_assignment PIN_B33 -to ddr3_a[5] +set_location_assignment PIN_H31 -to ddr3_a[6] +set_location_assignment PIN_J31 -to ddr3_a[7] +set_location_assignment PIN_C31 -to ddr3_a[8] +set_location_assignment PIN_D31 -to ddr3_a[9] +set_location_assignment PIN_C32 -to ddr3_a[10] +set_location_assignment PIN_D32 -to ddr3_a[11] +set_location_assignment PIN_N31 -to ddr3_a[12] +set_location_assignment PIN_P31 -to ddr3_a[13] +set_location_assignment PIN_M32 -to ddr3_ba[0] +set_location_assignment PIN_N32 -to ddr3_ba[1] +set_location_assignment PIN_J34 -to ddr3_ba[2] +set_location_assignment PIN_B30 -to ddr3_clk_p +set_location_assignment PIN_C30 -to ddr3_clk_n +set_location_assignment PIN_E31 -to ddr3_cke +set_location_assignment PIN_L34 -to ddr3_cs_n +set_location_assignment PIN_K34 -to ddr3_ras_n +set_location_assignment PIN_L33 -to ddr3_cas_n +set_location_assignment PIN_M33 -to ddr3_we_n +set_location_assignment PIN_G30 -to ddr3_reset_n +set_location_assignment PIN_L31 -to ddr3_odt +set_location_assignment PIN_F33 -to ddr3_rzq + +set_location_assignment PIN_N30 -to ddr3_dqs_p[0] +set_location_assignment PIN_P30 -to ddr3_dqs_n[0] +set_location_assignment PIN_R29 -to ddr3_dqs_p[1] +set_location_assignment PIN_T29 -to ddr3_dqs_n[1] +set_location_assignment PIN_J30 -to ddr3_dm[0] +set_location_assignment PIN_J29 -to ddr3_dm[1] +set_location_assignment PIN_B28 -to ddr3_dq[0] +set_location_assignment PIN_C29 -to ddr3_dq[1] +set_location_assignment PIN_R30 -to ddr3_dq[2] +set_location_assignment PIN_A29 -to ddr3_dq[3] +set_location_assignment PIN_A28 -to ddr3_dq[4] +set_location_assignment PIN_L30 -to ddr3_dq[5] +set_location_assignment PIN_D30 -to ddr3_dq[6] +set_location_assignment PIN_D29 -to ddr3_dq[7] +set_location_assignment PIN_L28 -to ddr3_dq[8] +set_location_assignment PIN_M28 -to ddr3_dq[9] +set_location_assignment PIN_H28 -to ddr3_dq[10] +set_location_assignment PIN_C28 -to ddr3_dq[11] +set_location_assignment PIN_D28 -to ddr3_dq[12] +set_location_assignment PIN_F28 -to ddr3_dq[13] +set_location_assignment PIN_M29 -to ddr3_dq[14] +set_location_assignment PIN_N29 -to ddr3_dq[15] + +set_location_assignment PIN_R28 -to ddr3_dqs_p[2] +set_location_assignment PIN_T28 -to ddr3_dqs_n[2] +set_location_assignment PIN_M26 -to ddr3_dqs_p[3] +set_location_assignment PIN_N26 -to ddr3_dqs_n[3] +set_location_assignment PIN_K27 -to ddr3_dm[2] +set_location_assignment PIN_J26 -to ddr3_dm[3] +set_location_assignment PIN_P27 -to ddr3_dq[16] +set_location_assignment PIN_R27 -to ddr3_dq[17] +set_location_assignment PIN_H27 -to ddr3_dq[18] +set_location_assignment PIN_B27 -to ddr3_dq[19] +set_location_assignment PIN_C27 -to ddr3_dq[20] +set_location_assignment PIN_E27 -to ddr3_dq[21] +set_location_assignment PIN_M27 -to ddr3_dq[22] +set_location_assignment PIN_N27 -to ddr3_dq[23] +set_location_assignment PIN_C26 -to ddr3_dq[24] +set_location_assignment PIN_D26 -to ddr3_dq[25] +set_location_assignment PIN_K25 -to ddr3_dq[26] +set_location_assignment PIN_R26 -to ddr3_dq[27] +set_location_assignment PIN_T27 -to ddr3_dq[28] +set_location_assignment PIN_A26 -to ddr3_dq[29] +set_location_assignment PIN_F26 -to ddr3_dq[30] +set_location_assignment PIN_G26 -to ddr3_dq[31] + +set_location_assignment PIN_A20 -to ddr3_dqs_p[4] +set_location_assignment PIN_B21 -to ddr3_dqs_n[4] +set_location_assignment PIN_C23 -to ddr3_dqs_p[5] +set_location_assignment PIN_D23 -to ddr3_dqs_n[5] +set_location_assignment PIN_M21 -to ddr3_dm[4] +set_location_assignment PIN_B22 -to ddr3_dm[5] +set_location_assignment PIN_D20 -to ddr3_dq[32] +set_location_assignment PIN_H21 -to ddr3_dq[33] +set_location_assignment PIN_D21 -to ddr3_dq[34] +set_location_assignment PIN_J21 -to ddr3_dq[35] +set_location_assignment PIN_A21 -to ddr3_dq[36] +set_location_assignment PIN_G21 -to ddr3_dq[37] +set_location_assignment PIN_A22 -to ddr3_dq[38] +set_location_assignment PIN_C20 -to ddr3_dq[39] +set_location_assignment PIN_A23 -to ddr3_dq[40] +set_location_assignment PIN_E22 -to ddr3_dq[41] +set_location_assignment PIN_L22 -to ddr3_dq[42] +set_location_assignment PIN_C22 -to ddr3_dq[43] +set_location_assignment PIN_N22 -to ddr3_dq[44] +set_location_assignment PIN_F22 -to ddr3_dq[45] +set_location_assignment PIN_P22 -to ddr3_dq[46] +set_location_assignment PIN_J22 -to ddr3_dq[47] + +set_location_assignment PIN_D24 -to ddr3_dqs_p[6] +set_location_assignment PIN_E24 -to ddr3_dqs_n[6] +set_location_assignment PIN_A25 -to ddr3_dqs_p[7] +set_location_assignment PIN_B25 -to ddr3_dqs_n[7] +set_location_assignment PIN_J23 -to ddr3_dm[6] +set_location_assignment PIN_D25 -to ddr3_dm[7] +set_location_assignment PIN_C24 -to ddr3_dq[48] +set_location_assignment PIN_M23 -to ddr3_dq[49] +set_location_assignment PIN_B24 -to ddr3_dq[50] +set_location_assignment PIN_R23 -to ddr3_dq[51] +set_location_assignment PIN_G24 -to ddr3_dq[52] +set_location_assignment PIN_G23 -to ddr3_dq[53] +set_location_assignment PIN_F24 -to ddr3_dq[54] +set_location_assignment PIN_F23 -to ddr3_dq[55] +set_location_assignment PIN_R24 -to ddr3_dq[56] +set_location_assignment PIN_G25 -to ddr3_dq[57] +set_location_assignment PIN_T26 -to ddr3_dq[58] +set_location_assignment PIN_E25 -to ddr3_dq[59] +set_location_assignment PIN_N24 -to ddr3_dq[60] +set_location_assignment PIN_K24 -to ddr3_dq[61] +set_location_assignment PIN_T25 -to ddr3_dq[62] +set_location_assignment PIN_P24 -to ddr3_dq[63] + +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_p +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt +set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_reset_n +set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_rzq + +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15] + +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31] + +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[32] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[33] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[34] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[35] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[36] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[37] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[38] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[39] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[40] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[41] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[42] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[43] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[44] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[45] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[46] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[47] + +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[48] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[49] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[50] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[51] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[52] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[53] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[54] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[55] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[56] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[57] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[58] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[59] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[60] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[61] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[62] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[63] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt + +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dm[0] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dm[1] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[0] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[1] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[2] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[3] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[4] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[5] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[6] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[7] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[8] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[9] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[10] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[11] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[12] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[13] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[14] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[15] -tag __ddr3x64_example_if0_p0 + +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dm[2] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dm[3] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[16] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[17] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[18] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[19] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[20] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[21] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[22] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[23] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[24] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[25] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[26] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[27] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[28] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[29] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[30] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[31] -tag __ddr3x64_example_if0_p0 + +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_p +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_n + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15] + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31] + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[32] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[33] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[34] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[35] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[36] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[37] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[38] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[39] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[40] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[41] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[42] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[43] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[44] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[45] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[46] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[47] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[32] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[33] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[34] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[35] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[36] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[37] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[38] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[39] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[40] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[41] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[42] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[43] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[44] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[45] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[46] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[47] + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[48] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[49] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[50] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[51] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[52] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[53] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[54] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[55] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[56] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[57] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[58] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[59] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[60] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[61] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[62] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[63] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[48] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[49] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[50] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[51] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[52] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[53] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[54] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[55] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[56] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[57] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[58] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[59] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[60] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[61] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[62] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[63] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_p +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cke +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cs_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ras_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cas_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_we_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_reset_n +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_odt + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[14] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[15] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[16] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[17] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[18] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[19] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[20] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[21] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[22] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[23] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[24] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[25] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[26] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[27] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[28] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[29] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[30] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[31] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[32] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[33] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[34] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[35] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[36] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[37] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[38] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[39] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[40] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[41] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[42] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[43] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[44] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[45] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[46] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[47] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[48] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[49] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[50] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[51] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[52] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[53] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[54] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[55] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[56] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[57] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[58] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[59] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[60] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[61] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[62] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[63] + +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[0] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[0] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[1] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[1] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[0] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[1] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[0] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[1] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[2] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[3] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[4] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[5] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[6] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[7] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[8] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[9] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[10] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[11] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[12] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[13] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[14] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[15] -tag __ddr3x64_example_if0_p0 + +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[2] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[2] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[3] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[3] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[2] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[3] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[16] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[17] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[18] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[19] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[20] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[21] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[22] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[23] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[24] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[25] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[26] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[27] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[28] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[29] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[30] -tag __ddr3x64_example_if0_p0 +set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[31] -tag __ddr3x64_example_if0_p0 + +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_fmcjesdadc1|sys_ddr3_cntrl + +set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_addr_cmd_clk +set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_avl_clk +set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_config_clk +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_afi_clk +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_hr_clk + +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[4].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[5].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[6].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[7].read_capture_clk_buffer +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7] +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_mem_stable_n +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_n +set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n + +# ethernet interface + +set_location_assignment PIN_M14 -to eth_rx_clk +set_location_assignment PIN_N14 -to eth_rx_data[0] +set_location_assignment PIN_N15 -to eth_rx_data[1] +set_location_assignment PIN_P15 -to eth_rx_data[2] +set_location_assignment PIN_B9 -to eth_rx_data[3] +set_location_assignment PIN_C9 -to eth_rx_cntrl[4] +set_location_assignment PIN_K18 -to eth_tx_clk_out[5] +set_location_assignment PIN_L18 -to eth_tx_data[0] +set_location_assignment PIN_R11 -to eth_tx_data[1] +set_location_assignment PIN_T11 -to eth_tx_data[2] +set_location_assignment PIN_H9 -to eth_tx_data[3] +set_location_assignment PIN_J9 -to eth_tx_cntrl +set_location_assignment PIN_F7 -to eth_mdc +set_location_assignment PIN_G7 -to eth_mdio_i +set_location_assignment PIN_F9 -to eth_mdio_o +set_location_assignment PIN_G9 -to eth_mdio_t + +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_clk +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_cntrl[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_clk_out[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_cntrl +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdc +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_i +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_o +set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_t + +# leds + +set_location_assignment PIN_M19 -to led_grn[0] +set_location_assignment PIN_L19 -to led_grn[1] +set_location_assignment PIN_K19 -to led_grn[2] +set_location_assignment PIN_J19 -to led_grn[3] +set_location_assignment PIN_K20 -to led_grn[4] +set_location_assignment PIN_J20 -to led_grn[5] +set_location_assignment PIN_T20 -to led_grn[6] +set_location_assignment PIN_R20 -to led_grn[7] +set_location_assignment PIN_N20 -to led_red[0] +set_location_assignment PIN_C15 -to led_red[1] +set_location_assignment PIN_AL28 -to led_red[2] +set_location_assignment PIN_F11 -to led_red[3] +set_location_assignment PIN_AJ31 -to led_red[4] +set_location_assignment PIN_AN34 -to led_red[5] +set_location_assignment PIN_AJ34 -to led_red[6] +set_location_assignment PIN_AK33 -to led_red[7] +set_location_assignment PIN_D6 -to push_buttons[0] +set_location_assignment PIN_C6 -to push_buttons[1] +set_location_assignment PIN_K7 -to push_buttons[2] +set_location_assignment PIN_C8 -to dip_switches[0] +set_location_assignment PIN_D8 -to dip_switches[1] +set_location_assignment PIN_E7 -to dip_switches[2] +set_location_assignment PIN_E6 -to dip_switches[3] +set_location_assignment PIN_G8 -to dip_switches[4] +set_location_assignment PIN_F8 -to dip_switches[5] +set_location_assignment PIN_D15 -to dip_switches[6] +set_location_assignment PIN_G11 -to dip_switches[7] + +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[7] + + +# globals + +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT fmcjesdadc1_sta.tcl +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF + +project_close + +################################################################################ +################################################################################ diff --git a/projects/fmcjesdadc1/a5gt/system_timing.tcl b/projects/fmcjesdadc1/a5gt/system_timing.tcl new file mode 100755 index 000000000..5209aa9e9 --- /dev/null +++ b/projects/fmcjesdadc1/a5gt/system_timing.tcl @@ -0,0 +1,23 @@ +################################################################################ +################################################################################ + +package require ::quartus::flow +project_open fmcjesdadc1 +execute_module -tool fit + +create_timing_netlist +read_sdc fmcjesdadc1.sdc +update_timing_netlist + +report_timing -detail summary -npaths 20 -file timing_summary.rpt +report_timing -detail path_only -npaths 20 -file timing.rpt +report_path -npaths 20 -file timing_paths.rpt +report_sdc -ignored -file timing_sdc.rpt +report_clocks -file timing_clocks.rpt +report_ucp -file timing_ucp.rpt + +check_timing -file timing_design.rpt +create_timing_summary -file timing_design_summary.rpt + +################################################################################ +################################################################################ diff --git a/projects/fmcjesdadc1/a5gt/system_top.v b/projects/fmcjesdadc1/a5gt/system_top.v new file mode 100755 index 000000000..bf4f8107b --- /dev/null +++ b/projects/fmcjesdadc1/a5gt/system_top.v @@ -0,0 +1,372 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module fmcjesdadc1_top ( + + // clock and resets + + sys_clk, + sys_resetn, + + // ddr3 + + ddr3_a, + ddr3_ba, + ddr3_clk_p, + ddr3_clk_n, + ddr3_cke, + ddr3_cs_n, + ddr3_dm, + ddr3_ras_n, + ddr3_cas_n, + ddr3_we_n, + ddr3_reset_n, + ddr3_dq, + ddr3_dqs_p, + ddr3_dqs_n, + ddr3_odt, + ddr3_rzq, + + // ethernet + + eth_rx_clk, + eth_rx_data, + eth_rx_cntrl, + eth_tx_clk_out, + eth_tx_data, + eth_tx_cntrl, + eth_mdc, + eth_mdio_i, + eth_mdio_o, + eth_mdio_t, + + // board gpio + + led_grn, + led_red, + push_buttons, + dip_switches, + + // lane interface + + ref_clk, + rx_data, + rx_sync, + rx_sysref, + + // spi + + spi_csn, + spi_clk, + spi_sdio); + + // clock and resets + + input sys_clk; + input sys_resetn; + + // ddr3 + + output [ 13:0] ddr3_a; + output [ 2:0] ddr3_ba; + output ddr3_clk_p; + output ddr3_clk_n; + output ddr3_cke; + output ddr3_cs_n; + output [ 7:0] ddr3_dm; + output ddr3_ras_n; + output ddr3_cas_n; + output ddr3_we_n; + output ddr3_reset_n; + inout [ 63:0] ddr3_dq; + inout [ 7:0] ddr3_dqs_p; + inout [ 7:0] ddr3_dqs_n; + output ddr3_odt; + input ddr3_rzq; + + // ethernet + + input eth_rx_clk; + input [ 3:0] eth_rx_data; + input eth_rx_cntrl; + output eth_tx_clk_out; + output [ 3:0] eth_tx_data; + output eth_tx_cntrl; + output eth_mdc; + input eth_mdio_i; + output eth_mdio_o; + output eth_mdio_t; + + // board gpio + + output [ 7:0] led_grn; + output [ 7:0] led_red; + input [ 2:0] push_buttons; + input [ 7:0] dip_switches; + + // lane interface + + input ref_clk; + input [ 3:0] rx_data; + output rx_sync; + output rx_sysref; + + // spi + + output spi_csn; + output spi_clk; + inout spi_sdio; + + // internal registers + + reg rx_sysref_m1 = 'd0; + reg rx_sysref_m2 = 'd0; + reg rx_sysref_m3 = 'd0; + reg rx_sysref = 'd0; + + // internal clocks and resets + + wire sys_125m_clk; + wire sys_25m_clk; + wire sys_2m5_clk; + wire eth_tx_clk; + wire rx_clk; + wire adc0_clk; + wire adc1_clk; + + // internal signals + + wire sys_pll_locked_s; + wire eth_tx_reset_s; + wire eth_tx_mode_1g_s; + wire eth_tx_mode_10m_100m_n_s; + wire spi_csn_s; + wire spi_clk_s; + wire spi_mosi_s; + wire spi_miso_s; + wire [ 63:0] adc0_ddata_s; + wire adc0_dsync_s; + wire adc0_dovf_s; + wire adc0_dwr_s; + wire adc0_mon_valid_s; + wire [119:0] adc0_mon_data_s; + wire [ 63:0] adc1_ddata_s; + wire adc1_dsync_s; + wire adc1_dovf_s; + wire adc1_dwr_s; + wire adc1_mon_valid_s; + wire [119:0] adc1_mon_data_s; + wire [ 3:0] rx_ip_sof_s; + wire [127:0] rx_ip_data_s; + wire [127:0] rx_data_s; + wire rx_sw_rstn_s; + wire rx_sysref_s; + wire rx_err_s; + wire rx_ready_s; + wire [ 3:0] rx_rst_state_s; + wire rx_lane_aligned_s; + wire [ 3:0] rx_analog_reset_s; + wire [ 3:0] rx_digital_reset_s; + wire [ 3:0] rx_cdr_locked_s; + wire [ 3:0] rx_cal_busy_s; + wire rx_pll_locked_s; + wire [ 15:0] rx_xcvr_status_s; + + // ethernet transmit clock + + assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk : + (eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk; + + altddio_out #(.width(1)) i_eth_tx_clk_out ( + .aset (1'b0), + .sset (1'b0), + .sclr (1'b0), + .oe (1'b1), + .oe_out (), + .datain_h (1'b1), + .datain_l (1'b0), + .outclocken (1'b1), + .aclr (eth_tx_reset_s), + .outclock (eth_tx_clk), + .dataout (eth_tx_clk_out)); + + assign eth_tx_reset_s = ~sys_pll_locked_s; + + always @(posedge rx_clk) begin + rx_sysref_m1 <= rx_sysref_s; + rx_sysref_m2 <= rx_sysref_m1; + rx_sysref_m3 <= rx_sysref_m2; + rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3; + end + + genvar n; + generate + for (n = 0; n < 4; n = n + 1) begin: g_align_1 + ad_jesd_align i_jesd_align ( + .rx_clk (rx_clk), + .rx_sof (rx_ip_sof_s), + .rx_ip_data (rx_ip_data_s[n*32+31:n*32]), + .rx_data (rx_data_s[n*32+31:n*32])); + end + endgenerate + + assign rx_xcvr_status_s[15:14] = 2'd0; + assign rx_xcvr_status_s[13:13] = rx_ready_s; + assign rx_xcvr_status_s[12:12] = rx_pll_locked_s; + assign rx_xcvr_status_s[11: 8] = rx_rst_state_s; + assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s; + assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s; + + ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst ( + .rx_clk (rx_clk), + .rx_rstn (sys_resetn), + .rx_sw_rstn (rx_sw_rstn_s), + .rx_pll_locked (rx_pll_locked_s), + .rx_cal_busy (rx_cal_busy_s), + .rx_cdr_locked (rx_cdr_locked_s), + .rx_analog_reset (rx_analog_reset_s), + .rx_digital_reset (rx_digital_reset_s), + .rx_ready (rx_ready_s), + .rx_rst_state (rx_rst_state_s)); + + fmcjesdadc1_spi i_fmcjesdadc1_spi ( + .sys_clk (sys_clk), + .spi4_csn (spi_csn_s), + .spi4_clk (spi_clk_s), + .spi4_mosi (spi_mosi_s), + .spi4_miso (spi_miso_s), + .spi3_csn (spi_csn), + .spi3_clk (spi_clk), + .spi3_sdio (spi_sdio)); + + fmcjesdadc1 i_fmcjesdadc1 ( + .sys_clk_clk (sys_clk), + .sys_reset_reset_n (sys_resetn), + .sys_125m_clk_clk (sys_125m_clk), + .sys_25m_clk_clk (sys_25m_clk), + .sys_2m5_clk_clk (sys_2m5_clk), + .sys_pll_locked_export (sys_pll_locked_s), + .sys_ddr3_phy_mem_a (ddr3_a), + .sys_ddr3_phy_mem_ba (ddr3_ba), + .sys_ddr3_phy_mem_ck (ddr3_clk_p), + .sys_ddr3_phy_mem_ck_n (ddr3_clk_n), + .sys_ddr3_phy_mem_cke (ddr3_cke), + .sys_ddr3_phy_mem_cs_n (ddr3_cs_n), + .sys_ddr3_phy_mem_dm (ddr3_dm), + .sys_ddr3_phy_mem_ras_n (ddr3_ras_n), + .sys_ddr3_phy_mem_cas_n (ddr3_cas_n), + .sys_ddr3_phy_mem_we_n (ddr3_we_n), + .sys_ddr3_phy_mem_reset_n (ddr3_reset_n), + .sys_ddr3_phy_mem_dq (ddr3_dq), + .sys_ddr3_phy_mem_dqs (ddr3_dqs_p), + .sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n), + .sys_ddr3_phy_mem_odt (ddr3_odt), + .sys_ddr3_oct_rzqin (ddr3_rzq), + .sys_ethernet_tx_clk_clk (eth_tx_clk), + .sys_ethernet_rx_clk_clk (eth_rx_clk), + .sys_ethernet_status_set_10 (), + .sys_ethernet_status_set_1000 (), + .sys_ethernet_status_eth_mode (eth_tx_mode_1g_s), + .sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s), + .sys_ethernet_rgmii_rgmii_in (eth_rx_data), + .sys_ethernet_rgmii_rgmii_out (eth_tx_data), + .sys_ethernet_rgmii_rx_control (eth_rx_cntrl), + .sys_ethernet_rgmii_tx_control (eth_tx_cntrl), + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_gpio_in_port ({rx_xcvr_status_s, 5'd0, push_buttons, dip_switches}), + .sys_gpio_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}), + .sys_spi_MISO (spi_miso_s), + .sys_spi_MOSI (spi_mosi_s), + .sys_spi_SCLK (spi_clk_s), + .sys_spi_SS_n (spi_csn_s), + .axi_ad9250_0_xcvr_clk_clk (rx_clk), + .axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]), + .axi_ad9250_0_adc_clock_clk (adc0_clk), + .axi_ad9250_0_adc_dma_if_ddata (adc0_ddata_s), + .axi_ad9250_0_adc_dma_if_dsync (adc0_dsync_s), + .axi_ad9250_0_adc_dma_if_dovf (adc0_dovf_s), + .axi_ad9250_0_adc_dma_if_dunf (1'b0), + .axi_ad9250_0_adc_dma_if_dwr (adc0_dwr_s), + .axi_ad9250_0_adc_mon_if_valid (adc0_mon_valid_s), + .axi_ad9250_0_adc_mon_if_data (adc0_mon_data_s), + .axi_dmac_0_fifo_wr_clock_clk (adc0_clk), + .axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s), + .axi_dmac_0_fifo_wr_if_wren (adc0_dwr_s), + .axi_dmac_0_fifo_wr_if_data (adc0_ddata_s), + .axi_dmac_0_fifo_wr_if_sync (adc0_dsync_s), + .axi_ad9250_1_xcvr_clk_clk (rx_clk), + .axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]), + .axi_ad9250_1_adc_clock_clk (adc1_clk), + .axi_ad9250_1_adc_dma_if_ddata (adc1_ddata_s), + .axi_ad9250_1_adc_dma_if_dsync (adc1_dsync_s), + .axi_ad9250_1_adc_dma_if_dovf (adc1_dovf_s), + .axi_ad9250_1_adc_dma_if_dunf (1'b0), + .axi_ad9250_1_adc_dma_if_dwr (adc1_dwr_s), + .axi_ad9250_1_adc_mon_if_valid (adc1_mon_valid_s), + .axi_ad9250_1_adc_mon_if_data (adc1_mon_data_s), + .axi_dmac_1_fifo_wr_clock_clk (adc1_clk), + .axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s), + .axi_dmac_1_fifo_wr_if_wren (adc1_dwr_s), + .axi_dmac_1_fifo_wr_if_data (adc1_ddata_s), + .axi_dmac_1_fifo_wr_if_sync (adc1_dsync_s), + .sys_jesd204b_s1_rx_link_data (rx_ip_data_s), + .sys_jesd204b_s1_rx_link_valid (), + .sys_jesd204b_s1_rx_link_ready (1'b1), + .sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s), + .sys_jesd204b_s1_sysref_export (rx_sysref), + .sys_jesd204b_s1_rx_ferr_export (rx_err_s), + .sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s), + .sys_jesd204b_s1_sync_n_export (rx_sync), + .sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s), + .sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data), + .sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s), + .sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s), + .sys_jesd204b_s1_locked_export (rx_cdr_locked_s), + .sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s), + .sys_jesd204b_s1_ref_clk_clk (ref_clk), + .sys_jesd204b_s1_rx_clk_clk (rx_clk), + .sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v b/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v new file mode 100644 index 000000000..4000907b8 --- /dev/null +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v @@ -0,0 +1,150 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module fmcjesdadc1_spi ( + + // master clock + + sys_clk, + + // 4-wire spi interface + + spi4_csn, + spi4_clk, + spi4_mosi, + spi4_miso, + + // 3-wire spi interface + + spi3_csn, + spi3_clk, + spi3_sdio); + + // parameters + + localparam FMC27X_CPLD = 8'h00; + localparam FMC27X_AD9517 = 8'h84; + localparam FMC27X_AD9250_0 = 8'h80; + localparam FMC27X_AD9250_1 = 8'h81; + localparam FMC27X_AD9129_0 = 8'h82; + localparam FMC27X_AD9129_1 = 8'h83; + + // master clock + + input sys_clk; + + // 4-wire spi interface + + input spi4_csn; + input spi4_clk; + input spi4_mosi; + output spi4_miso; + + // 3-wire spi interface + + output spi3_csn; + output spi3_clk; + inout spi3_sdio; + + // internal registers + + reg spi4_clk_d = 'd0; + reg spi4_csn_d = 'd0; + reg [ 5:0] spi4_clkcnt = 'd0; + reg [ 6:0] spi4_bitcnt = 'd0; + reg [ 7:0] spi4_devid = 'd0; + reg spi4_rwn = 'd0; + reg spi3_enable = 'd0; + + // pass through most of the stuff (no need to change clock or miso or mosi) + + assign spi4_miso = spi3_sdio; + assign spi3_csn = spi4_csn; + assign spi3_clk = spi4_clk; + assign spi3_sdio = ((spi4_csn == 1'b0) && (spi3_enable == 1'b1)) ? 1'bz : spi4_mosi; + + // the spi4 format is a preamble that selects a particular device, so all we need + // to do is collect the first 8 bits, then control the tristate based on the + // device's address and data widths. the details of the spi formats can be found + // in the data sheet of the devices. + + always @(posedge sys_clk) begin + spi4_clk_d <= spi4_clk; + spi4_csn_d <= spi4_csn; + if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin + spi4_clkcnt <= 6'd0; + end else begin + spi4_clkcnt <= spi4_clkcnt + 1'b1; + end + if ((spi4_csn == 1'b1) && (spi4_csn_d == 1'b0)) begin + spi4_bitcnt <= 7'd0; + spi4_devid <= 8'd0; + spi4_rwn <= 1'd0; + end else if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin + spi4_bitcnt <= spi4_bitcnt + 1'b1; + if (spi4_bitcnt < 8) begin + spi4_devid <= {spi4_devid[6:0], spi4_mosi}; + end + if (spi4_bitcnt == 8) begin + spi4_rwn <= spi4_mosi; + end + end + if (spi4_csn == 1'b0) begin + if ((spi4_devid == FMC27X_CPLD) || (spi4_devid == FMC27X_AD9129_0) || + (spi4_devid == FMC27X_AD9129_1)) begin + if ((spi4_bitcnt == 16) && (spi4_clkcnt == 8)) begin + spi3_enable <= spi4_rwn; + end + end else if ((spi4_devid == FMC27X_AD9517) || (spi4_devid == FMC27X_AD9250_0) || + (spi4_devid == FMC27X_AD9250_1)) begin + if ((spi4_bitcnt == 24) && (spi4_clkcnt == 8)) begin + spi3_enable <= spi4_rwn; + end + end + end else begin + spi3_enable <= 1'b0; + end + end + +endmodule + +// *************************************************************************** +// ***************************************************************************