util_clkdiv: set OOC default clock constraints
parent
5dd9cdcdea
commit
0cc07a20c8
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@ -8,6 +8,7 @@ LIBRARY_NAME := util_clkdiv
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XILINX_DEPS += util_clkdiv.v
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XILINX_DEPS += util_clkdiv_constr.xdc
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XILINX_DEPS += util_clkdiv_ooc.ttcl
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XILINX_DEPS += util_clkdiv_ip.tcl
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ALTERA_DEPS += util_clkdiv_alt.v
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@ -4,10 +4,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create util_clkdiv
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adi_ip_files util_clkdiv [list \
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"util_clkdiv_constr.xdc" \
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"util_clkdiv_ooc.ttcl" \
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"util_clkdiv.v" ]
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adi_ip_properties_lite util_clkdiv
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adi_ip_ttcl util_clkdiv "util_clkdiv_ooc.ttcl"
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set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \
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-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]]
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@ -0,0 +1,17 @@
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<: setFileUsedIn { out_of_context synthesis implementation } :>
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<: ;#Component and file information :>
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName $ComponentName :>
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<: setFileExtension "_ooc.xdc" :>
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# This XDC is used only for OOC mode of synthesis, implementation.
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# These are default values for timing driven synthesis during OOC flow.
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# These values will be overwritten during implementation with information
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# from top level.
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create_clock -name clk -period 10 [get_ports clk]
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################################################################################
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