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library: Fix broken parameters 

Fix the broken parameters for the following IP cores: axi_i2s_adi, axi_spdif_tx, util_cpack. Make additional name changes on the local parameters.
main
Istvan Csomortani 2015-08-25 09:19:47 +03:00
parent da315eb6c0
commit 0c3f110bff
6 changed files with 181 additions and 182 deletions
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84
library/axi_i2s_adi/axi_i2s_adi.vhd
View File

@ -19,30 +19,30 @@ entity axi_i2s_adi is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_SLOT_WIDTH : integer := 24;
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
SLOT_WIDTH : integer := 24;
LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_FAMILY : string := "virtex6";
S_AXI_DATA_WIDTH : integer := 32;
S_AXI_ADDRESS_WIDTH : integer := 32;
DEVICE_FAMILY : string := "virtex6";
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_DMA_TYPE : integer := 0;
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1
DMA_TYPE : integer := 0;
NUM_OF_CHANNEL : integer := 1;
HAS_TX : integer := 1;
HAS_RX : integer := 1
);
port
(
-- Serial Data interface
DATA_CLK_I : in std_logic;
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0);
BCLK_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
LRCLK_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
SDATA_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
SDATA_I : in std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
-- AXI Streaming DMA TX interface
S_AXIS_ACLK : in std_logic;
@ -85,17 +85,17 @@ entity axi_i2s_adi is
-- AXI bus interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
@ -113,13 +113,13 @@ architecture Behavioral of axi_i2s_adi is
signal i2s_reset : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_enable : Boolean;
signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal tx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
signal tx_ack : std_logic;
signal tx_stb : std_logic;
signal rx_enable : Boolean;
signal rx_fifo_reset : std_logic;
signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal rx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
signal rx_ack : std_logic;
signal rx_stb : std_logic;
@ -135,7 +135,7 @@ signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8))));
constant FIFO_AWIDTH : integer := integer(ceil(log2(real(NUM_OF_CHANNEL * 8))));
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
@ -175,8 +175,8 @@ begin
end if;
end process;
streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate
tx_fifo : entity axi_streaming_dma_tx_fifo
streaming_dma_tx_gen: if DMA_TYPE = 0 and HAS_TX = 1 generate
tx_fifo : entity axi_streaming_dma_tx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
@ -199,12 +199,12 @@ begin
);
end generate;
no_streaming_dma_tx_gen: if C_DMA_TYPE /= 0 or C_HAS_TX /= 1 generate
no_streaming_dma_tx_gen: if DMA_TYPE /= 0 or HAS_TX /= 1 generate
S_AXIS_TREADY <= '0';
end generate;
streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo
streaming_dma_rx_gen: if DMA_TYPE = 0 and HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
@ -232,7 +232,7 @@ begin
M_AXIS_TDATA(7 downto 0) <= (others => '0');
end generate;
no_streaming_dma_rx_gen: if C_DMA_TYPE /= 0 or C_HAS_RX /= 1 generate
no_streaming_dma_rx_gen: if DMA_TYPE /= 0 or HAS_RX /= 1 generate
M_AXIS_TDATA <= (others => '0');
M_AXIS_TLAST <= '0';
M_AXIS_TVALID <= '0';
@ -241,7 +241,7 @@ begin
pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
pl330_dma_tx_gen: if DMA_TYPE = 1 and HAS_TX = 1 generate
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
tx_fifo: entity pl330_dma_fifo
@ -275,14 +275,14 @@ begin
);
end generate;
no_pl330_dma_tx_gen: if C_DMA_TYPE /= 1 or C_HAS_TX /= 1 generate
no_pl330_dma_tx_gen: if DMA_TYPE /= 1 or HAS_TX /= 1 generate
DMA_REQ_TX_DAREADY <= '0';
DMA_REQ_TX_DRVALID <= '0';
DMA_REQ_TX_DRTYPE <= (others => '0');
DMA_REQ_TX_DRLAST <= '0';
end generate;
pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
pl330_dma_rx_gen: if DMA_TYPE = 1 and HAS_RX = 1 generate
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
rx_fifo: entity pl330_dma_fifo
@ -317,7 +317,7 @@ begin
end generate;
no_pl330_dma_rx_gen: if C_DMA_TYPE /= 1 or C_HAS_RX /= 1 generate
no_pl330_dma_rx_gen: if DMA_TYPE /= 1 or HAS_RX /= 1 generate
DMA_REQ_RX_DAREADY <= '0';
DMA_REQ_RX_DRVALID <= '0';
DMA_REQ_RX_DRTYPE <= (others => '0');
@ -326,12 +326,12 @@ begin
ctrl : entity i2s_controller
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_BCLK_POL => C_BCLK_POL,
C_LRCLK_POL => C_LRCLK_POL,
C_NUM_CH => C_NUM_CH,
C_HAS_TX => C_HAS_TX,
C_HAS_RX => C_HAS_RX
C_SLOT_WIDTH => SLOT_WIDTH,
C_BCLK_POL => BCLK_POL,
C_LRCLK_POL => LRCLK_POL,
C_NUM_CH => NUM_OF_CHANNEL,
C_HAS_TX => HAS_TX,
C_HAS_RX => HAS_RX
)
port map (
clk => S_AXI_ACLK,
@ -368,8 +368,8 @@ begin
ctrlif: entity axi_ctrlif
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
C_NUM_REG => 12
)
port map(
@ -407,8 +407,8 @@ begin
process(rd_addr, I2S_CONTROL_REG, I2S_CLK_CONTROL_REG, PERIOD_LEN_REG, rx_sample, cnt)
begin
case rd_addr is
when 1 => rd_data <= I2S_CONTROL_REG and x"00000003";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 1 => rd_data <= I2S_CONTROL_REG and x"00000003";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
when others => rd_data <= (others => '0');

20
library/axi_i2s_adi/axi_i2s_adi_ip.tcl
View File

@ -74,26 +74,26 @@ adi_add_bus "I2S" "master" \
adi_add_bus_clock "DATA_CLK_I" "i2s"
adi_set_bus_dependency "S_AXIS" "S_AXIS" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
adi_set_bus_dependency "M_AXIS" "M_AXIS" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
adi_set_bus_dependency "DMA_ACK_TX" "DMA_REQ_TX_DA" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_REQ_TX" "DMA_REQ_TX_DR" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_TX_ACLK" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_TX_RSTN" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_ACK_RX" "DMA_REQ_RX_DA" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_REQ_RX" "DMA_REQ_RX_DR" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_RX_ACLK" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_RX_RSTN" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
ipx::save_core [ipx::current_core]

52
library/axi_spdif_tx/axi_spdif_tx.vhd
View File

@ -1,9 +1,9 @@
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Copyright 2011-2013(c) Analog Devices, Inc.
--
--
-- All rights reserved.
--
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
@ -49,10 +49,10 @@ use work.pl330_dma_fifo;
entity axi_spdif_tx is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_FAMILY : string := "virtex6";
C_DMA_TYPE : integer := 0
S_AXI_DATA_WIDTH : integer := 32;
S_AXI_ADDRESS_WIDTH : integer := 32;
DEVICE_FAMILY : string := "virtex6";
DMA_TYPE : integer := 0
);
port (
--SPDIF ports
@ -62,24 +62,24 @@ entity axi_spdif_tx is
--AXI Lite interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
--AXI streaming interface
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
@ -109,8 +109,8 @@ architecture IMP of axi_spdif_tx is
------------------------------------------
-- SPDIF signals
------------------------------------------
signal config_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal chstatus_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal config_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
signal chstatus_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
signal chstat_freq : std_logic_vector(1 downto 0);
signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
@ -140,7 +140,7 @@ begin
enable <= conf_txdata = '1';
fifo_data_ack <= channel and sample_data_ack;
streaming_dma_gen: if C_DMA_TYPE = 0 generate
streaming_dma_gen: if DMA_TYPE = 0 generate
fifo: entity axi_streaming_dma_tx_fifo
generic map (
RAM_ADDR_WIDTH => 3,
@ -162,11 +162,11 @@ begin
);
end generate;
no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate
no_streaming_dma_gen: if DMA_TYPE /= 0 generate
S_AXIS_TREADY <= '0';
end generate;
pl330_dma_gen: if C_DMA_TYPE = 1 generate
pl330_dma_gen: if DMA_TYPE = 1 generate
tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
fifo: entity pl330_dma_fifo
@ -199,7 +199,7 @@ begin
);
end generate;
no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate
no_pl330_dma_gen: if DMA_TYPE /= 1 generate
DMA_REQ_DAREADY <= '0';
DMA_REQ_DRVALID <= '0';
DMA_REQ_DRTYPE <= (others => '0');
@ -228,12 +228,12 @@ begin
chstat_preem <= chstatus_reg(2);
chstat_copy <= chstatus_reg(1);
chstat_audio <= chstatus_reg(0);
-- Transmit encoder
TENC: tx_encoder
TENC: tx_encoder
generic map (
DATA_WIDTH => 16
)
)
port map (
up_clk => S_AXI_ACLK,
data_clk => spdif_data_clk, -- data clock
@ -255,8 +255,8 @@ begin
ctrlif: entity axi_ctrlif
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
C_NUM_REG => 4
)
port map(

10
library/axi_spdif_tx/axi_spdif_tx_ip.tcl
View File

@ -35,16 +35,16 @@ adi_add_bus "DMA_REQ" "master" \
adi_add_bus_clock "DMA_REQ_ACLK" "DMA_REQ:DMA_ACK" "DMA_REQ_RSTN"
adi_set_bus_dependency "S_AXIS" "S_AXIS" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
adi_set_bus_dependency "DMA_ACK" "DMA_REQ_DA" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_REQ" "DMA_REQ_DR" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_ACLK" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_RSTN" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
ipx::save_core [ipx::current_core]

179
library/util_cpack/util_cpack.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -76,91 +76,90 @@ module util_cpack (
// parameters
parameter CHANNEL_DATA_WIDTH = 32;
parameter NUM_OF_CHANNELS = 8;
parameter CHANNEL_DATA_WIDTH = 32;
parameter NUM_OF_CHANNELS = 8;
localparam CH_SCNT = CHANNEL_DATA_WIDTH/16;
localparam SAMPLES_PCHANNEL = CHANNEL_DATA_WIDTH/16;
localparam NUM_OF_CHANNELS_M = 8;
localparam P_DW = NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH;
localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS;
localparam P_SCNT = P_DW/16;
localparam BUS_DATA_WIDTH = NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH;
localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS;
// adc interface
input adc_rst;
input adc_clk;
input adc_enable_0;
input adc_valid_0;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_0;
input adc_enable_1;
input adc_valid_1;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_1;
input adc_enable_2;
input adc_valid_2;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_2;
input adc_enable_3;
input adc_valid_3;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_3;
input adc_enable_4;
input adc_valid_4;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_4;
input adc_enable_5;
input adc_valid_5;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_5;
input adc_enable_6;
input adc_valid_6;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_6;
input adc_enable_7;
input adc_valid_7;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_7;
input adc_rst;
input adc_clk;
input adc_enable_0;
input adc_valid_0;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_0;
input adc_enable_1;
input adc_valid_1;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_1;
input adc_enable_2;
input adc_valid_2;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_2;
input adc_enable_3;
input adc_valid_3;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_3;
input adc_enable_4;
input adc_valid_4;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_4;
input adc_enable_5;
input adc_valid_5;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_5;
input adc_enable_6;
input adc_valid_6;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_6;
input adc_enable_7;
input adc_valid_7;
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_7;
// fifo interface
output adc_valid;
output adc_sync;
output adc_valid;
output adc_sync;
output [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data;
// internal registers
reg adc_valid_d = 'd0;
reg [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_d = 'd0;
reg adc_mux_valid = 'd0;
reg [(NUM_OF_CHANNELS_M-1):0] adc_mux_enable = 'd0;
reg [((CH_SCNT*16*79)-1):0] adc_mux_data = 'd0;
reg adc_valid = 'd0;
reg adc_sync = 'd0;
reg adc_valid_d = 'd0;
reg [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_d = 'd0;
reg adc_mux_valid = 'd0;
reg [(NUM_OF_CHANNELS_M-1):0] adc_mux_enable = 'd0;
reg [((SAMPLES_PCHANNEL*16*79)-1):0] adc_mux_data = 'd0;
reg adc_valid = 'd0;
reg adc_sync = 'd0;
reg [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data = 'd0;
// internal signals
wire [(NUM_OF_CHANNELS_M-1):0] adc_enable_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_valid_s;
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_s;
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_intlv_s;
wire [(CH_SCNT-1):0] adc_mux_valid_s;
wire [(CH_SCNT-1):0] adc_mux_enable_0_s;
wire [(CH_SCNT-1):0] adc_mux_enable_1_s;
wire [(CH_SCNT-1):0] adc_mux_enable_2_s;
wire [(CH_SCNT-1):0] adc_mux_enable_3_s;
wire [(CH_SCNT-1):0] adc_mux_enable_4_s;
wire [(CH_SCNT-1):0] adc_mux_enable_5_s;
wire [(CH_SCNT-1):0] adc_mux_enable_6_s;
wire [(CH_SCNT-1):0] adc_mux_enable_7_s;
wire [((CH_SCNT*16*1)-1):0] adc_mux_data_0_s;
wire [((CH_SCNT*16*2)-1):0] adc_mux_data_1_s;
wire [((CH_SCNT*16*3)-1):0] adc_mux_data_2_s;
wire [((CH_SCNT*16*4)-1):0] adc_mux_data_3_s;
wire [((CH_SCNT*16*5)-1):0] adc_mux_data_4_s;
wire [((CH_SCNT*16*6)-1):0] adc_mux_data_5_s;
wire [((CH_SCNT*16*7)-1):0] adc_mux_data_6_s;
wire [((CH_SCNT*16*8)-1):0] adc_mux_data_7_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_valid_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_sync_s;
wire [(P_DW-1):0] adc_dsf_data_s[(NUM_OF_CHANNELS_M-1):0];
wire [(NUM_OF_CHANNELS_M-1):0] adc_enable_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_valid_s;
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_s;
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_intlv_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_valid_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_0_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_1_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_2_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_3_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_4_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_5_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_6_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_7_s;
wire [((SAMPLES_PCHANNEL*16*1)-1):0] adc_mux_data_0_s;
wire [((SAMPLES_PCHANNEL*16*2)-1):0] adc_mux_data_1_s;
wire [((SAMPLES_PCHANNEL*16*3)-1):0] adc_mux_data_2_s;
wire [((SAMPLES_PCHANNEL*16*4)-1):0] adc_mux_data_3_s;
wire [((SAMPLES_PCHANNEL*16*5)-1):0] adc_mux_data_4_s;
wire [((SAMPLES_PCHANNEL*16*6)-1):0] adc_mux_data_5_s;
wire [((SAMPLES_PCHANNEL*16*7)-1):0] adc_mux_data_6_s;
wire [((SAMPLES_PCHANNEL*16*8)-1):0] adc_mux_data_7_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_valid_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_sync_s;
wire [(BUS_DATA_WIDTH-1):0] adc_dsf_data_s[(NUM_OF_CHANNELS_M-1):0];
// loop variables
genvar n;
genvar n;
// making things a bit easier
@ -199,7 +198,7 @@ module util_cpack (
// interleave data
generate
for (n = 0; n < CH_SCNT; n = n + 1) begin: g_intlv
for (n = 0; n < SAMPLES_PCHANNEL; n = n + 1) begin: g_intlv
assign adc_data_intlv_s[((16*NUM_OF_CHANNELS_M*(n+1))-1):(16*NUM_OF_CHANNELS_M*n)] =
{ adc_data_d[(((CHANNEL_DATA_WIDTH*7)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*7)+(16*n))],
adc_data_d[(((CHANNEL_DATA_WIDTH*6)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*6)+(16*n))],
@ -215,7 +214,7 @@ module util_cpack (
// mux
generate
for (n = 0; n < CH_SCNT; n = n + 1) begin: g_mux
for (n = 0; n < SAMPLES_PCHANNEL; n = n + 1) begin: g_mux
util_cpack_mux i_mux (
.adc_clk (adc_clk),
.adc_valid (adc_valid_d),
@ -253,22 +252,22 @@ module util_cpack (
adc_mux_enable[5] <= & adc_mux_enable_5_s;
adc_mux_enable[6] <= & adc_mux_enable_6_s;
adc_mux_enable[7] <= & adc_mux_enable_7_s;
adc_mux_data[((CH_SCNT*16* 9)-1):(CH_SCNT*16* 1)] <= 'd0;
adc_mux_data[((CH_SCNT*16*19)-1):(CH_SCNT*16*12)] <= 'd0;
adc_mux_data[((CH_SCNT*16*29)-1):(CH_SCNT*16*23)] <= 'd0;
adc_mux_data[((CH_SCNT*16*39)-1):(CH_SCNT*16*34)] <= 'd0;
adc_mux_data[((CH_SCNT*16*49)-1):(CH_SCNT*16*45)] <= 'd0;
adc_mux_data[((CH_SCNT*16*59)-1):(CH_SCNT*16*56)] <= 'd0;
adc_mux_data[((CH_SCNT*16*69)-1):(CH_SCNT*16*67)] <= 'd0;
adc_mux_data[((CH_SCNT*16*79)-1):(CH_SCNT*16*78)] <= 'd0;
adc_mux_data[((CH_SCNT*16* 1)-1):(CH_SCNT*16* 0)] <= adc_mux_data_0_s;
adc_mux_data[((CH_SCNT*16*12)-1):(CH_SCNT*16*10)] <= adc_mux_data_1_s;
adc_mux_data[((CH_SCNT*16*23)-1):(CH_SCNT*16*20)] <= adc_mux_data_2_s;
adc_mux_data[((CH_SCNT*16*34)-1):(CH_SCNT*16*30)] <= adc_mux_data_3_s;
adc_mux_data[((CH_SCNT*16*45)-1):(CH_SCNT*16*40)] <= adc_mux_data_4_s;
adc_mux_data[((CH_SCNT*16*56)-1):(CH_SCNT*16*50)] <= adc_mux_data_5_s;
adc_mux_data[((CH_SCNT*16*67)-1):(CH_SCNT*16*60)] <= adc_mux_data_6_s;
adc_mux_data[((CH_SCNT*16*78)-1):(CH_SCNT*16*70)] <= adc_mux_data_7_s;
adc_mux_data[((SAMPLES_PCHANNEL*16* 9)-1):(SAMPLES_PCHANNEL*16* 1)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*19)-1):(SAMPLES_PCHANNEL*16*12)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*29)-1):(SAMPLES_PCHANNEL*16*23)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*39)-1):(SAMPLES_PCHANNEL*16*34)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*49)-1):(SAMPLES_PCHANNEL*16*45)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*59)-1):(SAMPLES_PCHANNEL*16*56)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*69)-1):(SAMPLES_PCHANNEL*16*67)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*79)-1):(SAMPLES_PCHANNEL*16*78)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16* 1)-1):(SAMPLES_PCHANNEL*16* 0)] <= adc_mux_data_0_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*12)-1):(SAMPLES_PCHANNEL*16*10)] <= adc_mux_data_1_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*23)-1):(SAMPLES_PCHANNEL*16*20)] <= adc_mux_data_2_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*34)-1):(SAMPLES_PCHANNEL*16*30)] <= adc_mux_data_3_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*45)-1):(SAMPLES_PCHANNEL*16*40)] <= adc_mux_data_4_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*56)-1):(SAMPLES_PCHANNEL*16*50)] <= adc_mux_data_5_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*67)-1):(SAMPLES_PCHANNEL*16*60)] <= adc_mux_data_6_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*78)-1):(SAMPLES_PCHANNEL*16*70)] <= adc_mux_data_7_s;
end
// store & fwd
@ -284,7 +283,7 @@ module util_cpack (
.adc_clk (adc_clk),
.adc_valid (adc_mux_valid),
.adc_enable (adc_mux_enable[n]),
.adc_data (adc_mux_data[((CH_SCNT*16*((11*n)+1))-1):(CH_SCNT*16*10*n)]),
.adc_data (adc_mux_data[((SAMPLES_PCHANNEL*16*((11*n)+1))-1):(SAMPLES_PCHANNEL*16*10*n)]),
.adc_dsf_valid (adc_dsf_valid_s[n]),
.adc_dsf_sync (adc_dsf_sync_s[n]),
.adc_dsf_data (adc_dsf_data_s[n]));

18
library/util_cpack/util_cpack_dsf.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -54,9 +54,9 @@ module util_cpack_dsf (
// parameters
parameter CHANNEL_DATA_WIDTH = 32;
parameter NUM_OF_CHANNELS_I = 4;
parameter NUM_OF_CHANNELS_M = 8;
parameter CHANNEL_DATA_WIDTH = 32;
parameter NUM_OF_CHANNELS_I = 4;
parameter NUM_OF_CHANNELS_M = 8;
parameter NUM_OF_CHANNELS_P = 4;
localparam CH_DCNT = NUM_OF_CHANNELS_P - NUM_OF_CHANNELS_I;
@ -93,7 +93,7 @@ module util_cpack_dsf (
wire [(M_WIDTH-1):0] adc_data_s;
// bypass
// bypass
generate
if (NUM_OF_CHANNELS_I == NUM_OF_CHANNELS_P) begin