ad9213_dual_ebz: Add possibility to change order of channels through a GPIO
parent
496b4ec748
commit
0c3ec108aa
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@ -9,3 +9,4 @@ create_clock -period "3.2 ns" -name device_clk [get_ports {rx_d
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set_input_delay -clock {device_clk} 0.2 [get_ports {rx_sysref_a}]
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -from [get_keepers -no_duplicates {i_system_bd|sys_gpio_out|sys_gpio_out|data_out[2]}] -to [get_keepers -no_duplicates {adc_swap_d1}]
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@ -180,11 +180,17 @@ module system_top (
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wire adc_enable_0;
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wire adc_enable_1;
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wire adc_valid;
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wire [ 1:0] ltc_csn;
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wire adc_swap;
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reg adc_valid_d1;
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reg [1023:0] adc_data_d1;
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reg [511:0] adc_data_0_d1;
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reg [511:0] adc_data_1_d1;
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wire [ 1:0] ltc_csn;
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reg [511:0] adc_data_0_swap;
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reg [511:0] adc_data_1_swap;
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reg adc_swap_d1;
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reg adc_swap_d2;
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// motherboard-gpio
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@ -195,6 +201,7 @@ module system_top (
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// assignments
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assign adc_swap = gpio_o[34];
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assign ad9213_a_rst = gpio_o[32];
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assign ad9213_b_rst = gpio_o[33];
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assign gpio_i[63:32] = gpio_o[63:32];
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@ -233,10 +240,21 @@ module system_top (
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genvar i;
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for (i = 0; i < 512; i = i + 16) begin
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assign adc_data[(2*i)+31:(2*i)] ={adc_data_1[i+15:i],adc_data_0[i+15:i]};
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assign adc_data[(2*i)+31:(2*i)] ={adc_data_1_swap[i+15:i],adc_data_0_swap[i+15:i]};
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end
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always @(posedge rx_device_clk_0) begin
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adc_swap_d1 <= adc_swap;
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adc_swap_d2 <= adc_swap_d1;
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if (adc_swap_d2 == 1'b0) begin
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adc_data_0_swap <= adc_data_0;
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adc_data_1_swap <= adc_data_1;
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end else begin
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adc_data_0_swap <= adc_data_1;
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adc_data_1_swap <= adc_data_0;
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end
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adc_data_0_d1 <= adc_data_0;
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adc_data_1_d1 <= adc_data_1;
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