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a10gx: Add a Avalon Pipeline Bridge between EMIF and DMA's

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Istvan Csomortani 2020-02-20 13:58:59 +00:00 committed by Adrian Costina
parent 0c7d85ac87
commit 0b51c474a1
1 changed files with 17 additions and 2 deletions
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19
projects/common/a10gx/a10gx_system_qsys.tcl
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@ -240,8 +240,23 @@ proc ad_cpu_interconnect {m_base m_port} {
proc ad_dma_interconnect {m_port} { proc ad_dma_interconnect {m_port} {
add_connection ${m_port} sys_ddr3_cntrl.ctrl_amm_0 set avm_bridge ""
set_connection_parameter_value ${m_port}/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0} append avm_bridge [lindex [split $m_port "."] 0] "_bridge"
set if_name [lindex [split $m_port "."] 1]
## Instantiate an Avalon Pipeline Bridge, in order to isolate the AXI to Avalon
## adapters from the main interconnect
add_instance ${avm_bridge} altera_avalon_mm_bridge
set_instance_parameter_value ${avm_bridge} {SYNC_RESET} {1}
set_instance_parameter_value ${avm_bridge} {DATA_WIDTH} {128}
set_instance_parameter_value ${avm_bridge} {USE_AUTO_ADDRESS_WIDTH} {1}
add_connection sys_clk.clk ${avm_bridge}.clk
add_connection sys_clk.clk_reset ${avm_bridge}.reset
add_connection ${m_port} ${avm_bridge}.s0
add_connection ${avm_bridge}.m0 sys_ddr3_cntrl.ctrl_amm_0
set_connection_parameter_value ${avm_bridge}.m0/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0}
} }
# common dma interfaces # common dma interfaces