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jesd204:up_common: Move cfg_links_disable to 0x086 address space

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Istvan Csomortani 2018-04-04 09:50:18 +01:00 committed by István Csomortáni
parent 05dbe8f42f
commit 0b20dbc2c9
3 changed files with 13 additions and 21 deletions
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5
library/jesd204/axi_jesd204_common/jesd204_up_common.v
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@ -229,7 +229,6 @@ always @(*) begin
/* 0x32-0x34 reserver for future use */
12'h080: up_rdata <= up_cfg_lanes_disable;
12'h081: up_rdata <= up_cfg_links_disable;
/* 0x82-0x83 reserved for future lane disable bits (max 128 lanes) */
12'h084: up_rdata <= {
/* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */
@ -242,7 +241,6 @@ always @(*) begin
/* 01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
/* 00 */ up_cfg_disable_scrambler /* Disable scrambler */
};
12'h086: up_rdata <= up_cfg_links_disable;
/* 0x87-0x8f reserved for future use */
@ -297,9 +295,6 @@ always @(posedge up_clk) begin
12'h080: begin
up_cfg_lanes_disable <= up_wdata[NUM_LANES-1:0];
end
12'h081: begin
up_cfg_links_disable <= up_wdata[NUM_LINKS-1:0];
end
12'h084: begin
up_cfg_octets_per_frame <= up_wdata[23:16];
up_cfg_beats_per_multiframe <= up_wdata[9:DATA_PATH_WIDTH];

19
library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
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@ -79,17 +79,14 @@ reg up_ctrl_manual_sync_request = 1'b0;
wire [1:0] up_status_state;
wire [NUM_LINKS-1:0] up_status_sync;
genvar j;
generate
for (j=0; j<NUM_LINKS; j=j+1) begin : SYNC_CDC
sync_bits i_cdc_sync (
.in(core_status_sync[j]),
.out_clk(up_clk),
.out_resetn(1'b1),
.out(up_status_sync[j])
);
end
endgenerate
sync_bits #(
.NUM_OF_BITS (NUM_LINKS))
i_cdc_sync (
.in(core_status_sync),
.out_clk(up_clk),
.out_resetn(1'b1),
.out(up_status_sync)
);
sync_data #(
.NUM_OF_BITS(2)

10
library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
View File

@ -240,16 +240,16 @@ module axi_jesd204_tx_tb;
write_reg_and_update('h200, {NUM_LANES{1'b1}});
check_all_registers();
/* Check links disable */
write_reg_and_update('h204, {NUM_LANES{1'b1}});
check_all_registers();
/* Check JESD common config */
write_reg_and_update('h210, 32'hff03ff);
check_all_registers();
write_reg_and_update('h214, 32'h03);
check_all_registers();
/* Check links disable */
write_reg_and_update('h218, {NUM_LINKS{1'b1}});
check_all_registers();
/* Check JESD TX configuration */
write_reg_and_update('h240, 32'h07);
check_all_registers();
@ -294,9 +294,9 @@ module axi_jesd204_tx_tb;
/* Should be read-only when core is out of reset */
invert_register('h200);
invert_register('h204);
invert_register('h210);
invert_register('h214);
invert_register('h218);
invert_register('h240);
invert_register('h244);
for (i = 0; i < NUM_LANES; i = i + 1) begin