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fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints

main
Adrian Costina 2014-11-07 13:45:15 +02:00
parent 2d9a529ab8
commit 0ade2a5f67
5 changed files with 175 additions and 141 deletions
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186
projects/fmcomms5/common/fmcomms5_bd.tcl
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@ -31,31 +31,38 @@ set tx_frame_out_1_n [create_bd_port -dir O tx_frame_out_1_n]
set tx_data_out_1_p [create_bd_port -dir O -from 5 -to 0 tx_data_out_1_p]
set tx_data_out_1_n [create_bd_port -dir O -from 5 -to 0 tx_data_out_1_n]
set sys_100m_resetn [create_bd_port -dir O sys_100m_resetn]
set sys_100m_clk [create_bd_port -dir O sys_100m_clk]
set sys_100m_resetn [create_bd_port -dir O sys_100m_resetn]
set sys_100m_clk [create_bd_port -dir O sys_100m_clk]
if {$sys_zynq == 0} {
set gpio_i [create_bd_port -dir I -from 32 -to 0 gpio_i]
set gpio_o [create_bd_port -dir O -from 32 -to 0 gpio_o]
set gpio_t [create_bd_port -dir O -from 32 -to 0 gpio_t]
set gpio_t [create_bd_port -dir O -from 32 -to 0 gpio_t]
}
if {$sys_zynq == 1} {
if {$sys_zynq == 1} {
set spi_csn_0_i [create_bd_port -dir I spi_csn_0_i]
set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o]
} else {
set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o]
}
set spi_sclk_i [create_bd_port -dir I spi_sclk_i]
set spi_sclk_o [create_bd_port -dir O spi_sclk_o]
set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
set spi_miso_i [create_bd_port -dir I spi_miso_i]
# interrupts
set fmcomms5_gpio_irq [create_bd_port -dir O fmcomms5_gpio_irq]
set ad9361_adc_dma_irq [create_bd_port -dir O ad9361_adc_dma_irq]
set ad9361_dac_dma_irq [create_bd_port -dir O ad9361_dac_dma_irq]
set fmcomms5_spi_irq [create_bd_port -dir O fmcomms5_spi_irq]
# instances
set axi_ad9361_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_0]
@ -72,7 +79,7 @@ set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_dac_dma
@ -97,26 +104,26 @@ set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma
if {$sys_zynq == 1} {
if {$sys_zynq == 1} {
set axi_ad9361_adc_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_adc_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_adc_dma_interconnect
}
if {$sys_zynq == 0} {
set axi_fmcomms2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_fmcomms2_spi]
set axi_fmcomms2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms2_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms2_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_fmcomms2_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms2_spi
}
}
if {$sys_zynq == 0} {
set axi_fmcomms2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_fmcomms2_gpio]
set_property -dict [list CONFIG.C_IS_DUAL {0}] $axi_fmcomms2_gpio
set_property -dict [list CONFIG.C_GPIO_WIDTH {17}] $axi_fmcomms2_gpio
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_fmcomms2_gpio
}
}
set util_adc_pack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_0]
set util_dac_unpack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack_0]
@ -131,7 +138,7 @@ if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
}
if {$sys_zynq == 1} {
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
@ -149,41 +156,41 @@ if {$sys_zynq == 1} {
# connections (spi)
if {$sys_zynq == 0} {
connect_bd_net -net spi_csn_i [get_bd_pins axi_fmcomms2_spi/ss_i] [get_bd_ports spi_csn_i]
connect_bd_net -net spi_csn_o [get_bd_pins axi_fmcomms2_spi/ss_o] [get_bd_ports spi_csn_o]
connect_bd_net -net spi_sclk_i [get_bd_pins axi_fmcomms2_spi/sck_i] [get_bd_ports spi_sclk_i]
connect_bd_net -net spi_sclk_o [get_bd_pins axi_fmcomms2_spi/sck_o] [get_bd_ports spi_sclk_o]
connect_bd_net -net spi_mosi_i [get_bd_pins axi_fmcomms2_spi/io0_i] [get_bd_ports spi_mosi_i]
connect_bd_net -net spi_mosi_o [get_bd_pins axi_fmcomms2_spi/io0_o] [get_bd_ports spi_mosi_o]
connect_bd_net -net spi_miso_i [get_bd_pins axi_fmcomms2_spi/io1_i] [get_bd_ports spi_miso_i]
connect_bd_net -net spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In7]
} else {
connect_bd_net -net spi_csn_0_i [get_bd_pins sys_ps7/SPI0_SS_I] [get_bd_ports spi_csn_0_i]
connect_bd_net -net spi_csn_0_o [get_bd_pins sys_ps7/SPI0_SS_O] [get_bd_ports spi_csn_0_o]
connect_bd_net -net spi_csn_1_o [get_bd_pins sys_ps7/SPI0_SS1_O] [get_bd_ports spi_csn_1_o]
connect_bd_net -net spi_csn_2_o [get_bd_pins sys_ps7/SPI0_SS2_O] [get_bd_ports spi_csn_2_o]
connect_bd_net -net spi_sclk_i [get_bd_pins sys_ps7/SPI0_SCLK_I] [get_bd_ports spi_sclk_i]
connect_bd_net -net spi_sclk_o [get_bd_pins sys_ps7/SPI0_SCLK_O] [get_bd_ports spi_sclk_o]
connect_bd_net -net spi_mosi_i [get_bd_pins sys_ps7/SPI0_MOSI_I] [get_bd_ports spi_mosi_i]
connect_bd_net -net spi_mosi_o [get_bd_pins sys_ps7/SPI0_MOSI_O] [get_bd_ports spi_mosi_o]
connect_bd_net -net spi_miso_i [get_bd_pins sys_ps7/SPI0_MISO_I] [get_bd_ports spi_miso_i]
connect_bd_net -net spi_csn_i [get_bd_pins axi_fmcomms2_spi/ss_i] [get_bd_ports spi_csn_i]
connect_bd_net -net spi_csn_o [get_bd_pins axi_fmcomms2_spi/ss_o] [get_bd_ports spi_csn_o]
connect_bd_net -net spi_sclk_i [get_bd_pins axi_fmcomms2_spi/sck_i] [get_bd_ports spi_sclk_i]
connect_bd_net -net spi_sclk_o [get_bd_pins axi_fmcomms2_spi/sck_o] [get_bd_ports spi_sclk_o]
connect_bd_net -net spi_mosi_i [get_bd_pins axi_fmcomms2_spi/io0_i] [get_bd_ports spi_mosi_i]
connect_bd_net -net spi_mosi_o [get_bd_pins axi_fmcomms2_spi/io0_o] [get_bd_ports spi_mosi_o]
connect_bd_net -net spi_miso_i [get_bd_pins axi_fmcomms2_spi/io1_i] [get_bd_ports spi_miso_i]
connect_bd_net -net spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_ports fmcomms5_spi_irq]
} else {
connect_bd_net -net spi_csn_0_i [get_bd_pins sys_ps7/SPI0_SS_I] [get_bd_ports spi_csn_0_i]
connect_bd_net -net spi_csn_0_o [get_bd_pins sys_ps7/SPI0_SS_O] [get_bd_ports spi_csn_0_o]
connect_bd_net -net spi_csn_1_o [get_bd_pins sys_ps7/SPI0_SS1_O] [get_bd_ports spi_csn_1_o]
connect_bd_net -net spi_csn_2_o [get_bd_pins sys_ps7/SPI0_SS2_O] [get_bd_ports spi_csn_2_o]
connect_bd_net -net spi_sclk_i [get_bd_pins sys_ps7/SPI0_SCLK_I] [get_bd_ports spi_sclk_i]
connect_bd_net -net spi_sclk_o [get_bd_pins sys_ps7/SPI0_SCLK_O] [get_bd_ports spi_sclk_o]
connect_bd_net -net spi_mosi_i [get_bd_pins sys_ps7/SPI0_MOSI_I] [get_bd_ports spi_mosi_i]
connect_bd_net -net spi_mosi_o [get_bd_pins sys_ps7/SPI0_MOSI_O] [get_bd_ports spi_mosi_o]
connect_bd_net -net spi_miso_i [get_bd_pins sys_ps7/SPI0_MISO_I] [get_bd_ports spi_miso_i]
}
# connections (gpio)
if {$sys_zynq == 0} {
connect_bd_net -net gpio_i [get_bd_pins axi_fmcomms2_gpio/gpio_io_i] [get_bd_ports gpio_i]
connect_bd_net -net gpio_o [get_bd_pins axi_fmcomms2_gpio/gpio_io_o] [get_bd_ports gpio_o]
connect_bd_net -net gpio_t [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] [get_bd_ports gpio_t]
connect_bd_net -net gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In8]
connect_bd_net -net gpio_i [get_bd_pins axi_fmcomms2_gpio/gpio_io_i] [get_bd_ports gpio_i]
connect_bd_net -net gpio_o [get_bd_pins axi_fmcomms2_gpio/gpio_io_o] [get_bd_ports gpio_o]
connect_bd_net -net gpio_t [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] [get_bd_ports gpio_t]
connect_bd_net -net gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_ports fmcomms5_gpio_irq]
}
# connections (ad9361)
connect_bd_net -net sys_100m_resetn [get_bd_ports sys_100m_resetn]
connect_bd_net -net sys_100m_clk [get_bd_ports sys_100m_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361_0/delay_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361_1/delay_clk]
connect_bd_net -net sys_100m_resetn [get_bd_ports sys_100m_resetn]
connect_bd_net -net sys_100m_clk [get_bd_ports sys_100m_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361_0/delay_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361_1/delay_clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_0/l_clk]
connect_bd_net -net axi_ad9361_1_clk [get_bd_pins axi_ad9361_1/l_clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_0/clk]
@ -248,44 +255,44 @@ connect_bd_net -net axi_ad9361_1_adc_data_q1 [get_bd_pins axi_ad9361_1/adc_
connect_bd_net -net axi_ad9361_0_dvalid [get_bd_pins util_adc_pack_0/dvalid] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en]
connect_bd_net -net axi_ad9361_0_dsync [get_bd_pins util_adc_pack_0/dsync] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9361_adc_ddata [get_bd_pins util_adc_pack_0/ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din]
connect_bd_net -net axi_ad9361_0_dac_enable_0 [get_bd_pins axi_ad9361_0/dac_enable_i0] [get_bd_pins util_dac_unpack_0/dac_enable_00]
connect_bd_net -net axi_ad9361_0_dac_valid_0 [get_bd_pins axi_ad9361_0/dac_valid_i0] [get_bd_pins util_dac_unpack_0/dac_valid_00]
connect_bd_net -net axi_ad9361_0_dac_data_0 [get_bd_pins axi_ad9361_0/dac_data_i0] [get_bd_pins util_dac_unpack_0/dac_data_00]
connect_bd_net -net axi_ad9361_0_dac_enable_1 [get_bd_pins axi_ad9361_0/dac_enable_q0] [get_bd_pins util_dac_unpack_0/dac_enable_01]
connect_bd_net -net axi_ad9361_0_dac_valid_1 [get_bd_pins axi_ad9361_0/dac_valid_q0] [get_bd_pins util_dac_unpack_0/dac_valid_01]
connect_bd_net -net axi_ad9361_0_dac_data_1 [get_bd_pins axi_ad9361_0/dac_data_q0] [get_bd_pins util_dac_unpack_0/dac_data_01]
connect_bd_net -net axi_ad9361_0_dac_enable_2 [get_bd_pins axi_ad9361_0/dac_enable_i1] [get_bd_pins util_dac_unpack_0/dac_enable_02]
connect_bd_net -net axi_ad9361_0_dac_valid_2 [get_bd_pins axi_ad9361_0/dac_valid_i1] [get_bd_pins util_dac_unpack_0/dac_valid_02]
connect_bd_net -net axi_ad9361_0_dac_data_2 [get_bd_pins axi_ad9361_0/dac_data_i1] [get_bd_pins util_dac_unpack_0/dac_data_02]
connect_bd_net -net axi_ad9361_0_dac_enable_3 [get_bd_pins axi_ad9361_0/dac_enable_q1] [get_bd_pins util_dac_unpack_0/dac_enable_03]
connect_bd_net -net axi_ad9361_0_dac_valid_3 [get_bd_pins axi_ad9361_0/dac_valid_q1] [get_bd_pins util_dac_unpack_0/dac_valid_03]
connect_bd_net -net axi_ad9361_0_dac_data_3 [get_bd_pins axi_ad9361_0/dac_data_q1] [get_bd_pins util_dac_unpack_0/dac_data_03]
connect_bd_net -net axi_ad9361_1_dac_enable_0 [get_bd_pins axi_ad9361_1/dac_enable_i0] [get_bd_pins util_dac_unpack_0/dac_enable_04]
connect_bd_net -net axi_ad9361_1_dac_valid_0 [get_bd_pins axi_ad9361_1/dac_valid_i0] [get_bd_pins util_dac_unpack_0/dac_valid_04]
connect_bd_net -net axi_ad9361_1_dac_data_0 [get_bd_pins axi_ad9361_1/dac_data_i0] [get_bd_pins util_dac_unpack_0/dac_data_04]
connect_bd_net -net axi_ad9361_1_dac_enable_1 [get_bd_pins axi_ad9361_1/dac_enable_q0] [get_bd_pins util_dac_unpack_0/dac_enable_05]
connect_bd_net -net axi_ad9361_1_dac_valid_1 [get_bd_pins axi_ad9361_1/dac_valid_q0] [get_bd_pins util_dac_unpack_0/dac_valid_05]
connect_bd_net -net axi_ad9361_1_dac_data_1 [get_bd_pins axi_ad9361_1/dac_data_q0] [get_bd_pins util_dac_unpack_0/dac_data_05]
connect_bd_net -net axi_ad9361_1_dac_enable_2 [get_bd_pins axi_ad9361_1/dac_enable_i1] [get_bd_pins util_dac_unpack_0/dac_enable_06]
connect_bd_net -net axi_ad9361_1_dac_valid_2 [get_bd_pins axi_ad9361_1/dac_valid_i1] [get_bd_pins util_dac_unpack_0/dac_valid_06]
connect_bd_net -net axi_ad9361_1_dac_data_2 [get_bd_pins axi_ad9361_1/dac_data_i1] [get_bd_pins util_dac_unpack_0/dac_data_06]
connect_bd_net -net axi_ad9361_1_dac_enable_3 [get_bd_pins axi_ad9361_1/dac_enable_q1] [get_bd_pins util_dac_unpack_0/dac_enable_07]
connect_bd_net -net axi_ad9361_1_dac_valid_3 [get_bd_pins axi_ad9361_1/dac_valid_q1] [get_bd_pins util_dac_unpack_0/dac_valid_07]
connect_bd_net -net axi_ad9361_1_dac_data_3 [get_bd_pins axi_ad9361_1/dac_data_q1] [get_bd_pins util_dac_unpack_0/dac_data_07]
connect_bd_net -net axi_ad9361_0_dac_enable_0 [get_bd_pins axi_ad9361_0/dac_enable_i0] [get_bd_pins util_dac_unpack_0/dac_enable_00]
connect_bd_net -net axi_ad9361_0_dac_valid_0 [get_bd_pins axi_ad9361_0/dac_valid_i0] [get_bd_pins util_dac_unpack_0/dac_valid_00]
connect_bd_net -net axi_ad9361_0_dac_data_0 [get_bd_pins axi_ad9361_0/dac_data_i0] [get_bd_pins util_dac_unpack_0/dac_data_00]
connect_bd_net -net axi_ad9361_0_dac_enable_1 [get_bd_pins axi_ad9361_0/dac_enable_q0] [get_bd_pins util_dac_unpack_0/dac_enable_01]
connect_bd_net -net axi_ad9361_0_dac_valid_1 [get_bd_pins axi_ad9361_0/dac_valid_q0] [get_bd_pins util_dac_unpack_0/dac_valid_01]
connect_bd_net -net axi_ad9361_0_dac_data_1 [get_bd_pins axi_ad9361_0/dac_data_q0] [get_bd_pins util_dac_unpack_0/dac_data_01]
connect_bd_net -net axi_ad9361_0_dac_enable_2 [get_bd_pins axi_ad9361_0/dac_enable_i1] [get_bd_pins util_dac_unpack_0/dac_enable_02]
connect_bd_net -net axi_ad9361_0_dac_valid_2 [get_bd_pins axi_ad9361_0/dac_valid_i1] [get_bd_pins util_dac_unpack_0/dac_valid_02]
connect_bd_net -net axi_ad9361_0_dac_data_2 [get_bd_pins axi_ad9361_0/dac_data_i1] [get_bd_pins util_dac_unpack_0/dac_data_02]
connect_bd_net -net axi_ad9361_0_dac_enable_3 [get_bd_pins axi_ad9361_0/dac_enable_q1] [get_bd_pins util_dac_unpack_0/dac_enable_03]
connect_bd_net -net axi_ad9361_0_dac_valid_3 [get_bd_pins axi_ad9361_0/dac_valid_q1] [get_bd_pins util_dac_unpack_0/dac_valid_03]
connect_bd_net -net axi_ad9361_0_dac_data_3 [get_bd_pins axi_ad9361_0/dac_data_q1] [get_bd_pins util_dac_unpack_0/dac_data_03]
connect_bd_net -net axi_ad9361_1_dac_enable_0 [get_bd_pins axi_ad9361_1/dac_enable_i0] [get_bd_pins util_dac_unpack_0/dac_enable_04]
connect_bd_net -net axi_ad9361_1_dac_valid_0 [get_bd_pins axi_ad9361_1/dac_valid_i0] [get_bd_pins util_dac_unpack_0/dac_valid_04]
connect_bd_net -net axi_ad9361_1_dac_data_0 [get_bd_pins axi_ad9361_1/dac_data_i0] [get_bd_pins util_dac_unpack_0/dac_data_04]
connect_bd_net -net axi_ad9361_1_dac_enable_1 [get_bd_pins axi_ad9361_1/dac_enable_q0] [get_bd_pins util_dac_unpack_0/dac_enable_05]
connect_bd_net -net axi_ad9361_1_dac_valid_1 [get_bd_pins axi_ad9361_1/dac_valid_q0] [get_bd_pins util_dac_unpack_0/dac_valid_05]
connect_bd_net -net axi_ad9361_1_dac_data_1 [get_bd_pins axi_ad9361_1/dac_data_q0] [get_bd_pins util_dac_unpack_0/dac_data_05]
connect_bd_net -net axi_ad9361_1_dac_enable_2 [get_bd_pins axi_ad9361_1/dac_enable_i1] [get_bd_pins util_dac_unpack_0/dac_enable_06]
connect_bd_net -net axi_ad9361_1_dac_valid_2 [get_bd_pins axi_ad9361_1/dac_valid_i1] [get_bd_pins util_dac_unpack_0/dac_valid_06]
connect_bd_net -net axi_ad9361_1_dac_data_2 [get_bd_pins axi_ad9361_1/dac_data_i1] [get_bd_pins util_dac_unpack_0/dac_data_06]
connect_bd_net -net axi_ad9361_1_dac_enable_3 [get_bd_pins axi_ad9361_1/dac_enable_q1] [get_bd_pins util_dac_unpack_0/dac_enable_07]
connect_bd_net -net axi_ad9361_1_dac_valid_3 [get_bd_pins axi_ad9361_1/dac_valid_q1] [get_bd_pins util_dac_unpack_0/dac_valid_07]
connect_bd_net -net axi_ad9361_1_dac_data_3 [get_bd_pins axi_ad9361_1/dac_data_q1] [get_bd_pins util_dac_unpack_0/dac_data_07]
connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins util_dac_unpack_0/dma_rd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en]
connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9361_fifo_valid [get_bd_pins util_dac_unpack_0/fifo_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_ports ad9361_adc_dma_irq]
connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_ports ad9361_dac_dma_irq]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9361_0/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9361_dac_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9361_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9361_0/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9361_dac_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9361_1/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
@ -293,19 +300,19 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sy
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_0/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_adc_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_dac_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_1/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_1/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_0/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_1/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_0/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_1/s_axi_aresetn]
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_fmcomms2_spi/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_fmcomms2_gpio/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_fmcomms2_gpio/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcomms2_spi/s_axi_aclk]
@ -315,11 +322,11 @@ if {$sys_zynq == 0} {
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcomms2_spi/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcomms2_gpio/s_axi_aresetn]
}
}
# memory interconnects share the same clock (fclk2)
if {$sys_zynq == 1} {
if {$sys_zynq == 1} {
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
}
@ -348,25 +355,26 @@ if {$sys_zynq == 0} {
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aresetn]
connect_bd_intf_net -intf_net axi_ad9361_adc_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9361_adc_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_ad9361_adc_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9361_adc_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn]
}
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn]
}
if {$xl_board eq "zc702"} {
# ila (adc) master
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_0]
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc_0]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_0
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_adc_0
@ -380,7 +388,8 @@ if {$xl_board eq "zc702"} {
# ila (adc) master
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_0]
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc_0]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_0
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {62}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {112}] $ila_adc_0
@ -388,7 +397,7 @@ if {$xl_board eq "zc702"} {
set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE4_WIDTH {128}] $ila_adc_0
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_0
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins ila_adc_0/clk]
connect_bd_net -net axi_ad9361_0_dev_l_dbg_data [get_bd_pins axi_ad9361_0/dev_l_dbg_data] [get_bd_pins ila_adc_0/probe0]
@ -399,13 +408,14 @@ if {$xl_board eq "zc702"} {
# ila (adc) slave
set ila_adc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_1]
set ila_adc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc_1]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_1
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_adc_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {62}] $ila_adc_1
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_1
connect_bd_net -net axi_ad9361_1_clk [get_bd_pins ila_adc_1/clk]
connect_bd_net -net axi_ad9361_1_dev_l_dbg_data [get_bd_pins axi_ad9361_1/dev_l_dbg_data] [get_bd_pins ila_adc_1/probe0]
connect_bd_net -net axi_ad9361_1_dev_l_dbg_data [get_bd_pins axi_ad9361_1/dev_l_dbg_data] [get_bd_pins ila_adc_1/probe0]
}
# address map
@ -413,7 +423,7 @@ if {$xl_board eq "zc702"} {
create_bd_addr_seg -range 0x00010000 -offset 0x79020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_0/s_axi/axi_lite] SEG_data_ad9361_0
create_bd_addr_seg -range 0x00010000 -offset 0x7C420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_dac_dma/s_axi/axi_lite] SEG_data_ad9361_0_dac_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7C400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_adc_dma/s_axi/axi_lite] SEG_data_ad9361_0_adc_dma
create_bd_addr_seg -range 0x00010000 -offset 0x79040000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_1/s_axi/axi_lite] SEG_data_ad9361_1
create_bd_addr_seg -range 0x00010000 -offset 0x79040000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_1/s_axi/axi_lite] SEG_data_ad9361_1
if {$sys_zynq == 0} {
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcomms2_spi/axi_lite/Reg] SEG_data_fmcomms2_spi
@ -423,7 +433,7 @@ if {$sys_zynq == 0} {
if {$sys_zynq == 0} {
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
} else {
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
}

7
projects/fmcomms5/zc702/system_constr.xdc
View File

@ -133,10 +133,3 @@ set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS25} [get_ports gpio_ca
create_clock -name rx_0_clk -period 5.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 5.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name ps7_clk_2 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]
set_clock_groups -asynchronous -group {ad9361_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_clock_groups -asynchronous -group {ps7_clk_2}

65
projects/fmcomms5/zc702/system_top.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -114,8 +114,8 @@ module system_top (
tx_frame_out_1_p,
tx_frame_out_1_n,
tx_data_out_1_p,
tx_data_out_1_n,
gpio_status_1,
tx_data_out_1_n,
gpio_status_1,
gpio_ctl_1,
gpio_en_agc_1,
gpio_resetb_1,
@ -151,27 +151,27 @@ module system_top (
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [ 53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [ 15:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [ 15:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_clk_in_0_p;
input rx_clk_in_0_n;
input rx_frame_in_0_p;
@ -187,7 +187,7 @@ module system_top (
inout [ 7:0] gpio_status_0;
inout [ 3:0] gpio_ctl_0;
inout gpio_en_agc_0;
output mcs_sync;
output mcs_sync;
inout gpio_resetb_0;
inout gpio_enable_0;
inout gpio_txnrx_0;
@ -197,7 +197,7 @@ module system_top (
inout gpio_calsw_2_0;
inout gpio_ad5355_rfen;
inout gpio_ad5355_lock;
input rx_clk_in_1_p;
input rx_clk_in_1_n;
input rx_frame_in_1_p;
@ -209,7 +209,7 @@ module system_top (
output tx_frame_out_1_p;
output tx_frame_out_1_n;
output [ 5:0] tx_data_out_1_p;
output [ 5:0] tx_data_out_1_n;
output [ 5:0] tx_data_out_1_n;
inout [ 7:0] gpio_status_1;
inout [ 3:0] gpio_ctl_1;
inout gpio_en_agc_1;
@ -220,16 +220,16 @@ module system_top (
inout gpio_debug_4_1;
inout gpio_calsw_3_1;
inout gpio_calsw_4_1;
output spi_ad9361_0;
output spi_ad9361_1;
output spi_ad5355;
output spi_clk;
output spi_mosi;
input spi_miso;
input spi_miso;
input ref_clk_p;
input ref_clk_n;
input ref_clk_n;
// internal registers
@ -245,6 +245,7 @@ module system_top (
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 63:0] gpio_t;
wire [15:0] ps_intrs;
wire gpio_open_45_45;
wire gpio_open_44_44;
@ -335,6 +336,24 @@ module system_top (
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ad9361_dac_dma_irq (ps_intrs[12]),
.ad9361_adc_dma_irq (ps_intrs[13]),
.fmcomms5_gpio_irq(),
.fmcomms5_spi_irq(),
.rx_clk_in_0_n (rx_clk_in_0_n),
.rx_clk_in_0_p (rx_clk_in_0_p),
.rx_clk_in_1_n (rx_clk_in_1_n),
@ -346,12 +365,12 @@ module system_top (
.rx_frame_in_0_n (rx_frame_in_0_n),
.rx_frame_in_0_p (rx_frame_in_0_p),
.rx_frame_in_1_n (rx_frame_in_1_n),
.rx_frame_in_1_p (rx_frame_in_1_p),
.rx_frame_in_1_p (rx_frame_in_1_p),
.spdif (spdif),
.spi_csn_0_i (1'b1),
.spi_csn_0_o (spi_ad9361_0),
.spi_csn_0_o (spi_ad9361_0),
.spi_csn_1_o (spi_ad9361_1),
.spi_csn_2_o (spi_ad5355),
.spi_csn_2_o (spi_ad5355),
.spi_miso_i (spi_miso),
.spi_mosi_i (1'b0),
.spi_mosi_o (spi_mosi),

7
projects/fmcomms5/zc706/system_constr.xdc
View File

@ -133,10 +133,3 @@ set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports gpio_ca
create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name ps7_clk_2 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]
set_clock_groups -asynchronous -group {ad9361_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_clock_groups -asynchronous -group {ps7_clk_2}

51
projects/fmcomms5/zc706/system_top.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -65,7 +65,7 @@ module system_top (
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
@ -73,7 +73,7 @@ module system_top (
hdmi_data,
spdif,
iic_scl,
iic_sda,
@ -114,8 +114,8 @@ module system_top (
tx_frame_out_1_p,
tx_frame_out_1_n,
tx_data_out_1_p,
tx_data_out_1_n,
gpio_status_1,
tx_data_out_1_n,
gpio_status_1,
gpio_ctl_1,
gpio_en_agc_1,
gpio_resetb_1,
@ -187,7 +187,7 @@ module system_top (
inout [ 7:0] gpio_status_0;
inout [ 3:0] gpio_ctl_0;
inout gpio_en_agc_0;
output mcs_sync;
output mcs_sync;
inout gpio_resetb_0;
inout gpio_enable_0;
inout gpio_txnrx_0;
@ -209,7 +209,7 @@ module system_top (
output tx_frame_out_1_p;
output tx_frame_out_1_n;
output [ 5:0] tx_data_out_1_p;
output [ 5:0] tx_data_out_1_n;
output [ 5:0] tx_data_out_1_n;
inout [ 7:0] gpio_status_1;
inout [ 3:0] gpio_ctl_1;
inout gpio_en_agc_1;
@ -226,10 +226,10 @@ module system_top (
output spi_ad5355;
output spi_clk;
output spi_mosi;
input spi_miso;
input spi_miso;
input ref_clk_p;
input ref_clk_n;
input ref_clk_n;
// internal registers
@ -248,6 +248,7 @@ module system_top (
wire gpio_open_45_45;
wire gpio_open_44_44;
wire gpio_open_15_15;
wire [15:0] ps_intrs;
// multi-chip synchronization
@ -337,6 +338,24 @@ module system_top (
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ad9361_dac_dma_irq (ps_intrs[12]),
.ad9361_adc_dma_irq (ps_intrs[13]),
.fmcomms5_gpio_irq(),
.fmcomms5_spi_irq(),
.rx_clk_in_0_n (rx_clk_in_0_n),
.rx_clk_in_0_p (rx_clk_in_0_p),
.rx_clk_in_1_n (rx_clk_in_1_n),
@ -348,12 +367,12 @@ module system_top (
.rx_frame_in_0_n (rx_frame_in_0_n),
.rx_frame_in_0_p (rx_frame_in_0_p),
.rx_frame_in_1_n (rx_frame_in_1_n),
.rx_frame_in_1_p (rx_frame_in_1_p),
.rx_frame_in_1_p (rx_frame_in_1_p),
.spdif (spdif),
.spi_csn_0_i (1'b1),
.spi_csn_0_o (spi_ad9361_0),
.spi_csn_0_o (spi_ad9361_0),
.spi_csn_1_o (spi_ad9361_1),
.spi_csn_2_o (spi_ad5355),
.spi_csn_2_o (spi_ad5355),
.spi_miso_i (spi_miso),
.spi_mosi_i (1'b0),
.spi_mosi_o (spi_mosi),