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fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints

main
Adrian Costina 2014-11-07 13:45:15 +02:00
parent 2d9a529ab8
commit 0ade2a5f67
5 changed files with 175 additions and 141 deletions
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26
projects/fmcomms5/common/fmcomms5_bd.tcl
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@ -56,6 +56,13 @@ set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
set spi_miso_i [create_bd_port -dir I spi_miso_i]
# interrupts
set fmcomms5_gpio_irq [create_bd_port -dir O fmcomms5_gpio_irq]
set ad9361_adc_dma_irq [create_bd_port -dir O ad9361_adc_dma_irq]
set ad9361_dac_dma_irq [create_bd_port -dir O ad9361_dac_dma_irq]
set fmcomms5_spi_irq [create_bd_port -dir O fmcomms5_spi_irq]
# instances
set axi_ad9361_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_0]
@ -105,7 +112,7 @@ if {$sys_zynq == 1} {
}
if {$sys_zynq == 0} {
set axi_fmcomms2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_fmcomms2_spi]
set axi_fmcomms2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms2_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms2_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_fmcomms2_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms2_spi
@ -156,7 +163,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net spi_mosi_i [get_bd_pins axi_fmcomms2_spi/io0_i] [get_bd_ports spi_mosi_i]
connect_bd_net -net spi_mosi_o [get_bd_pins axi_fmcomms2_spi/io0_o] [get_bd_ports spi_mosi_o]
connect_bd_net -net spi_miso_i [get_bd_pins axi_fmcomms2_spi/io1_i] [get_bd_ports spi_miso_i]
connect_bd_net -net spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In7]
connect_bd_net -net spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_ports fmcomms5_spi_irq]
} else {
connect_bd_net -net spi_csn_0_i [get_bd_pins sys_ps7/SPI0_SS_I] [get_bd_ports spi_csn_0_i]
connect_bd_net -net spi_csn_0_o [get_bd_pins sys_ps7/SPI0_SS_O] [get_bd_ports spi_csn_0_o]
@ -175,7 +182,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net gpio_i [get_bd_pins axi_fmcomms2_gpio/gpio_io_i] [get_bd_ports gpio_i]
connect_bd_net -net gpio_o [get_bd_pins axi_fmcomms2_gpio/gpio_io_o] [get_bd_ports gpio_o]
connect_bd_net -net gpio_t [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] [get_bd_ports gpio_t]
connect_bd_net -net gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In8]
connect_bd_net -net gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_ports fmcomms5_gpio_irq]
}
# connections (ad9361)
@ -276,9 +283,9 @@ connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins util_dac_unpack_0
connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9361_fifo_valid [get_bd_pins util_dac_unpack_0/fifo_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_ports ad9361_adc_dma_irq]
connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_ports ad9361_dac_dma_irq]
# interconnect (cpu)
@ -366,7 +373,8 @@ if {$xl_board eq "zc702"} {
# ila (adc) master
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_0]
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc_0]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_0
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_adc_0
@ -380,7 +388,8 @@ if {$xl_board eq "zc702"} {
# ila (adc) master
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_0]
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc_0]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_0
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {62}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {112}] $ila_adc_0
@ -399,7 +408,8 @@ if {$xl_board eq "zc702"} {
# ila (adc) slave
set ila_adc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_1]
set ila_adc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc_1]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_1
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_adc_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {62}] $ila_adc_1
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_1

7
projects/fmcomms5/zc702/system_constr.xdc
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@ -133,10 +133,3 @@ set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS25} [get_ports gpio_ca
create_clock -name rx_0_clk -period 5.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 5.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name ps7_clk_2 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]
set_clock_groups -asynchronous -group {ad9361_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_clock_groups -asynchronous -group {ps7_clk_2}

19
projects/fmcomms5/zc702/system_top.v
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@ -245,6 +245,7 @@ module system_top (
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 63:0] gpio_t;
wire [15:0] ps_intrs;
wire gpio_open_45_45;
wire gpio_open_44_44;
@ -335,6 +336,24 @@ module system_top (
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ad9361_dac_dma_irq (ps_intrs[12]),
.ad9361_adc_dma_irq (ps_intrs[13]),
.fmcomms5_gpio_irq(),
.fmcomms5_spi_irq(),
.rx_clk_in_0_n (rx_clk_in_0_n),
.rx_clk_in_0_p (rx_clk_in_0_p),
.rx_clk_in_1_n (rx_clk_in_1_n),

7
projects/fmcomms5/zc706/system_constr.xdc
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@ -133,10 +133,3 @@ set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports gpio_ca
create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name ps7_clk_2 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]
set_clock_groups -asynchronous -group {ad9361_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_clock_groups -asynchronous -group {ps7_clk_2}

19
projects/fmcomms5/zc706/system_top.v
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@ -248,6 +248,7 @@ module system_top (
wire gpio_open_45_45;
wire gpio_open_44_44;
wire gpio_open_15_15;
wire [15:0] ps_intrs;
// multi-chip synchronization
@ -337,6 +338,24 @@ module system_top (
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ad9361_dac_dma_irq (ps_intrs[12]),
.ad9361_adc_dma_irq (ps_intrs[13]),
.fmcomms5_gpio_irq(),
.fmcomms5_spi_irq(),
.rx_clk_in_0_n (rx_clk_in_0_n),
.rx_clk_in_0_p (rx_clk_in_0_p),
.rx_clk_in_1_n (rx_clk_in_1_n),