diff --git a/library/axi_ad9265/Makefile b/library/axi_ad9265/Makefile index c871ca415..e0f3fc0a1 100644 --- a/library/axi_ad9265/Makefile +++ b/library/axi_ad9265/Makefile @@ -18,8 +18,8 @@ M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../xilinx/common/ad_lvds_clk.v -M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += ../xilinx/common/ad_data_clk.v +M_DEPS += ../xilinx/common/ad_data_in.v M_DEPS += ../xilinx/common/ad_rst_constr.xdc M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc diff --git a/library/axi_ad9467/Makefile b/library/axi_ad9467/Makefile index d46185a1b..9370d626c 100644 --- a/library/axi_ad9467/Makefile +++ b/library/axi_ad9467/Makefile @@ -17,8 +17,8 @@ M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../xilinx/common/ad_lvds_clk.v -M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += ../xilinx/common/ad_data_clk.v +M_DEPS += ../xilinx/common/ad_data_in.v M_DEPS += ../xilinx/common/ad_rst_constr.xdc M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc diff --git a/library/axi_ad9963/Makefile b/library/axi_ad9963/Makefile index 04dc07ebb..c5a3c2226 100644 --- a/library/axi_ad9963/Makefile +++ b/library/axi_ad9963/Makefile @@ -24,7 +24,7 @@ M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += ../xilinx/common/ad_data_in.v M_DEPS += ../xilinx/common/ad_mul.v M_DEPS += ../xilinx/common/ad_rst_constr.xdc M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc diff --git a/library/axi_fmcadc5_sync/Makefile b/library/axi_fmcadc5_sync/Makefile index 1e9985b48..ef63e66a6 100644 --- a/library/axi_fmcadc5_sync/Makefile +++ b/library/axi_fmcadc5_sync/Makefile @@ -8,7 +8,7 @@ M_DEPS += ../common/up_axi.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../xilinx/common/ad_lvds_out.v +M_DEPS += ../xilinx/common/ad_data_out.v M_DEPS += ../xilinx/common/ad_mul.v M_DEPS += axi_fmcadc5_sync.v M_DEPS += axi_fmcadc5_sync_calcor.v diff --git a/library/xilinx/common/ad_lvds_clk.v b/library/xilinx/common/ad_lvds_clk.v deleted file mode 100644 index d80a6a8d0..000000000 --- a/library/xilinx/common/ad_lvds_clk.v +++ /dev/null @@ -1,84 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad_lvds_clk #( - - parameter DEVICE_TYPE = 0) ( - - input rst, - output locked, - - input clk_in_p, - input clk_in_n, - output clk); - - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; - - // wires - - wire clk_ibuf_s; - - // defaults - - assign locked = 1'b1; - - // instantiations - - IBUFGDS i_rx_clk_ibuf ( - .I (clk_in_p), - .IB (clk_in_n), - .O (clk_ibuf_s)); - - generate - if (DEVICE_TYPE == VIRTEX6) begin - BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf ( - .CLR (1'b0), - .CE (1'b1), - .I (clk_ibuf_s), - .O (clk)); - end else begin - BUFG i_clk_gbuf ( - .I (clk_ibuf_s), - .O (clk)); - end - endgenerate - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/xilinx/common/ad_lvds_in.v b/library/xilinx/common/ad_lvds_in.v deleted file mode 100644 index 3542f1857..000000000 --- a/library/xilinx/common/ad_lvds_in.v +++ /dev/null @@ -1,285 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad_lvds_in #( - - // parameters - - parameter SINGLE_ENDED = 0, - parameter DEVICE_TYPE = 0, - parameter IODELAY_ENABLE = 1, - parameter IODELAY_CTRL = 0, - parameter IODELAY_GROUP = "dev_if_delay_group") ( - - // data interface - - input rx_clk, - input rx_data_in_p, - input rx_data_in_n, - output rx_data_p, - output rx_data_n, - - // delay-data interface - - input up_clk, - input up_dld, - input [ 4:0] up_dwdata, - output [ 4:0] up_drdata, - - // delay-cntrl interface - - input delay_clk, - input delay_rst, - output delay_locked); - - // internal parameters - - localparam VIRTEX7 = 0; - localparam VIRTEX6 = 1; - localparam ULTRASCALE_PLUS = 2; - localparam ULTRASCALE = 3; - - // internal signals - - wire rx_data_ibuf_s; - wire rx_data_idelay_s; - wire [ 8:0] up_drdata_s; - - // delay controller - - generate if (IODELAY_ENABLE == 1 && IODELAY_CTRL == 1) begin - if ((DEVICE_TYPE == ULTRASCALE_PLUS) || (DEVICE_TYPE == ULTRASCALE)) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl ( - .RST (delay_rst), - .REFCLK (delay_clk), - .RDY (delay_locked)); - end - if ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6)) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYCTRL i_delay_ctrl ( - .RST (delay_rst), - .REFCLK (delay_clk), - .RDY (delay_locked)); - end - end else begin - assign delay_locked = 1'b1; - end - endgenerate - - // receive data interface, ibuf -> idelay -> iddr - - generate - if (SINGLE_ENDED == 1) begin - IBUF i_rx_data_ibuf ( - .I (rx_data_in_p), - .O (rx_data_ibuf_s)); - end else begin - IBUFDS i_rx_data_ibuf ( - .I (rx_data_in_p), - .IB (rx_data_in_n), - .O (rx_data_ibuf_s)); - end - endgenerate - - // idelay - - generate if (IODELAY_ENABLE == 1) begin - if (DEVICE_TYPE == VIRTEX6) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IODELAYE1 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("I"), - .HIGH_PERFORMANCE_MODE ("TRUE"), - .IDELAY_TYPE ("VAR_LOADABLE"), - .IDELAY_VALUE (0), - .ODELAY_TYPE ("FIXED"), - .ODELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .SIGNAL_PATTERN ("DATA")) - i_rx_data_idelay ( - .T (1'b1), - .CE (1'b0), - .INC (1'b0), - .CLKIN (1'b0), - .DATAIN (1'b0), - .ODATAIN (1'b0), - .CINVCTRL (1'b0), - .C (up_clk), - .IDATAIN (rx_data_ibuf_s), - .DATAOUT (rx_data_idelay_s), - .RST (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end - - if (DEVICE_TYPE == VIRTEX7) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYE2 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("IDATAIN"), - .HIGH_PERFORMANCE_MODE ("FALSE"), - .IDELAY_TYPE ("VAR_LOAD"), - .IDELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .PIPE_SEL ("FALSE"), - .SIGNAL_PATTERN ("DATA")) - i_rx_data_idelay ( - .CE (1'b0), - .INC (1'b0), - .DATAIN (1'b0), - .LDPIPEEN (1'b0), - .CINVCTRL (1'b0), - .REGRST (1'b0), - .C (up_clk), - .IDATAIN (rx_data_ibuf_s), - .DATAOUT (rx_data_idelay_s), - .LD (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end - - if (DEVICE_TYPE == ULTRASCALE) begin - assign up_drdata = up_drdata_s[8:4]; - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYE3 #( - .SIM_DEVICE ("ULTRASCALE"), - .DELAY_SRC ("IDATAIN"), - .DELAY_TYPE ("VAR_LOAD"), - .REFCLK_FREQUENCY (200.0), - .DELAY_FORMAT ("COUNT")) - i_rx_data_idelay ( - .CASC_RETURN (1'b0), - .CASC_IN (1'b0), - .CASC_OUT (), - .CE (1'b0), - .CLK (up_clk), - .INC (1'b0), - .LOAD (up_dld), - .CNTVALUEIN ({up_dwdata, 4'd0}), - .CNTVALUEOUT (up_drdata_s), - .DATAIN (1'b0), - .IDATAIN (rx_data_ibuf_s), - .DATAOUT (rx_data_idelay_s), - .RST (1'b0), - .EN_VTC (~up_dld)); - end - - if (DEVICE_TYPE == ULTRASCALE_PLUS) begin - assign up_drdata = up_drdata_s[8:4]; - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYE3 #( - .SIM_DEVICE ("ULTRASCALE_PLUS_ES1"), - .DELAY_SRC ("IDATAIN"), - .DELAY_TYPE ("VAR_LOAD"), - .REFCLK_FREQUENCY (200.0), - .DELAY_FORMAT ("COUNT")) - i_rx_data_idelay ( - .CASC_RETURN (1'b0), - .CASC_IN (1'b0), - .CASC_OUT (), - .CE (1'b0), - .CLK (up_clk), - .INC (1'b0), - .LOAD (up_dld), - .CNTVALUEIN ({up_dwdata, 4'd0}), - .CNTVALUEOUT (up_drdata_s), - .DATAIN (1'b0), - .IDATAIN (rx_data_ibuf_s), - .DATAOUT (rx_data_idelay_s), - .RST (1'b0), - .EN_VTC (~up_dld)); - end - - end else begin - assign rx_data_idelay_s = rx_data_ibuf_s; - assign up_drdata = 'h00; - end - endgenerate - - // iddr - - generate - if (DEVICE_TYPE == ULTRASCALE) begin - IDDRE1 #( - .DDR_CLK_EDGE ("SAME_EDGE")) - i_rx_data_iddr ( - .R (1'b0), - .C (rx_clk), - .CB (~rx_clk), - .D (rx_data_idelay_s), - .Q1 (rx_data_p), - .Q2 (rx_data_n)); - end - endgenerate - - generate - if (DEVICE_TYPE == ULTRASCALE_PLUS) begin - IDDRE1 #( - .DDR_CLK_EDGE ("SAME_EDGE")) - i_rx_data_iddr ( - .R (1'b0), - .C (rx_clk), - .CB (~rx_clk), - .D (rx_data_idelay_s), - .Q1 (rx_data_p), - .Q2 (rx_data_n)); - end - endgenerate - - generate - if ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6)) begin - IDDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT_Q1 (1'b0), - .INIT_Q2 (1'b0), - .SRTYPE ("ASYNC")) - i_rx_data_iddr ( - .CE (1'b1), - .R (1'b0), - .S (1'b0), - .C (rx_clk), - .D (rx_data_idelay_s), - .Q1 (rx_data_p), - .Q2 (rx_data_n)); - end - endgenerate - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/xilinx/common/ad_lvds_out.v b/library/xilinx/common/ad_lvds_out.v deleted file mode 100644 index 32fb79845..000000000 --- a/library/xilinx/common/ad_lvds_out.v +++ /dev/null @@ -1,164 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad_lvds_out #( - - parameter DEVICE_TYPE = 0, - parameter SINGLE_ENDED = 0, - parameter IODELAY_ENABLE = 0, - parameter IODELAY_CTRL = 0, - parameter IODELAY_GROUP = "dev_if_delay_group") ( - - // data interface - - input tx_clk, - input tx_data_p, - input tx_data_n, - output tx_data_out_p, - output tx_data_out_n, - - // delay-data interface - - input up_clk, - input up_dld, - input [ 4:0] up_dwdata, - output [ 4:0] up_drdata, - - // delay-cntrl interface - - input delay_clk, - input delay_rst, - output delay_locked); - - localparam VIRTEX7 = 0; - localparam VIRTEX6 = 1; - localparam ULTRASCALE = 2; - - // internal signals - - wire tx_data_oddr_s; - wire tx_data_odelay_s; - - // delay controller - - generate - if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == VIRTEX7) && (IODELAY_CTRL == 1)) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYCTRL i_delay_ctrl ( - .RST (delay_rst), - .REFCLK (delay_clk), - .RDY (delay_locked)); - end else begin - assign delay_locked = 1'b1; - end - endgenerate - - // transmit data interface, oddr -> odelay -> obuf - - generate - if (DEVICE_TYPE == ULTRASCALE) begin - ODDRE1 i_tx_data_oddr ( - .SR (1'b0), - .C (tx_clk), - .D1 (tx_data_p), - .D2 (tx_data_n), - .Q (tx_data_oddr_s)); - end else begin - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_tx_data_oddr ( - .CE (1'b1), - .R (1'b0), - .S (1'b0), - .C (tx_clk), - .D1 (tx_data_p), - .D2 (tx_data_n), - .Q (tx_data_oddr_s)); - end - endgenerate - - generate - if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == VIRTEX7)) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - ODELAYE2 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("ODATAIN"), - .HIGH_PERFORMANCE_MODE ("FALSE"), - .ODELAY_TYPE ("VAR_LOAD"), - .ODELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .PIPE_SEL ("FALSE"), - .SIGNAL_PATTERN ("DATA")) - i_tx_data_odelay ( - .CE (1'b0), - .CLKIN (1'b0), - .INC (1'b0), - .LDPIPEEN (1'b0), - .CINVCTRL (1'b0), - .REGRST (1'b0), - .C (up_clk), - .ODATAIN (tx_data_oddr_s), - .DATAOUT (tx_data_odelay_s), - .LD (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end else begin - assign up_drdata = 5'd0; - assign tx_data_odelay_s = tx_data_oddr_s; - end - endgenerate - - generate - if (SINGLE_ENDED == 1) begin - assign tx_data_out_n = 1'b0; - OBUF i_tx_data_obuf ( - .I (tx_data_odelay_s), - .O (tx_data_out_p)); - end else begin - OBUFDS i_tx_data_obuf ( - .I (tx_data_odelay_s), - .O (tx_data_out_p), - .OB (tx_data_out_n)); - end - endgenerate - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile index c0c4bcb18..34807e915 100644 --- a/projects/fmcadc2/zc706/Makefile +++ b/projects/fmcadc2/zc706/Makefile @@ -18,7 +18,6 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc M_DEPS += ../../common/zc706/zc706_plddr3_adcfifo_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl M_DEPS += ../../../library/common/ad_sysref_gen.v diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile index 357f53fd4..9e31d560f 100644 --- a/projects/fmcadc5/vc707/Makefile +++ b/projects/fmcadc5/vc707/Makefile @@ -18,7 +18,6 @@ M_DEPS += ../../common/xilinx/adcfifo_bd.tcl M_DEPS += ../../common/vc707/vc707_system_mig.prj M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr