Merge branch 'hdl_2014_r2' into dev
Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.vmain
Rejeesh Kutty
commit
0a8fabe874
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@ -37,7 +37,7 @@
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`timescale 1ns/100ps
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module ad9625_fmc_spi (
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module fmcadc2_spi (
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spi_adc_csn,
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spi_clk_csn,
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@ -4,6 +4,6 @@ source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
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p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 10
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source ../common/ad9625_fmc_bd.tcl
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source ../common/fmcadc2_bd.tcl
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@ -4,10 +4,10 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create ad9625_fmc_vc707
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adi_project_files ad9625_fmc_vc707 [list \
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adi_project_create fmcadc2_vc707
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adi_project_files fmcadc2_vc707 [list \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"../common/ad9625_fmc_spi.v" \
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"../common/fmcadc2_spi.v" \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
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@ -15,6 +15,6 @@ adi_project_files ad9625_fmc_vc707 [list \
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
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adi_project_run ad9625_fmc_vc707
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adi_project_run fmcadc2_vc707
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@ -242,7 +242,7 @@ module system_top (
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assign spi_adc_clk = spi_clk;
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assign spi_clk_clk = spi_clk;
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ad9625_fmc_spi i_ad9625_fmc_spi (
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fmcadc2_spi i_fmcadc2_spi (
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.spi_adc_csn (spi_adc_csn),
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.spi_clk_csn (spi_clk_csn),
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.spi_clk (spi_clk),
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@ -12,7 +12,7 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_
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[get_bd_addr_segs axi_ad9625_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr
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source ../common/ad9625_fmc_bd.tcl
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source ../common/fmcadc2_bd.tcl
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@ -4,10 +4,10 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create ad9625_fmc_zc706
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adi_project_files ad9625_fmc_zc706 [list \
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adi_project_create fmcadc2_zc706
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adi_project_files fmcadc2_zc706 [list \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"../common/ad9625_fmc_spi.v" \
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"../common/fmcadc2_spi.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
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@ -16,6 +16,6 @@ adi_project_files ad9625_fmc_zc706 [list \
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
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adi_project_run ad9625_fmc_zc706
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adi_project_run fmcadc2_zc706
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@ -235,7 +235,7 @@ module system_top (
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assign spi_adc_clk = spi_clk;
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assign spi_clk_clk = spi_clk;
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ad9625_fmc_spi i_ad9625_fmc_spi (
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fmcadc2_spi i_fmcadc2_spi (
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.spi_adc_csn (spi_adc_csn),
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.spi_clk_csn (spi_clk_csn),
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.spi_clk (spi_clk),
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@ -1,5 +1,5 @@
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# fmcadc3
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# fmcadc4
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if {$sys_zynq == 0} {
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@ -56,9 +56,9 @@ if {$sys_zynq == 0} {
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set adc_dsync [create_bd_port -dir I adc_dsync]
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set adc_ddata [create_bd_port -dir I -from 255 -to 0 adc_ddata]
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set fmcadc3_spi_intr [create_bd_port -dir O fmcadc3_spi_intr]
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set fmcadc3_gpio_intr [create_bd_port -dir O fmcadc3_gpio_intr]
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set fmcadc3_dma_intr [create_bd_port -dir O fmcadc3_dma_intr]
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set fmcadc4_spi_intr [create_bd_port -dir O fmcadc4_spi_intr]
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set fmcadc4_gpio_intr [create_bd_port -dir O fmcadc4_gpio_intr]
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set fmcadc4_dma_intr [create_bd_port -dir O fmcadc4_dma_intr]
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# adc peripherals
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@ -90,29 +90,29 @@ if {$sys_zynq == 1} {
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# dac/adc common gt/gpio
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set axi_fmcadc3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc3_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_fmcadc3_gt
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set axi_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc4_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_fmcadc4_gt
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if {$sys_zynq == 1} {
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set axi_fmcadc3_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_fmcadc3_gt_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_fmcadc3_gt_interconnect
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set axi_fmcadc4_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_fmcadc4_gt_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_fmcadc4_gt_interconnect
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}
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# gpio and spi
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if {$sys_zynq == 0} {
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set axi_fmcadc3_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_fmcadc3_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcadc3_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_fmcadc3_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcadc3_spi
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set axi_fmcadc4_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_fmcadc4_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcadc4_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_fmcadc4_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcadc4_spi
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set axi_fmcadc3_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_fmcadc3_gpio]
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set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_fmcadc3_gpio
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set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_fmcadc3_gpio
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set_property -dict [list CONFIG.C_GPIO2_WIDTH {1}] $axi_fmcadc3_gpio
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_fmcadc3_gpio
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set axi_fmcadc4_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_fmcadc4_gpio]
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set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_fmcadc4_gpio
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set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_fmcadc4_gpio
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set_property -dict [list CONFIG.C_GPIO2_WIDTH {1}] $axi_fmcadc4_gpio
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_fmcadc4_gpio
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}
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# additions to default configuration
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@ -151,13 +151,13 @@ if {$sys_zynq == 1} {
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if {$sys_zynq == 0} {
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_fmcadc3_spi/ss_i]
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_fmcadc3_spi/ss_o]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_fmcadc3_spi/sck_i]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_fmcadc3_spi/sck_o]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_fmcadc3_spi/io0_i]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_fmcadc3_spi/io0_o]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_fmcadc3_spi/io1_i]
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_fmcadc4_spi/ss_i]
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_fmcadc4_spi/ss_o]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_fmcadc4_spi/sck_i]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_fmcadc4_spi/sck_o]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_fmcadc4_spi/io0_i]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_fmcadc4_spi/io0_o]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_fmcadc4_spi/io1_i]
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} else {
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@ -174,44 +174,44 @@ if {$sys_zynq == 0} {
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if {$sys_zynq == 0} {
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connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_fmcadc3_gpio/gpio_io_i]
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connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_fmcadc3_gpio/gpio_io_o]
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connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_fmcadc3_gpio/gpio_io_t]
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connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_i]
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connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_o]
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connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_t]
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connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_fmcadc4_gpio/gpio_io_i]
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connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_fmcadc4_gpio/gpio_io_o]
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connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_fmcadc4_gpio/gpio_io_t]
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connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_fmcadc4_gpio/gpio2_io_i]
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connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_fmcadc4_gpio/gpio2_io_o]
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connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_fmcadc4_gpio/gpio2_io_t]
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}
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# connections (gt)
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connect_bd_net -net axi_fmcadc3_gt_ref_clk_q [get_bd_pins axi_fmcadc3_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_fmcadc3_gt_rx_data_p [get_bd_pins axi_fmcadc3_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_fmcadc3_gt_rx_data_n [get_bd_pins axi_fmcadc3_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_fmcadc3_gt_rx_sync [get_bd_pins axi_fmcadc3_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_fmcadc3_gt_rx_ext_sysref [get_bd_pins axi_fmcadc3_gt/rx_ext_sysref] [get_bd_ports rx_sysref]
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connect_bd_net -net axi_fmcadc4_gt_ref_clk_q [get_bd_pins axi_fmcadc4_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_fmcadc4_gt_rx_data_p [get_bd_pins axi_fmcadc4_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_fmcadc4_gt_rx_data_n [get_bd_pins axi_fmcadc4_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_fmcadc4_gt_rx_sync [get_bd_pins axi_fmcadc4_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_fmcadc4_gt_rx_ext_sysref [get_bd_pins axi_fmcadc4_gt/rx_ext_sysref] [get_bd_ports rx_sysref]
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# connections (adc)
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connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_fmcadc3_gt/rx_clk_g]
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connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_fmcadc3_gt/rx_clk]
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connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_core_0/rx_clk]
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connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_core_1/rx_clk]
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connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_jesd/rx_core_clk]
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connect_bd_net -net axi_fmcadc4_gt_rx_clk [get_bd_pins axi_fmcadc4_gt/rx_clk_g]
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connect_bd_net -net axi_fmcadc4_gt_rx_clk [get_bd_pins axi_fmcadc4_gt/rx_clk]
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connect_bd_net -net axi_fmcadc4_gt_rx_clk [get_bd_pins axi_ad9234_core_0/rx_clk]
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connect_bd_net -net axi_fmcadc4_gt_rx_clk [get_bd_pins axi_ad9234_core_1/rx_clk]
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connect_bd_net -net axi_fmcadc4_gt_rx_clk [get_bd_pins axi_ad9234_jesd/rx_core_clk]
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connect_bd_net -net axi_fmcadc3_gt_rx_rst [get_bd_pins axi_fmcadc3_gt/rx_rst] [get_bd_pins axi_ad9234_jesd/rx_reset]
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connect_bd_net -net axi_fmcadc3_gt_rx_sysref [get_bd_pins axi_fmcadc3_gt/rx_sysref] [get_bd_pins axi_ad9234_jesd/rx_sysref]
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connect_bd_net -net axi_fmcadc3_gt_rx_gt_charisk [get_bd_pins axi_fmcadc3_gt/rx_gt_charisk] [get_bd_pins axi_ad9234_jesd/gt_rxcharisk_in]
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connect_bd_net -net axi_fmcadc3_gt_rx_gt_disperr [get_bd_pins axi_fmcadc3_gt/rx_gt_disperr] [get_bd_pins axi_ad9234_jesd/gt_rxdisperr_in]
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connect_bd_net -net axi_fmcadc3_gt_rx_gt_notintable [get_bd_pins axi_fmcadc3_gt/rx_gt_notintable] [get_bd_pins axi_ad9234_jesd/gt_rxnotintable_in]
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connect_bd_net -net axi_fmcadc3_gt_rx_gt_data [get_bd_pins axi_fmcadc3_gt/rx_gt_data] [get_bd_pins axi_ad9234_jesd/gt_rxdata_in]
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connect_bd_net -net axi_fmcadc3_gt_rx_rst_done [get_bd_pins axi_fmcadc3_gt/rx_rst_done] [get_bd_pins axi_ad9234_jesd/rx_reset_done]
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connect_bd_net -net axi_fmcadc3_gt_rx_ip_comma_align [get_bd_pins axi_fmcadc3_gt/rx_ip_comma_align] [get_bd_pins axi_ad9234_jesd/rxencommaalign_out]
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connect_bd_net -net axi_fmcadc3_gt_rx_ip_sync [get_bd_pins axi_fmcadc3_gt/rx_ip_sync] [get_bd_pins axi_ad9234_jesd/rx_sync]
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connect_bd_net -net axi_fmcadc3_gt_rx_ip_sof [get_bd_pins axi_fmcadc3_gt/rx_ip_sof] [get_bd_pins axi_ad9234_jesd/rx_start_of_frame]
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connect_bd_net -net axi_fmcadc3_gt_rx_ip_data [get_bd_pins axi_fmcadc3_gt/rx_ip_data] [get_bd_pins axi_ad9234_jesd/rx_tdata]
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connect_bd_net -net axi_fmcadc3_gt_rx_data [get_bd_pins axi_fmcadc3_gt/rx_data] [get_bd_ports gt_data]
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connect_bd_net -net axi_fmcadc3_gt_0_rx_data [get_bd_pins axi_ad9234_core_0/rx_data] [get_bd_ports gt_data_0]
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connect_bd_net -net axi_fmcadc3_gt_1_rx_data [get_bd_pins axi_ad9234_core_1/rx_data] [get_bd_ports gt_data_1]
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connect_bd_net -net axi_fmcadc4_gt_rx_rst [get_bd_pins axi_fmcadc4_gt/rx_rst] [get_bd_pins axi_ad9234_jesd/rx_reset]
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connect_bd_net -net axi_fmcadc4_gt_rx_sysref [get_bd_pins axi_fmcadc4_gt/rx_sysref] [get_bd_pins axi_ad9234_jesd/rx_sysref]
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connect_bd_net -net axi_fmcadc4_gt_rx_gt_charisk [get_bd_pins axi_fmcadc4_gt/rx_gt_charisk] [get_bd_pins axi_ad9234_jesd/gt_rxcharisk_in]
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connect_bd_net -net axi_fmcadc4_gt_rx_gt_disperr [get_bd_pins axi_fmcadc4_gt/rx_gt_disperr] [get_bd_pins axi_ad9234_jesd/gt_rxdisperr_in]
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connect_bd_net -net axi_fmcadc4_gt_rx_gt_notintable [get_bd_pins axi_fmcadc4_gt/rx_gt_notintable] [get_bd_pins axi_ad9234_jesd/gt_rxnotintable_in]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_gt_data [get_bd_pins axi_fmcadc4_gt/rx_gt_data] [get_bd_pins axi_ad9234_jesd/gt_rxdata_in]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_rst_done [get_bd_pins axi_fmcadc4_gt/rx_rst_done] [get_bd_pins axi_ad9234_jesd/rx_reset_done]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_ip_comma_align [get_bd_pins axi_fmcadc4_gt/rx_ip_comma_align] [get_bd_pins axi_ad9234_jesd/rxencommaalign_out]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_ip_sync [get_bd_pins axi_fmcadc4_gt/rx_ip_sync] [get_bd_pins axi_ad9234_jesd/rx_sync]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_ip_sof [get_bd_pins axi_fmcadc4_gt/rx_ip_sof] [get_bd_pins axi_ad9234_jesd/rx_start_of_frame]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_ip_data [get_bd_pins axi_fmcadc4_gt/rx_ip_data] [get_bd_pins axi_ad9234_jesd/rx_tdata]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_data [get_bd_pins axi_fmcadc4_gt/rx_data] [get_bd_ports gt_data]
|
||||
connect_bd_net -net axi_fmcadc4_gt_0_rx_data [get_bd_pins axi_ad9234_core_0/rx_data] [get_bd_ports gt_data_0]
|
||||
connect_bd_net -net axi_fmcadc4_gt_1_rx_data [get_bd_pins axi_ad9234_core_1/rx_data] [get_bd_ports gt_data_1]
|
||||
connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins axi_ad9234_dma/fifo_wr_clk]
|
||||
connect_bd_net -net axi_ad9234_0_adc_enable_0 [get_bd_pins axi_ad9234_core_0/adc_enable_0] [get_bd_ports adc_enable_0]
|
||||
connect_bd_net -net axi_ad9234_0_adc_valid_0 [get_bd_pins axi_ad9234_core_0/adc_valid_0] [get_bd_ports adc_valid_0]
|
||||
|
|
@ -229,7 +229,7 @@ if {$sys_zynq == 0} {
|
|||
connect_bd_net -net axi_ad9234_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9234_dma/fifo_wr_sync]
|
||||
connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9234_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins axi_ad9234_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9234_dma_irq [get_bd_pins axi_ad9234_dma/irq] [get_bd_ports fmcadc3_dma_intr]
|
||||
connect_bd_net -net axi_ad9234_dma_irq [get_bd_pins axi_ad9234_dma/irq] [get_bd_ports fmcadc4_dma_intr]
|
||||
|
||||
# dac/adc clocks
|
||||
|
||||
|
|
@ -241,13 +241,13 @@ if {$sys_zynq == 0} {
|
|||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9234_core_0/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9234_core_1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9234_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_fmcadc3_gt/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_fmcadc4_gt/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_core_0/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_core_1/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_jesd/s_axi_aclk]
|
||||
|
|
@ -257,7 +257,7 @@ if {$sys_zynq == 0} {
|
|||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_core_0/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_core_1/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_jesd/s_axi_aresetn]
|
||||
|
|
@ -265,47 +265,47 @@ if {$sys_zynq == 0} {
|
|||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_fmcadc3_spi/axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_fmcadc3_gpio/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_fmcadc4_spi/axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_fmcadc4_gpio/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_spi/ext_spi_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gpio/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_spi/ext_spi_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gpio/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_spi/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gpio/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_spi/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_gpio/s_axi_aresetn]
|
||||
|
||||
connect_bd_net -net axi_fmcadc3_spi_irq [get_bd_pins axi_fmcadc3_spi/ip2intc_irpt] [get_bd_ports fmcadc3_spi_intr]
|
||||
connect_bd_net -net axi_fmcadc3_gpio_irq [get_bd_pins axi_fmcadc3_gpio/ip2intc_irpt] [get_bd_ports fmcadc3_gpio_intr]
|
||||
connect_bd_net -net axi_fmcadc4_spi_irq [get_bd_pins axi_fmcadc4_spi/ip2intc_irpt] [get_bd_ports fmcadc4_spi_intr]
|
||||
connect_bd_net -net axi_fmcadc4_gpio_irq [get_bd_pins axi_fmcadc4_gpio/ip2intc_irpt] [get_bd_ports fmcadc4_gpio_intr]
|
||||
}
|
||||
|
||||
# gt uses hp3, and 100MHz clock for both DRP and AXI4
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_fmcadc3_gt/m_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_fmcadc4_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/m_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_gt/m_axi_aresetn]
|
||||
|
||||
} else {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_fmcadc3_gt_interconnect_m00_axi [get_bd_intf_pins axi_fmcadc3_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
|
||||
connect_bd_intf_net -intf_net axi_fmcadc3_gt_interconnect_s00_axi [get_bd_intf_pins axi_fmcadc3_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_fmcadc3_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_intf_net -intf_net axi_fmcadc4_gt_interconnect_m00_axi [get_bd_intf_pins axi_fmcadc4_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
|
||||
connect_bd_intf_net -intf_net axi_fmcadc4_gt_interconnect_s00_axi [get_bd_intf_pins axi_fmcadc4_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_fmcadc4_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gt_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gt_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gt_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/m_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc4_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_gt_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_gt/m_axi_aresetn]
|
||||
}
|
||||
|
||||
# memory interconnects share the same clock (fclk2)
|
||||
|
|
@ -361,36 +361,36 @@ if {$sys_zynq == 0} {
|
|||
set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_jesd_rx_mon
|
||||
|
||||
connect_bd_net -net axi_fmcadc3_gt_rx_mon_data [get_bd_pins axi_fmcadc3_gt/rx_mon_data]
|
||||
connect_bd_net -net axi_fmcadc3_gt_rx_mon_trigger [get_bd_pins axi_fmcadc3_gt/rx_mon_trigger]
|
||||
connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_fmcadc3_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_fmcadc3_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
connect_bd_net -net axi_fmcadc3_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_mon_data [get_bd_pins axi_fmcadc4_gt/rx_mon_data]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_mon_trigger [get_bd_pins axi_fmcadc4_gt/rx_mon_trigger]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
connect_bd_net -net axi_fmcadc4_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
|
||||
connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
|
||||
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_core_0/s_axi/axi_lite] SEG_data_ad9234_0_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_core_1/s_axi/axi_lite] SEG_data_ad9234_1_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_gt/s_axi/axi_lite] SEG_data_fmcadc3_gt
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc4_gt/s_axi/axi_lite] SEG_data_fmcadc4_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_jesd/s_axi/Reg] SEG_data_ad9234_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_dma/s_axi/axi_lite] SEG_data_ad9234_dma
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_gpio/S_AXI/Reg] SEG_data_fmcadc3_gpio
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_spi/axi_lite/Reg] SEG_data_fmcadc3_spi
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc4_gpio/S_AXI/Reg] SEG_data_fmcadc4_gpio
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc4_spi/axi_lite/Reg] SEG_data_fmcadc4_spi
|
||||
}
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9234_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_fmcadc3_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_fmcadc4_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
|
||||
} else {
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9234_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_fmcadc3_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_fmcadc4_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
}
|
||||
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module fmcadc3_spi (
|
||||
module fmcadc4_spi (
|
||||
|
||||
csn,
|
||||
spi_clk,
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
|
||||
source ../common/fmcadc3_bd.tcl
|
||||
source ../common/fmcadc4_bd.tcl
|
||||
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9234_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9234_dma
|
||||
|
|
@ -21,7 +21,7 @@ delete_bd_objs [get_bd_nets axi_ad9234_adc_ddata]
|
|||
delete_bd_objs [get_bd_nets axi_ad9234_adc_dsync]
|
||||
delete_bd_objs [get_bd_nets axi_ad9234_adc_dovf]
|
||||
|
||||
connect_bd_net -net [get_bd_nets axi_fmcadc3_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_fmcadc3_gt/rx_rst]
|
||||
connect_bd_net -net [get_bd_nets axi_fmcadc4_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_fmcadc4_gt/rx_rst]
|
||||
connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn]
|
||||
connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins axi_ad9234_dma/s_axis_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req]
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins axi_ad9234_dma/s_axis_d
|
|||
connect_bd_net -net axi_ad9234_adc_clk [get_bd_ports adc_clk]
|
||||
connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
|
||||
|
||||
connect_bd_net -net axi_ad9234_dma_irq [get_bd_ports fmcadc3_dma_intr] [get_bd_pins sys_concat_intc/In2]
|
||||
connect_bd_net -net axi_ad9234_dma_irq [get_bd_ports fmcadc4_dma_intr] [get_bd_pins sys_concat_intc/In2]
|
||||
|
||||
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
# fmcadc3
|
||||
# fmcadc4
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||
|
|
@ -46,7 +46,7 @@ set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9234_2
|
|||
# clocks
|
||||
|
||||
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcadc3_gt_rx_clk]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcadc4_gt_rx_clk]
|
||||
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
|
||||
create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk]
|
||||
create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0]
|
||||
|
|
@ -4,14 +4,14 @@
|
|||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
|
||||
adi_project_create fmcadc3_zc706
|
||||
adi_project_files fmcadc3_zc706 [list \
|
||||
"../common/fmcadc3_spi.v" \
|
||||
adi_project_create fmcadc4_zc706
|
||||
adi_project_files fmcadc4_zc706 [list \
|
||||
"../common/fmcadc4_spi.v" \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||
|
||||
adi_project_run fmcadc3_zc706
|
||||
adi_project_run fmcadc4_zc706
|
||||
|
||||
|
||||
|
|
@ -433,7 +433,7 @@ module system_top (
|
|||
.O (rx_sync_1_p),
|
||||
.OB (rx_sync_1_n));
|
||||
|
||||
fmcadc3_spi i_spi (
|
||||
fmcadc4_spi i_spi (
|
||||
.csn (csn),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
|
|
@ -1,299 +1,298 @@
|
|||
|
||||
# ad9625
|
||||
|
||||
set spi_csn_o [create_bd_port -dir O -from 3 -to 0 spi_csn_o]
|
||||
set spi_csn_i [create_bd_port -dir I -from 3 -to 0 spi_csn_i]
|
||||
set spi_clk_i [create_bd_port -dir I spi_clk_i]
|
||||
set spi_clk_o [create_bd_port -dir O spi_clk_o]
|
||||
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
|
||||
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
|
||||
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
|
||||
|
||||
set rx_ref_clk_0 [create_bd_port -dir I rx_ref_clk_0]
|
||||
set rx_data_0_p [create_bd_port -dir I -from 7 -to 0 rx_data_0_p]
|
||||
set rx_data_0_n [create_bd_port -dir I -from 7 -to 0 rx_data_0_n]
|
||||
set rx_sync_0 [create_bd_port -dir O rx_sync_0]
|
||||
|
||||
set rx_ref_clk_1 [create_bd_port -dir I rx_ref_clk_1]
|
||||
set rx_data_1_p [create_bd_port -dir I -from 7 -to 0 rx_data_1_p]
|
||||
set rx_data_1_n [create_bd_port -dir I -from 7 -to 0 rx_data_1_n]
|
||||
set rx_sync_1 [create_bd_port -dir O rx_sync_1]
|
||||
|
||||
set rx_sysref [create_bd_port -dir O rx_sysref]
|
||||
|
||||
set ad9625_spi_intr [create_bd_port -dir O ad9625_spi_intr]
|
||||
set ad9625_gpio_intr [create_bd_port -dir O ad9625_gpio_intr]
|
||||
set ad9625_dma_intr [create_bd_port -dir O ad9625_dma_intr]
|
||||
|
||||
set gpio_ad9625_i [create_bd_port -dir I -from 18 -to 0 gpio_ad9625_i]
|
||||
set gpio_ad9625_o [create_bd_port -dir O -from 18 -to 0 gpio_ad9625_o]
|
||||
set gpio_ad9625_t [create_bd_port -dir O -from 18 -to 0 gpio_ad9625_t]
|
||||
|
||||
set adc_clk [create_bd_port -dir O adc_clk]
|
||||
set adc_valid_0 [create_bd_port -dir O adc_valid_0]
|
||||
set adc_enable_0 [create_bd_port -dir O adc_enable_0]
|
||||
set adc_data_0 [create_bd_port -dir O -from 255 -to 0 adc_data_0]
|
||||
set adc_valid_1 [create_bd_port -dir O adc_valid_1]
|
||||
set adc_enable_1 [create_bd_port -dir O adc_enable_1]
|
||||
set adc_data_1 [create_bd_port -dir O -from 255 -to 0 adc_data_1]
|
||||
set adc_wr [create_bd_port -dir I adc_wr]
|
||||
set adc_wdata [create_bd_port -dir I -from 511 -to 0 adc_wdata]
|
||||
|
||||
# adc peripherals
|
||||
|
||||
set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
|
||||
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_0_core
|
||||
|
||||
set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9625_0_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
|
||||
|
||||
set axi_ad9625_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_0_gt]
|
||||
set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_0_gt
|
||||
|
||||
set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
|
||||
set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9625_1_core
|
||||
|
||||
set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9625_1_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
|
||||
|
||||
set axi_ad9625_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_1_gt]
|
||||
set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_1_gt
|
||||
|
||||
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
|
||||
|
||||
set axi_ad9625_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_ad9625_gpio]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {0}] $axi_ad9625_gpio
|
||||
set_property -dict [list CONFIG.C_GPIO_WIDTH {15}] $axi_ad9625_gpio
|
||||
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_ad9625_gpio
|
||||
|
||||
set axi_ad9625_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad9625_spi]
|
||||
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9625_spi
|
||||
set_property -dict [list CONFIG.C_NUM_SS_BITS {4}] $axi_ad9625_spi
|
||||
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi
|
||||
|
||||
|
||||
p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 512 18
|
||||
|
||||
# additions to default configuration
|
||||
|
||||
set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect
|
||||
set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
|
||||
|
||||
# connections (spi and gpio)
|
||||
|
||||
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9625_spi/ss_i]
|
||||
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9625_spi/ss_o]
|
||||
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9625_spi/sck_i]
|
||||
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9625_spi/sck_o]
|
||||
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9625_spi/io0_i]
|
||||
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9625_spi/io0_o]
|
||||
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9625_spi/io1_i]
|
||||
|
||||
connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins axi_ad9625_gpio/gpio_io_i]
|
||||
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
|
||||
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
|
||||
|
||||
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_ports ad9625_spi_intr]
|
||||
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_ports ad9625_gpio_intr]
|
||||
|
||||
# connections (gt)
|
||||
|
||||
connect_bd_net -net axi_ad9625_0_gt_ref_clk_c [get_bd_pins axi_ad9625_0_gt/ref_clk_c] [get_bd_ports rx_ref_clk_0]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_data_p [get_bd_pins axi_ad9625_0_gt/rx_data_p] [get_bd_ports rx_data_0_p]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_data_n [get_bd_pins axi_ad9625_0_gt/rx_data_n] [get_bd_ports rx_data_0_n]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_sync [get_bd_pins axi_ad9625_0_gt/rx_sync] [get_bd_ports rx_sync_0]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_0_gt/rx_sysref] [get_bd_ports rx_sysref]
|
||||
|
||||
connect_bd_net -net axi_ad9625_1_gt_ref_clk_c [get_bd_pins axi_ad9625_1_gt/ref_clk_c] [get_bd_ports rx_ref_clk_1]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_data_p [get_bd_pins axi_ad9625_1_gt/rx_data_p] [get_bd_ports rx_data_1_p]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_data_n [get_bd_pins axi_ad9625_1_gt/rx_data_n] [get_bd_ports rx_data_1_n]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_sync [get_bd_pins axi_ad9625_1_gt/rx_sync] [get_bd_ports rx_sync_1]
|
||||
|
||||
# connections (adc)
|
||||
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_0_gt/rx_rst]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_0_jesd/rx_reset]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_1_jesd/rx_reset]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_gt/rx_clk_g]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_gt/rx_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_core/rx_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_jesd/rx_core_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_gt/rx_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_core/rx_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_jesd/rx_core_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_ports adc_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_0_jesd/rx_sysref]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_1_jesd/rx_sysref]
|
||||
connect_bd_net -net axi_ad9625_0_core_raddr [get_bd_pins axi_ad9625_0_core/adc_raddr_out]
|
||||
connect_bd_net -net axi_ad9625_0_core_raddr [get_bd_pins axi_ad9625_0_core/adc_raddr_in]
|
||||
connect_bd_net -net axi_ad9625_0_core_raddr [get_bd_pins axi_ad9625_1_core/adc_raddr_in]
|
||||
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_gt_charisk [get_bd_pins axi_ad9625_0_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_0_jesd/gt_rxcharisk_in]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_gt_disperr [get_bd_pins axi_ad9625_0_gt/rx_gt_disperr] [get_bd_pins axi_ad9625_0_jesd/gt_rxdisperr_in]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_gt_notintable [get_bd_pins axi_ad9625_0_gt/rx_gt_notintable] [get_bd_pins axi_ad9625_0_jesd/gt_rxnotintable_in]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_gt_data [get_bd_pins axi_ad9625_0_gt/rx_gt_data] [get_bd_pins axi_ad9625_0_jesd/gt_rxdata_in]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst_done [get_bd_pins axi_ad9625_0_gt/rx_rst_done] [get_bd_pins axi_ad9625_0_jesd/rx_reset_done]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_ip_comma_align [get_bd_pins axi_ad9625_0_gt/rx_ip_comma_align] [get_bd_pins axi_ad9625_0_jesd/rxencommaalign_out]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_ip_sync [get_bd_pins axi_ad9625_0_gt/rx_ip_sync] [get_bd_pins axi_ad9625_0_jesd/rx_sync]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_ip_sof [get_bd_pins axi_ad9625_0_gt/rx_ip_sof] [get_bd_pins axi_ad9625_0_jesd/rx_start_of_frame]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_ip_data [get_bd_pins axi_ad9625_0_gt/rx_ip_data] [get_bd_pins axi_ad9625_0_jesd/rx_tdata]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_gt_charisk [get_bd_pins axi_ad9625_1_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_1_jesd/gt_rxcharisk_in]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_gt_disperr [get_bd_pins axi_ad9625_1_gt/rx_gt_disperr] [get_bd_pins axi_ad9625_1_jesd/gt_rxdisperr_in]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_gt_notintable [get_bd_pins axi_ad9625_1_gt/rx_gt_notintable] [get_bd_pins axi_ad9625_1_jesd/gt_rxnotintable_in]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_gt_data [get_bd_pins axi_ad9625_1_gt/rx_gt_data] [get_bd_pins axi_ad9625_1_jesd/gt_rxdata_in]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_rst_done [get_bd_pins axi_ad9625_1_gt/rx_rst_done] [get_bd_pins axi_ad9625_1_jesd/rx_reset_done]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_ip_comma_align [get_bd_pins axi_ad9625_1_gt/rx_ip_comma_align] [get_bd_pins axi_ad9625_1_jesd/rxencommaalign_out]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_ip_sync [get_bd_pins axi_ad9625_1_gt/rx_ip_sync] [get_bd_pins axi_ad9625_1_jesd/rx_sync]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_ip_sof [get_bd_pins axi_ad9625_1_gt/rx_ip_sof] [get_bd_pins axi_ad9625_1_jesd/rx_start_of_frame]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_ip_data [get_bd_pins axi_ad9625_1_gt/rx_ip_data] [get_bd_pins axi_ad9625_1_jesd/rx_tdata]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_data [get_bd_pins axi_ad9625_0_gt/rx_data] [get_bd_pins axi_ad9625_0_core/rx_data]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_data [get_bd_pins axi_ad9625_1_gt/rx_data] [get_bd_pins axi_ad9625_1_core/rx_data]
|
||||
connect_bd_net -net axi_ad9625_0_core_adc_valid [get_bd_pins axi_ad9625_0_core/adc_valid] [get_bd_ports adc_valid_0]
|
||||
connect_bd_net -net axi_ad9625_0_core_adc_enable [get_bd_pins axi_ad9625_0_core/adc_enable] [get_bd_ports adc_enable_0]
|
||||
connect_bd_net -net axi_ad9625_0_core_adc_data [get_bd_pins axi_ad9625_0_core/adc_data] [get_bd_ports adc_data_0]
|
||||
connect_bd_net -net axi_ad9625_1_core_adc_valid [get_bd_pins axi_ad9625_1_core/adc_valid] [get_bd_ports adc_valid_1]
|
||||
connect_bd_net -net axi_ad9625_1_core_adc_enable [get_bd_pins axi_ad9625_1_core/adc_enable] [get_bd_ports adc_enable_1]
|
||||
connect_bd_net -net axi_ad9625_1_core_adc_data [get_bd_pins axi_ad9625_1_core/adc_data] [get_bd_ports adc_data_1]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_fifo/adc_rst] [get_bd_pins axi_ad9625_0_gt/rx_rst]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_fifo/adc_clk] [get_bd_pins axi_ad9625_0_gt/rx_clk_g]
|
||||
connect_bd_net -net axi_ad9625_adc_wr [get_bd_ports adc_wr] [get_bd_pins axi_ad9625_fifo/adc_wr]
|
||||
connect_bd_net -net axi_ad9625_adc_wdata [get_bd_ports adc_wdata] [get_bd_pins axi_ad9625_fifo/adc_wdata]
|
||||
connect_bd_net -net axi_ad9625_adc_wovf [get_bd_pins axi_ad9625_0_core/adc_dovf] [get_bd_pins axi_ad9625_fifo/adc_wovf]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/s_axis_aclk]
|
||||
connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fifo/dma_wr] [get_bd_pins axi_ad9625_dma/s_axis_valid]
|
||||
connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready]
|
||||
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data]
|
||||
connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_fifo/dma_xfer_req] [get_bd_pins axi_ad9625_dma/s_axis_xfer_req]
|
||||
connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_ports ad9625_dma_intr]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9625_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9625_0_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9625_0_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9625_0_gt/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9625_spi/axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9625_gpio/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_ad9625_1_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_ad9625_1_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_ad9625_1_gt/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/ext_spi_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gpio/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_spi/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gpio/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_jesd/s_axi_aresetn]
|
||||
|
||||
# interconnect (gt es)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9625_0_gt/m_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9625_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9625_1_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/drp_clk]
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_gt/m_axi_aresetn]
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_gt/m_axi_aresetn]
|
||||
|
||||
# ila
|
||||
|
||||
set ila_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_rx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {512}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {256}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_rx_mon
|
||||
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins ila_rx_mon/CLK]
|
||||
connect_bd_net -net axi_ad9625_adc_wdata [get_bd_pins ila_rx_mon/probe0]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_data [get_bd_pins ila_rx_mon/probe1]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_data [get_bd_pins ila_rx_mon/probe2]
|
||||
connect_bd_net -net axi_ad9625_0_core_adc_sref [get_bd_pins axi_ad9625_0_core/adc_sref] [get_bd_pins ila_rx_mon/probe3]
|
||||
connect_bd_net -net axi_ad9625_1_core_adc_sref [get_bd_pins axi_ad9625_1_core/adc_sref] [get_bd_pins ila_rx_mon/probe4]
|
||||
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_core/s_axi/axi_lite] SEG_data_ad9625_0_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_gt/s_axi/axi_lite] SEG_data_ad9625_0_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44a91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_jesd/s_axi/Reg] SEG_data_ad9625_0_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44b10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_core/s_axi/axi_lite] SEG_data_ad9625_1_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44b60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_gt/s_axi/axi_lite] SEG_data_ad9625_1_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44b91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_jesd/s_axi/Reg] SEG_data_ad9625_1_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_dma/s_axi/axi_lite] SEG_data_ad9625_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_spi/axi_lite/Reg] SEG_data_ad9625_spi
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40030000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_gpio/s_axi/Reg] SEG_data_ad9625_gpio
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_0_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_1_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
|
||||
|
||||
# ad9625
|
||||
|
||||
set spi_csn_o [create_bd_port -dir O -from 3 -to 0 spi_csn_o]
|
||||
set spi_csn_i [create_bd_port -dir I -from 3 -to 0 spi_csn_i]
|
||||
set spi_clk_i [create_bd_port -dir I spi_clk_i]
|
||||
set spi_clk_o [create_bd_port -dir O spi_clk_o]
|
||||
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
|
||||
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
|
||||
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
|
||||
|
||||
set rx_ref_clk_0 [create_bd_port -dir I rx_ref_clk_0]
|
||||
set rx_data_0_p [create_bd_port -dir I -from 7 -to 0 rx_data_0_p]
|
||||
set rx_data_0_n [create_bd_port -dir I -from 7 -to 0 rx_data_0_n]
|
||||
set rx_sync_0 [create_bd_port -dir O rx_sync_0]
|
||||
|
||||
set rx_ref_clk_1 [create_bd_port -dir I rx_ref_clk_1]
|
||||
set rx_data_1_p [create_bd_port -dir I -from 7 -to 0 rx_data_1_p]
|
||||
set rx_data_1_n [create_bd_port -dir I -from 7 -to 0 rx_data_1_n]
|
||||
set rx_sync_1 [create_bd_port -dir O rx_sync_1]
|
||||
|
||||
set rx_sysref [create_bd_port -dir O rx_sysref]
|
||||
|
||||
set ad9625_spi_intr [create_bd_port -dir O ad9625_spi_intr]
|
||||
set ad9625_gpio_intr [create_bd_port -dir O ad9625_gpio_intr]
|
||||
set ad9625_dma_intr [create_bd_port -dir O ad9625_dma_intr]
|
||||
|
||||
set gpio_ad9625_i [create_bd_port -dir I -from 18 -to 0 gpio_ad9625_i]
|
||||
set gpio_ad9625_o [create_bd_port -dir O -from 18 -to 0 gpio_ad9625_o]
|
||||
set gpio_ad9625_t [create_bd_port -dir O -from 18 -to 0 gpio_ad9625_t]
|
||||
|
||||
set adc_clk [create_bd_port -dir O adc_clk]
|
||||
set adc_valid_0 [create_bd_port -dir O adc_valid_0]
|
||||
set adc_enable_0 [create_bd_port -dir O adc_enable_0]
|
||||
set adc_data_0 [create_bd_port -dir O -from 255 -to 0 adc_data_0]
|
||||
set adc_valid_1 [create_bd_port -dir O adc_valid_1]
|
||||
set adc_enable_1 [create_bd_port -dir O adc_enable_1]
|
||||
set adc_data_1 [create_bd_port -dir O -from 255 -to 0 adc_data_1]
|
||||
set adc_wr [create_bd_port -dir I adc_wr]
|
||||
set adc_wdata [create_bd_port -dir I -from 511 -to 0 adc_wdata]
|
||||
|
||||
# adc peripherals
|
||||
|
||||
set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
|
||||
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_0_core
|
||||
|
||||
set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9625_0_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
|
||||
|
||||
set axi_ad9625_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_0_gt]
|
||||
set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_0_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_0_gt
|
||||
|
||||
set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
|
||||
set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9625_1_core
|
||||
|
||||
set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9625_1_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
|
||||
|
||||
set axi_ad9625_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_1_gt]
|
||||
set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_1_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_1_gt
|
||||
|
||||
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
|
||||
|
||||
set axi_ad9625_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_ad9625_gpio]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {0}] $axi_ad9625_gpio
|
||||
set_property -dict [list CONFIG.C_GPIO_WIDTH {15}] $axi_ad9625_gpio
|
||||
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_ad9625_gpio
|
||||
|
||||
set axi_ad9625_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad9625_spi]
|
||||
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9625_spi
|
||||
set_property -dict [list CONFIG.C_NUM_SS_BITS {4}] $axi_ad9625_spi
|
||||
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi
|
||||
|
||||
p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 512 18
|
||||
|
||||
# additions to default configuration
|
||||
|
||||
set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect
|
||||
set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
|
||||
|
||||
# connections (spi and gpio)
|
||||
|
||||
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9625_spi/ss_i]
|
||||
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9625_spi/ss_o]
|
||||
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9625_spi/sck_i]
|
||||
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9625_spi/sck_o]
|
||||
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9625_spi/io0_i]
|
||||
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9625_spi/io0_o]
|
||||
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9625_spi/io1_i]
|
||||
|
||||
connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins axi_ad9625_gpio/gpio_io_i]
|
||||
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
|
||||
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
|
||||
|
||||
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_ports ad9625_spi_intr]
|
||||
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_ports ad9625_gpio_intr]
|
||||
|
||||
# connections (gt)
|
||||
|
||||
connect_bd_net -net axi_ad9625_0_gt_ref_clk_c [get_bd_pins axi_ad9625_0_gt/ref_clk_c] [get_bd_ports rx_ref_clk_0]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_data_p [get_bd_pins axi_ad9625_0_gt/rx_data_p] [get_bd_ports rx_data_0_p]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_data_n [get_bd_pins axi_ad9625_0_gt/rx_data_n] [get_bd_ports rx_data_0_n]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_sync [get_bd_pins axi_ad9625_0_gt/rx_sync] [get_bd_ports rx_sync_0]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_0_gt/rx_sysref] [get_bd_ports rx_sysref]
|
||||
|
||||
connect_bd_net -net axi_ad9625_1_gt_ref_clk_c [get_bd_pins axi_ad9625_1_gt/ref_clk_c] [get_bd_ports rx_ref_clk_1]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_data_p [get_bd_pins axi_ad9625_1_gt/rx_data_p] [get_bd_ports rx_data_1_p]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_data_n [get_bd_pins axi_ad9625_1_gt/rx_data_n] [get_bd_ports rx_data_1_n]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_sync [get_bd_pins axi_ad9625_1_gt/rx_sync] [get_bd_ports rx_sync_1]
|
||||
|
||||
# connections (adc)
|
||||
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_0_gt/rx_rst]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_0_jesd/rx_reset]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_1_jesd/rx_reset]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_gt/rx_clk_g]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_gt/rx_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_core/rx_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_jesd/rx_core_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_gt/rx_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_core/rx_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_jesd/rx_core_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_ports adc_clk]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_0_jesd/rx_sysref]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_1_jesd/rx_sysref]
|
||||
connect_bd_net -net axi_ad9625_0_core_raddr [get_bd_pins axi_ad9625_0_core/adc_raddr_out]
|
||||
connect_bd_net -net axi_ad9625_0_core_raddr [get_bd_pins axi_ad9625_0_core/adc_raddr_in]
|
||||
connect_bd_net -net axi_ad9625_0_core_raddr [get_bd_pins axi_ad9625_1_core/adc_raddr_in]
|
||||
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_gt_charisk [get_bd_pins axi_ad9625_0_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_0_jesd/gt_rxcharisk_in]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_gt_disperr [get_bd_pins axi_ad9625_0_gt/rx_gt_disperr] [get_bd_pins axi_ad9625_0_jesd/gt_rxdisperr_in]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_gt_notintable [get_bd_pins axi_ad9625_0_gt/rx_gt_notintable] [get_bd_pins axi_ad9625_0_jesd/gt_rxnotintable_in]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_gt_data [get_bd_pins axi_ad9625_0_gt/rx_gt_data] [get_bd_pins axi_ad9625_0_jesd/gt_rxdata_in]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst_done [get_bd_pins axi_ad9625_0_gt/rx_rst_done] [get_bd_pins axi_ad9625_0_jesd/rx_reset_done]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_ip_comma_align [get_bd_pins axi_ad9625_0_gt/rx_ip_comma_align] [get_bd_pins axi_ad9625_0_jesd/rxencommaalign_out]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_ip_sync [get_bd_pins axi_ad9625_0_gt/rx_ip_sync] [get_bd_pins axi_ad9625_0_jesd/rx_sync]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_ip_sof [get_bd_pins axi_ad9625_0_gt/rx_ip_sof] [get_bd_pins axi_ad9625_0_jesd/rx_start_of_frame]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_ip_data [get_bd_pins axi_ad9625_0_gt/rx_ip_data] [get_bd_pins axi_ad9625_0_jesd/rx_tdata]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_gt_charisk [get_bd_pins axi_ad9625_1_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_1_jesd/gt_rxcharisk_in]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_gt_disperr [get_bd_pins axi_ad9625_1_gt/rx_gt_disperr] [get_bd_pins axi_ad9625_1_jesd/gt_rxdisperr_in]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_gt_notintable [get_bd_pins axi_ad9625_1_gt/rx_gt_notintable] [get_bd_pins axi_ad9625_1_jesd/gt_rxnotintable_in]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_gt_data [get_bd_pins axi_ad9625_1_gt/rx_gt_data] [get_bd_pins axi_ad9625_1_jesd/gt_rxdata_in]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_rst_done [get_bd_pins axi_ad9625_1_gt/rx_rst_done] [get_bd_pins axi_ad9625_1_jesd/rx_reset_done]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_ip_comma_align [get_bd_pins axi_ad9625_1_gt/rx_ip_comma_align] [get_bd_pins axi_ad9625_1_jesd/rxencommaalign_out]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_ip_sync [get_bd_pins axi_ad9625_1_gt/rx_ip_sync] [get_bd_pins axi_ad9625_1_jesd/rx_sync]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_ip_sof [get_bd_pins axi_ad9625_1_gt/rx_ip_sof] [get_bd_pins axi_ad9625_1_jesd/rx_start_of_frame]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_ip_data [get_bd_pins axi_ad9625_1_gt/rx_ip_data] [get_bd_pins axi_ad9625_1_jesd/rx_tdata]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_data [get_bd_pins axi_ad9625_0_gt/rx_data] [get_bd_pins axi_ad9625_0_core/rx_data]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_data [get_bd_pins axi_ad9625_1_gt/rx_data] [get_bd_pins axi_ad9625_1_core/rx_data]
|
||||
connect_bd_net -net axi_ad9625_0_core_adc_valid [get_bd_pins axi_ad9625_0_core/adc_valid] [get_bd_ports adc_valid_0]
|
||||
connect_bd_net -net axi_ad9625_0_core_adc_enable [get_bd_pins axi_ad9625_0_core/adc_enable] [get_bd_ports adc_enable_0]
|
||||
connect_bd_net -net axi_ad9625_0_core_adc_data [get_bd_pins axi_ad9625_0_core/adc_data] [get_bd_ports adc_data_0]
|
||||
connect_bd_net -net axi_ad9625_1_core_adc_valid [get_bd_pins axi_ad9625_1_core/adc_valid] [get_bd_ports adc_valid_1]
|
||||
connect_bd_net -net axi_ad9625_1_core_adc_enable [get_bd_pins axi_ad9625_1_core/adc_enable] [get_bd_ports adc_enable_1]
|
||||
connect_bd_net -net axi_ad9625_1_core_adc_data [get_bd_pins axi_ad9625_1_core/adc_data] [get_bd_ports adc_data_1]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_fifo/adc_rst] [get_bd_pins axi_ad9625_0_gt/rx_rst]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_fifo/adc_clk] [get_bd_pins axi_ad9625_0_gt/rx_clk_g]
|
||||
connect_bd_net -net axi_ad9625_adc_wr [get_bd_ports adc_wr] [get_bd_pins axi_ad9625_fifo/adc_wr]
|
||||
connect_bd_net -net axi_ad9625_adc_wdata [get_bd_ports adc_wdata] [get_bd_pins axi_ad9625_fifo/adc_wdata]
|
||||
connect_bd_net -net axi_ad9625_adc_wovf [get_bd_pins axi_ad9625_0_core/adc_dovf] [get_bd_pins axi_ad9625_fifo/adc_wovf]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/s_axis_aclk]
|
||||
connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fifo/dma_wr] [get_bd_pins axi_ad9625_dma/s_axis_valid]
|
||||
connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready]
|
||||
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data]
|
||||
connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_fifo/dma_xfer_req] [get_bd_pins axi_ad9625_dma/s_axis_xfer_req]
|
||||
connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_ports ad9625_dma_intr]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9625_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9625_0_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9625_0_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9625_0_gt/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9625_spi/axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9625_gpio/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_ad9625_1_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_ad9625_1_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_ad9625_1_gt/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/ext_spi_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gpio/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_spi/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gpio/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_jesd/s_axi_aresetn]
|
||||
|
||||
# interconnect (gt es)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9625_0_gt/m_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9625_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9625_1_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/drp_clk]
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_gt/m_axi_aresetn]
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_gt/m_axi_aresetn]
|
||||
|
||||
# ila
|
||||
|
||||
set ila_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_rx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {512}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {256}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_rx_mon
|
||||
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins ila_rx_mon/CLK]
|
||||
connect_bd_net -net axi_ad9625_adc_wdata [get_bd_pins ila_rx_mon/probe0]
|
||||
connect_bd_net -net axi_ad9625_0_gt_rx_data [get_bd_pins ila_rx_mon/probe1]
|
||||
connect_bd_net -net axi_ad9625_1_gt_rx_data [get_bd_pins ila_rx_mon/probe2]
|
||||
connect_bd_net -net axi_ad9625_0_core_adc_sref [get_bd_pins axi_ad9625_0_core/adc_sref] [get_bd_pins ila_rx_mon/probe3]
|
||||
connect_bd_net -net axi_ad9625_1_core_adc_sref [get_bd_pins axi_ad9625_1_core/adc_sref] [get_bd_pins ila_rx_mon/probe4]
|
||||
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_core/s_axi/axi_lite] SEG_data_ad9625_0_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_gt/s_axi/axi_lite] SEG_data_ad9625_0_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44a91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_jesd/s_axi/Reg] SEG_data_ad9625_0_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44b10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_core/s_axi/axi_lite] SEG_data_ad9625_1_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44b60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_gt/s_axi/axi_lite] SEG_data_ad9625_1_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44b91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_jesd/s_axi/Reg] SEG_data_ad9625_1_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_dma/s_axi/axi_lite] SEG_data_ad9625_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_spi/axi_lite/Reg] SEG_data_ad9625_spi
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40030000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_gpio/s_axi/Reg] SEG_data_ad9625_gpio
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_0_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_1_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad9625x2_fmc_spi (
|
||||
module fmcadc5_spi (
|
||||
|
||||
spi_csn_0,
|
||||
spi_csn_1,
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
|
||||
source ../common/ad9625x2_fmc_bd.tcl
|
||||
source ../common/fmcadc5_bd.tcl
|
||||
|
||||
|
||||
|
|
@ -4,10 +4,10 @@
|
|||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
|
||||
adi_project_create ad9625x2_fmc_vc707
|
||||
adi_project_files ad9625x2_fmc_vc707 [list \
|
||||
adi_project_create fmcadc5_vc707
|
||||
adi_project_files fmcadc5_vc707 [list \
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"../common/ad9625x2_fmc_spi.v" \
|
||||
"../common/fmcadc5_spi.v" \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
|
||||
|
|
@ -15,6 +15,6 @@ adi_project_files ad9625x2_fmc_vc707 [list \
|
|||
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
|
||||
|
||||
adi_project_run ad9625x2_fmc_vc707
|
||||
adi_project_run fmcadc5_vc707
|
||||
|
||||
|
||||
|
|
@ -369,7 +369,7 @@ module system_top (
|
|||
drst_0, // 1
|
||||
arst_0})); // 0
|
||||
|
||||
ad9625x2_fmc_spi i_ad9625x2_fmc_spi (
|
||||
fmcadc5_spi i_fmcadc5_spi (
|
||||
.spi_csn_0 (spi_csn_0),
|
||||
.spi_csn_1 (spi_csn_1),
|
||||
.spi_clk (spi_clk),
|
||||
|
|
@ -319,8 +319,8 @@
|
|||
|
||||
# xadc
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source
|
||||
# connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source
|
||||
# connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn]
|
||||
connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0]
|
||||
|
|
@ -332,7 +332,7 @@
|
|||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_controller/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
|
||||
# connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi]
|
||||
|
|
@ -438,7 +438,7 @@
|
|||
create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
|
||||
# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
|
||||
create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/s_axi/axi_lite] SEG_foc_controller_f_c
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
|
|
|
|||
Loading…
Reference in New Issue