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fmcjesdadc1/a5gt: 14.1 updates

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Rejeesh Kutty 2015-04-03 14:54:15 -04:00
parent 3aac5f9494
commit 0a8823361f
1 changed files with 6 additions and 5 deletions
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11
projects/fmcjesdadc1/a5gt/system_top.v
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@ -165,6 +165,9 @@ module system_top (
reg [ 63:0] dma0_wdata = 'd0;
reg dma1_wr = 'd0;
reg [ 63:0] dma1_wdata = 'd0;
reg [ 3:0] phy_rst_cnt = 0;
reg phy_rst_reg = 0;
// internal clocks and resets
@ -210,8 +213,6 @@ module system_top (
wire rx_pll_locked_s;
wire [ 15:0] rx_xcvr_status_s;
reg [ 3:0] phy_rst_cnt = 0;
reg phy_rst_reg = 0;
// ethernet transmit clock
assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
@ -220,7 +221,7 @@ module system_top (
assign eth_phy_resetn = phy_rst_reg;
always@ (posedge eth_mdc) begin
phy_rst_cnt <= phy_rst_cnt +1;
phy_rst_cnt <= phy_rst_cnt + 4'd1;
if (phy_rst_cnt == 4'h0) begin
phy_rst_reg <= sys_pll_locked_s;
end
@ -413,8 +414,8 @@ module system_top (
.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
.sys_jesd204b_s1_locked_export (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
.sys_jesd204b_s1_locked_rx_is_lockedtodata (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_rx_cal_busy (rx_cal_busy_s),
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),