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axi_ad9152: Added CDC and reset constraints

main
Adrian Costina 2015-04-23 10:21:52 +03:00
parent 3526145992
commit 09f05cf8e9
2 changed files with 42 additions and 2 deletions
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42
library/axi_ad9152/axi_ad9152_constr.xdc
View File

@ -1,6 +1,44 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad9152_clk [get_clocks -of_objects [get_ports tx_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad9152_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

2
library/axi_ad9152/axi_ad9152_ip.tcl
View File

@ -20,9 +20,11 @@ adi_ip_files axi_ad9152 [list \
"axi_ad9152_channel.v" \
"axi_ad9152_core.v" \
"axi_ad9152_if.v" \
"axi_ad9152_constr.v" \
"axi_ad9152.v" ]
adi_ip_properties axi_ad9152
adi_ip_constraints axi_ad9152 [list \
"axi_ad9152_constr.xdc" ]