adrv9009zu11eg: Make the project more parametrizable
parent
2e4ac278eb
commit
09ad67bfd7
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@ -6,7 +6,14 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
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set p_device "xczu11eg-ffvf1517-2-i"
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set sys_zynq 2
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adi_project adrv9009zu11eg
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adi_project adrv9009zu11eg 0 [list \
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JESD_RX_M 8 \
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JESD_RX_L 4 \
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JESD_TX_M 8 \
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JESD_TX_L 8 \
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JESD_OBS_M 4 \
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JESD_OBS_L 4 \
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]
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adi_project_files adrv9009zu11eg [list \
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"system_top.v" \
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"../common/adrv9009zu11eg_spi.v" \
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@ -158,29 +158,30 @@ ad_connect sys_concat_intc_0/In0 GND
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# ADRV9009 Specific Connections
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# TX parameters
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set TX_NUM_OF_LANES 8 ; # L
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set TX_NUM_OF_CONVERTERS 8 ; # M
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set TX_NUM_OF_LANES $ad_project_params(JESD_TX_L) ; # L
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set TX_NUM_OF_CONVERTERS $ad_project_params(JESD_TX_M) ; # M
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set TX_SAMPLES_PER_FRAME 1 ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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set TX_SAMPLES_PER_CHANNEL [expr ($TX_NUM_OF_LANES * 32) / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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# RX parameters
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 8 ; # M
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set RX_NUM_OF_LANES $ad_project_params(JESD_RX_L) ; # L
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set RX_NUM_OF_CONVERTERS $ad_project_params(JESD_RX_M) ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL 1 ; # L * 32 / (M * N)
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set RX_SAMPLES_PER_CHANNEL [expr ($RX_NUM_OF_LANES * 32) / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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# RX Observation parameters
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set OBS_NUM_OF_LANES 4 ; # L
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set OBS_NUM_OF_CONVERTERS 4 ; # M
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set OBS_NUM_OF_LANES $ad_project_params(JESD_OBS_L) ; # L
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set OBS_NUM_OF_CONVERTERS $ad_project_params(JESD_OBS_M) ; # M
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set OBS_SAMPLES_PER_FRAME 1 ; # S
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set OBS_SAMPLE_WIDTH 16 ; # N/NP
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set OBS_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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set OBS_SAMPLES_PER_CHANNEL [expr ($OBS_NUM_OF_LANES * 32) / ($OBS_NUM_OF_CONVERTERS * $OBS_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_rtl_1
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ddr4_ref_1
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@ -201,7 +202,7 @@ ad_connect ddr4_ref_1 ddr4_1/C0_SYS_CLK
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set dac_fifo_name axi_tx_fifo
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set dac_data_width [expr 32*$TX_NUM_OF_LANES]
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set dac_dma_data_width 256
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set dac_dma_data_width [expr 32*$TX_NUM_OF_LANES]
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set dac_fifo_address_width 31
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ad_ip_instance axi_dacfifo $dac_fifo_name
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@ -278,7 +279,7 @@ ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_som_rx_dma MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance axi_adxcvr axi_adrv9009_som_obs_xcvr
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@ -286,7 +287,7 @@ ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_som_obs_jesd $OBS_NUM_OF_LANES
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adi_axi_jesd204_rx_create axi_adrv9009_som_obs_jesd $OBS_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_som_obs_cpack [list \
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NUM_OF_CHANNELS $OBS_NUM_OF_CONVERTERS \
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@ -309,7 +310,7 @@ ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_som_obs_dma MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$OBS_NUM_OF_LANES]
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance util_adxcvr util_adrv9009_som_xcvr
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