From 09a05fe9d8a16757cb8bc6df1255a829cd355d64 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 19 May 2015 12:43:39 -0400 Subject: [PATCH] ad9652: delay changes --- library/axi_ad9652/axi_ad9652.v | 70 ++++++++++++---------- library/axi_ad9652/axi_ad9652_if.v | 96 +++++------------------------- 2 files changed, 54 insertions(+), 112 deletions(-) diff --git a/library/axi_ad9652/axi_ad9652.v b/library/axi_ad9652/axi_ad9652.v index f146ad16a..080bc1567 100644 --- a/library/axi_ad9652/axi_ad9652.v +++ b/library/axi_ad9652/axi_ad9652.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -96,7 +94,6 @@ module axi_ad9652 ( parameter PCORE_DEVICE_TYPE = 0; parameter PCORE_ADC_DP_DISABLE = 0; parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; - parameter C_S_AXI_MIN_SIZE = 32'hffff; // adc interface (clk, data, over-range) @@ -161,6 +158,7 @@ module axi_ad9652 ( wire adc_rst; wire up_rstn; wire up_clk; + wire delay_rst; // internal signals @@ -177,17 +175,13 @@ module axi_ad9652 ( wire [ 1:0] up_status_or_s; wire adc_ddr_edgesel_s; wire adc_status_s; - wire delay_rst_s; - wire delay_sel_s; - wire delay_rwn_s; - wire [ 7:0] delay_addr_s; - wire [ 4:0] delay_wdata_s; - wire [ 4:0] delay_rdata_s; - wire delay_ack_t_s; + wire [16:0] up_dld_s; + wire [84:0] up_dwdata_s; + wire [84:0] up_drdata_s; wire delay_locked_s; - wire [31:0] up_rdata_s[0:2]; - wire up_rack_s[0:2]; - wire up_wack_s[0:2]; + wire [31:0] up_rdata_s[0:3]; + wire up_rack_s[0:3]; + wire up_wack_s[0:3]; wire up_wreq_s; wire [13:0] up_waddr_s; wire [31:0] up_wdata_s; @@ -218,9 +212,9 @@ module axi_ad9652 ( up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1]; up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1]; up_status_or <= up_status_or_s[0] | up_status_or_s[1]; - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; - up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; - up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; end end @@ -301,14 +295,12 @@ module axi_ad9652 ( .adc_or_b (adc_or_b_s), .adc_status (adc_status_s), .adc_ddr_edgesel (adc_ddr_edgesel_s), + .up_clk (up_clk), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), .delay_clk (delay_clk), - .delay_rst (delay_rst_s), - .delay_sel (delay_sel_s), - .delay_rwn (delay_rwn_s), - .delay_addr (delay_addr_s), - .delay_wdata (delay_wdata_s), - .delay_rdata (delay_rdata_s), - .delay_ack_t (delay_ack_t_s), + .delay_rst (delay_rst), .delay_locked (delay_locked_s)); // common processor control @@ -321,21 +313,15 @@ module axi_ad9652 ( .adc_ddr_edgesel (adc_ddr_edgesel_s), .adc_pin_mode (), .adc_status (adc_status_s), + .adc_sync_status (1'd0), .adc_status_ovf (adc_dovf), .adc_status_unf (adc_dunf), .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sync (), .up_status_pn_err (up_status_pn_err), .up_status_pn_oos (up_status_pn_oos), .up_status_or (up_status_or), - .delay_clk (delay_clk), - .delay_rst (delay_rst_s), - .delay_sel (delay_sel_s), - .delay_rwn (delay_rwn_s), - .delay_addr (delay_addr_s), - .delay_wdata (delay_wdata_s), - .delay_rdata (delay_rdata_s), - .delay_ack_t (delay_ack_t_s), - .delay_locked (delay_locked_s), .drp_clk (1'd0), .drp_rst (), .drp_sel (), @@ -360,6 +346,26 @@ module axi_ad9652 ( .up_rdata (up_rdata_s[2]), .up_rack (up_rack_s[2])); + // adc delay control + + up_delay_cntrl #(.IO_WIDTH(17), .IO_BASEADDR(6'h02)) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + // up bus interface up_axi i_up_axi ( diff --git a/library/axi_ad9652/axi_ad9652_if.v b/library/axi_ad9652/axi_ad9652_if.v index 0ff3b69c9..14d12aa0e 100644 --- a/library/axi_ad9652/axi_ad9652_if.v +++ b/library/axi_ad9652/axi_ad9652_if.v @@ -68,14 +68,12 @@ module axi_ad9652_if ( // delay control signals + up_clk, + up_dld, + up_dwdata, + up_drdata, delay_clk, delay_rst, - delay_sel, - delay_rwn, - delay_addr, - delay_wdata, - delay_rdata, - delay_ack_t, delay_locked); // This parameter controls the buffer type based on the target device. @@ -107,14 +105,12 @@ module axi_ad9652_if ( // delay control signals + input up_clk; + input [16:0] up_dld; + input [84:0] up_dwdata; + output [84:0] up_drdata; input delay_clk; input delay_rst; - input delay_sel; - input delay_rwn; - input [ 7:0] delay_addr; - input [ 4:0] delay_wdata; - output [ 4:0] delay_rdata; - output delay_ack_t; output delay_locked; // internal registers @@ -130,13 +126,9 @@ module axi_ad9652_if ( reg [15:0] adc_data_b = 'd0; reg adc_or_a = 'd0; reg adc_or_b = 'd0; - reg [16:0] delay_ld = 'd0; - reg delay_ack_t = 'd0; - reg [ 4:0] delay_rdata = 'd0; // internal signals - wire [ 4:0] delay_rdata_s[16:0]; wire [15:0] adc_data_p_s; wire [15:0] adc_data_n_s; wire adc_or_p_s; @@ -172,64 +164,6 @@ module axi_ad9652_if ( end end - // delay write interface, each delay element can be individually - // addressed, and a delay value can be directly loaded (no inc/dec stuff) - - always @(posedge delay_clk) begin - if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin - case (delay_addr) - 8'h10: delay_ld <= 17'h10000; - 8'h0f: delay_ld <= 17'h08000; - 8'h0e: delay_ld <= 17'h04000; - 8'h0d: delay_ld <= 17'h02000; - 8'h0c: delay_ld <= 17'h01000; - 8'h0b: delay_ld <= 17'h00800; - 8'h0a: delay_ld <= 17'h00400; - 8'h09: delay_ld <= 17'h00200; - 8'h08: delay_ld <= 17'h00100; - 8'h07: delay_ld <= 17'h00080; - 8'h06: delay_ld <= 17'h00040; - 8'h05: delay_ld <= 17'h00020; - 8'h04: delay_ld <= 17'h00010; - 8'h03: delay_ld <= 17'h00008; - 8'h02: delay_ld <= 17'h00004; - 8'h01: delay_ld <= 17'h00002; - 8'h00: delay_ld <= 17'h00001; - default: delay_ld <= 17'h00000; - endcase - end else begin - delay_ld <= 15'h0000; - end - end - - // delay read interface, a delay ack toggle is used to transfer data to the - // processor side- delay locked is independently transferred - - always @(posedge delay_clk) begin - case (delay_addr) - 8'h10: delay_rdata <= delay_rdata_s[16]; - 8'h0f: delay_rdata <= delay_rdata_s[15]; - 8'h0e: delay_rdata <= delay_rdata_s[14]; - 8'h0d: delay_rdata <= delay_rdata_s[13]; - 8'h0c: delay_rdata <= delay_rdata_s[12]; - 8'h0b: delay_rdata <= delay_rdata_s[11]; - 8'h0a: delay_rdata <= delay_rdata_s[10]; - 8'h09: delay_rdata <= delay_rdata_s[ 9]; - 8'h08: delay_rdata <= delay_rdata_s[ 8]; - 8'h07: delay_rdata <= delay_rdata_s[ 7]; - 8'h06: delay_rdata <= delay_rdata_s[ 6]; - 8'h05: delay_rdata <= delay_rdata_s[ 5]; - 8'h04: delay_rdata <= delay_rdata_s[ 4]; - 8'h03: delay_rdata <= delay_rdata_s[ 3]; - 8'h02: delay_rdata <= delay_rdata_s[ 2]; - 8'h01: delay_rdata <= delay_rdata_s[ 1]; - 8'h00: delay_rdata <= delay_rdata_s[ 0]; - default: delay_rdata <= 5'd0; - endcase - if (delay_sel == 1'b1) begin - delay_ack_t <= ~delay_ack_t; - end - end // data interface @@ -245,11 +179,12 @@ module axi_ad9652_if ( .rx_data_in_n (adc_data_in_n[l_inst]), .rx_data_p (adc_data_p_s[l_inst]), .rx_data_n (adc_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_dld[l_inst]), + .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), .delay_clk (delay_clk), .delay_rst (delay_rst), - .delay_ld (delay_ld[l_inst]), - .delay_wdata (delay_wdata), - .delay_rdata (delay_rdata_s[l_inst]), .delay_locked ()); end endgenerate @@ -266,11 +201,12 @@ module axi_ad9652_if ( .rx_data_in_n (adc_or_in_n), .rx_data_p (adc_or_p_s), .rx_data_n (adc_or_n_s), + .up_clk (up_clk), + .up_dld (up_dld[16]), + .up_dwdata (up_dwdata[84:80]), + .up_drdata (up_drdata[84:80]), .delay_clk (delay_clk), .delay_rst (delay_rst), - .delay_ld (delay_ld[16]), - .delay_wdata (delay_wdata), - .delay_rdata (delay_rdata_s[16]), .delay_locked (delay_locked)); // clock